Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header

2022-01-26 Thread Lucas De Marchi

On Mon, Jan 24, 2022 at 06:08:21PM -0800, Matt Roper wrote:

The OA unit registers are only used by the perf code; move them to their
own header file.

Cc: Jani Nikula 
Cc: Umesh Nerlige Ramappa 
Cc: Lionel Landwerlin 
Signed-off-by: Matt Roper 


I checked the output from git show --color-moved to help and indeed this
is just moving the registers. Also, looking at the register names, they
all seem to be OA/perf related.


Reviewed-by: Lucas De Marchi 

Lucas De Marchi


[Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header

2022-01-24 Thread Matt Roper
The OA unit registers are only used by the perf code; move them to their
own header file.

Cc: Jani Nikula 
Cc: Umesh Nerlige Ramappa 
Cc: Lionel Landwerlin 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gvt/scheduler.c |   1 +
 drivers/gpu/drm/i915/i915_perf.c |   1 +
 drivers/gpu/drm/i915/i915_perf_oa_regs.h | 497 +++
 drivers/gpu/drm/i915/i915_reg.h  | 485 --
 4 files changed, 499 insertions(+), 485 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_perf_oa_regs.h

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 42a0c9ae0a73..ecd90dbd9544 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -43,6 +43,7 @@
 
 #include "i915_drv.h"
 #include "i915_gem_gtt.h"
+#include "i915_perf_oa_regs.h"
 #include "gvt.h"
 
 #define RING_CTX_OFF(x) \
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index da4045c9df4e..20af83517cb1 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -208,6 +208,7 @@
 
 #include "i915_drv.h"
 #include "i915_perf.h"
+#include "i915_perf_oa_regs.h"
 
 /* HW requires this to be a power of two, between 128k and 16M, though driver
  * is currently generally designed assuming the largest 16M size is used such
diff --git a/drivers/gpu/drm/i915/i915_perf_oa_regs.h 
b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
new file mode 100644
index ..5896ed43f5c4
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_perf_oa_regs.h
@@ -0,0 +1,497 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PERF_OA_REGS__
+#define __INTEL_PERF_OA_REGS__
+
+#include "i915_reg_defs.h"
+
+#define GEN7_OACONTROL _MMIO(0x2360)
+#define  GEN7_OACONTROL_CTX_MASK   0xF000
+#define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F
+#define  GEN7_OACONTROL_TIMER_PERIOD_SHIFT  6
+#define  GEN7_OACONTROL_TIMER_ENABLE   (1 << 5)
+#define  GEN7_OACONTROL_FORMAT_A13 (0 << 2)
+#define  GEN7_OACONTROL_FORMAT_A29 (1 << 2)
+#define  GEN7_OACONTROL_FORMAT_A13_B8_C8(2 << 2)
+#define  GEN7_OACONTROL_FORMAT_A29_B8_C8(3 << 2)
+#define  GEN7_OACONTROL_FORMAT_B4_C8   (4 << 2)
+#define  GEN7_OACONTROL_FORMAT_A45_B8_C8(5 << 2)
+#define  GEN7_OACONTROL_FORMAT_B4_C8_A16(6 << 2)
+#define  GEN7_OACONTROL_FORMAT_C4_B8   (7 << 2)
+#define  GEN7_OACONTROL_FORMAT_SHIFT   2
+#define  GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1)
+#define  GEN7_OACONTROL_ENABLE (1 << 0)
+
+#define GEN8_OACTXID _MMIO(0x2364)
+
+#define GEN8_OA_DEBUG _MMIO(0x2B04)
+#define  GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS(1 << 5)
+#define  GEN9_OA_DEBUG_INCLUDE_CLK_RATIO   (1 << 6)
+#define  GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS  (1 << 2)
+#define  GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS   (1 << 1)
+
+#define GEN8_OACONTROL _MMIO(0x2B00)
+#define  GEN8_OA_REPORT_FORMAT_A12 (0 << 2)
+#define  GEN8_OA_REPORT_FORMAT_A12_B8_C8(2 << 2)
+#define  GEN8_OA_REPORT_FORMAT_A36_B8_C8(5 << 2)
+#define  GEN8_OA_REPORT_FORMAT_C4_B8   (7 << 2)
+#define  GEN8_OA_REPORT_FORMAT_SHIFT   2
+#define  GEN8_OA_SPECIFIC_CONTEXT_ENABLE(1 << 1)
+#define  GEN8_OA_COUNTER_ENABLE (1 << 0)
+
+#define GEN8_OACTXCONTROL _MMIO(0x2360)
+#define  GEN8_OA_TIMER_PERIOD_MASK 0x3F
+#define  GEN8_OA_TIMER_PERIOD_SHIFT2
+#define  GEN8_OA_TIMER_ENABLE  (1 << 1)
+#define  GEN8_OA_COUNTER_RESUME(1 << 0)
+
+#define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
+#define  GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3)
+#define  GEN7_OABUFFER_EDGE_TRIGGER(1 << 2)
+#define  GEN7_OABUFFER_STOP_RESUME_ENABLE   (1 << 1)
+#define  GEN7_OABUFFER_RESUME  (1 << 0)
+
+#define GEN8_OABUFFER_UDW _MMIO(0x23b4)
+#define GEN8_OABUFFER _MMIO(0x2b14)
+#define  GEN8_OABUFFER_MEM_SELECT_GGTT  (1 << 0)  /* 0: PPGTT, 1: GGTT */
+
+#define GEN7_OASTATUS1 _MMIO(0x2364)
+#define  GEN7_OASTATUS1_TAIL_MASK  0xffc0
+#define  GEN7_OASTATUS1_COUNTER_OVERFLOW(1 << 2)
+#define  GEN7_OASTATUS1_OABUFFER_OVERFLOW   (1 << 1)
+#define  GEN7_OASTATUS1_REPORT_LOST(1 << 0)
+
+#define GEN7_OASTATUS2 _MMIO(0x2368)
+#define  GEN7_OASTATUS2_HEAD_MASK   0xffc0
+#define  GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+
+#define GEN8_OASTATUS _MMIO(0x2b08)
+#define  GEN8_OASTATUS_TAIL_POINTER_WRAP(1 << 17)
+#define  GEN8_OASTATUS_HEAD_POINTER_WRAP(1 << 16)
+#define  GEN8_OASTATUS_OVERRUN_STATUS  (1 << 3)
+#define  GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
+#define  GEN8_OASTATUS_OABUFFER_OVERFLOW(1 << 1)
+#define  GEN8_OASTATUS_REPORT_LOST (1 << 0)
+
+#define GEN8_OAHEADPTR _MMIO(0x2B0C)
+#define GEN8_OAHEADPTR_MASK0xffc0
+#define GEN8_OATAILPTR _MMIO(0x2B10)
+#define GEN8_OATAILPTR_MASK0xffc0
+
+#define