Re: [Intel-gfx] [PATCH v3] drm/i915/mtl/gsc: Add a gsc_info debugfs

[Teres Alexis, Alan Previn]

On Mon, 2023-06-05 at 21:32 -0700, Ceraolo Spurio, Daniele wrote:
> Add a new debugfs to dump information about the GSC. This includes:
> 
> - the FW path and SW tracking status;
> - the release, security and compatibility versions;
> - the HECI1 status registers.
> 
> Note that those are the same registers that the mei driver dumps in
> their own status sysfs on DG2 (where mei owns the GSC).
> 
alan:snip


all looks good. (ofc we do have to follow up on those 2 actions from last rev's
conversation (that we agreed should be separate patch). For now, this patch is

Reviewed-by: Alan Previn 

[Intel-gfx] [PATCH v3] drm/i915/mtl/gsc: Add a gsc_info debugfs

[Daniele Ceraolo Spurio]

Add a new debugfs to dump information about the GSC. This includes:

- the FW path and SW tracking status;
- the release, security and compatibility versions;
- the HECI1 status registers.

Note that those are the same registers that the mei driver dumps in
their own status sysfs on DG2 (where mei owns the GSC).

To make it simpler to loop through the status register, the code has
been update to use a PICK macro and the existing code using the regs had
been adapted to match.

v2: fix includes and copyright dates (Alan)
v3: actually fix the includes

Signed-off-by: Daniele Ceraolo Spurio 
Cc: Alan Previn 
Cc: John Harrison 
---
 drivers/gpu/drm/i915/Makefile |  3 +-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c | 29 +--
 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c | 48 ++-
 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h |  2 +
 .../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c | 39 +++
 .../gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h | 14 ++
 drivers/gpu/drm/i915/gt/uc/intel_huc.c|  6 +--
 drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c |  2 +
 drivers/gpu/drm/i915/i915_reg.h   | 26 +-
 9 files changed, 144 insertions(+), 25 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1c9ed4c52760..b6c54fb0b4cc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -192,7 +192,8 @@ i915-y += \
  gt/uc/intel_gsc_fw.o \
  gt/uc/intel_gsc_proxy.o \
  gt/uc/intel_gsc_uc.o \
- gt/uc/intel_gsc_uc_heci_cmd_submit.o\
+ gt/uc/intel_gsc_uc_debugfs.o \
+ gt/uc/intel_gsc_uc_heci_cmd_submit.o \
  gt/uc/intel_guc.o \
  gt/uc/intel_guc_ads.o \
  gt/uc/intel_guc_capture.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
index 7d48d59011c8..b069459e2596 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c
@@ -12,36 +12,31 @@
 #include "intel_gsc_binary_headers.h"
 #include "intel_gsc_fw.h"
 #include "intel_gsc_uc_heci_cmd_submit.h"
-
-#define GSC_FW_STATUS_REG  _MMIO(0x116C40)
-#define GSC_FW_CURRENT_STATE   REG_GENMASK(3, 0)
-#define   GSC_FW_CURRENT_STATE_RESET   0
-#define   GSC_FW_PROXY_STATE_NORMAL5
-#define GSC_FW_INIT_COMPLETE_BIT   REG_BIT(9)
+#include "i915_reg.h"
 
 static bool gsc_is_in_reset(struct intel_uncore *uncore)
 {
-   u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+   u32 fw_status = intel_uncore_read(uncore, 
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
 
-   return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
-  GSC_FW_CURRENT_STATE_RESET;
+   return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==
+   HECI1_FWSTS1_CURRENT_STATE_RESET;
 }
 
 bool intel_gsc_uc_fw_proxy_init_done(struct intel_gsc_uc *gsc)
 {
struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
-   u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+   u32 fw_status = intel_uncore_read(uncore, 
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
 
-   return REG_FIELD_GET(GSC_FW_CURRENT_STATE, fw_status) ==
-  GSC_FW_PROXY_STATE_NORMAL;
+   return REG_FIELD_GET(HECI1_FWSTS1_CURRENT_STATE, fw_status) ==
+  HECI1_FWSTS1_PROXY_STATE_NORMAL;
 }
 
 bool intel_gsc_uc_fw_init_done(struct intel_gsc_uc *gsc)
 {
struct intel_uncore *uncore = gsc_uc_to_gt(gsc)->uncore;
-   u32 fw_status = intel_uncore_read(uncore, GSC_FW_STATUS_REG);
+   u32 fw_status = intel_uncore_read(uncore, 
HECI_FWSTS(MTL_GSC_HECI1_BASE, 1));
 
-   return fw_status & GSC_FW_INIT_COMPLETE_BIT;
+   return fw_status & HECI1_FWSTS1_INIT_COMPLETE;
 }
 
 static inline u32 cpd_entry_offset(const struct intel_gsc_cpd_entry *entry)
@@ -293,9 +288,9 @@ static int gsc_fw_load_prepare(struct intel_gsc_uc *gsc)
 static int gsc_fw_wait(struct intel_gt *gt)
 {
return intel_wait_for_register(gt->uncore,
-  GSC_FW_STATUS_REG,
-  GSC_FW_INIT_COMPLETE_BIT,
-  GSC_FW_INIT_COMPLETE_BIT,
+  HECI_FWSTS(MTL_GSC_HECI1_BASE, 1),
+  HECI1_FWSTS1_INIT_COMPLETE,
+  HECI1_FWSTS1_INIT_COMPLETE,
   500);
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
index 4fe639a80564..6826aa5d6985 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.c
@@ -7,10 +7,11 @@
 
 #include "gt/intel_gt.h"
 #include