Re: [Intel-gfx] [PATCH v3 05/11] drm/i915/dsb: Register definition of DSB registers.

2019-08-29 Thread Animesh Manna 

Hi,


On 8/28/2019 10:32 PM, Sharma, Shashank wrote:


On 8/28/2019 12:40 AM, Animesh Manna wrote:

Added key register definitions of DSB.

dsb-ctrl register is required to enable dsb-engine.

head-ptr register hold the head of buffer address from where the
execution will start.

Programming tail-ptr register is a trigger point to start execution.

Cc: Uma Shankar 
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
---
  drivers/gpu/drm/i915/i915_reg.h | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h 
b/drivers/gpu/drm/i915/i915_reg.h

index 02e1ef10c47e..71c6c2380443 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11564,4 +11564,19 @@ enum skl_power_gate {
  #define PORT_TX_DFLEXDPCSSS(fia)_MMIO_FIA((fia), 0x00894)
  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)(1 << (tc_port))
  +/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE0x70B00
+#define DSBSL_INSTANCE(pipe, id)(_DSBSL_INSTANCE_BASE + \
+ (pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
+#define DSB_CTRL(pipe, id)_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define   DSB_ENABLE(1 << 31)
+#define   DSB_BUFFER_REITERATE(1 << 29)
+#define   DSB_WAIT_FOR_VBLANK(1 << 28)
+#define   DSB_WAIT_FOR_LINE_IN_RANGE(1 << 27)
+#define   DSB_HALT(1 << 16)
+#define   DSB_NON_POSTED_ENABLE(1 << 8)
+#define   DSB_STATUS(1 << 0)
+


Again, this patch is just adding the header definitions, please merge 
this patch in the patch where these definitions are being used.


Ok.

Regards,
Animesh


- Shashank


  #endif /* _I915_REG_H_ */


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Re: [Intel-gfx] [PATCH v3 05/11] drm/i915/dsb: Register definition of DSB registers.

2019-08-28 Thread Sharma, Shashank 


On 8/28/2019 12:40 AM, Animesh Manna wrote:

Added key register definitions of DSB.

dsb-ctrl register is required to enable dsb-engine.

head-ptr register hold the head of buffer address from where the
execution will start.

Programming tail-ptr register is a trigger point to start execution.

Cc: Uma Shankar 
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
---
  drivers/gpu/drm/i915/i915_reg.h | 15 +++
  1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..71c6c2380443 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11564,4 +11564,19 @@ enum skl_power_gate {
  #define PORT_TX_DFLEXDPCSSS(fia)  _MMIO_FIA((fia), 0x00894)
  #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)(1 << (tc_port))
  
+/* This register controls the Display State Buffer (DSB) engines. */

+#define _DSBSL_INSTANCE_BASE   0x70B00
+#define DSBSL_INSTANCE(pipe, id)   (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define   DSB_ENABLE   (1 << 31)
+#define   DSB_BUFFER_REITERATE (1 << 29)
+#define   DSB_WAIT_FOR_VBLANK  (1 << 28)
+#define   DSB_WAIT_FOR_LINE_IN_RANGE   (1 << 27)
+#define   DSB_HALT (1 << 16)
+#define   DSB_NON_POSTED_ENABLE(1 << 8)
+#define   DSB_STATUS   (1 << 0)
+


Again, this patch is just adding the header definitions, please merge 
this patch in the patch where these definitions are being used.


- Shashank


  #endif /* _I915_REG_H_ */

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[Intel-gfx] [PATCH v3 05/11] drm/i915/dsb: Register definition of DSB registers.

2019-08-27 Thread Animesh Manna 
Added key register definitions of DSB.

dsb-ctrl register is required to enable dsb-engine.

head-ptr register hold the head of buffer address from where the
execution will start.

Programming tail-ptr register is a trigger point to start execution.

Cc: Uma Shankar 
Cc: Jani Nikula 
Cc: Rodrigo Vivi 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/i915_reg.h | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02e1ef10c47e..71c6c2380443 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11564,4 +11564,19 @@ enum skl_power_gate {
 #define PORT_TX_DFLEXDPCSSS(fia)   _MMIO_FIA((fia), 0x00894)
 #define   DP_PHY_MODE_STATUS_NOT_SAFE(tc_port) (1 << (tc_port))
 
+/* This register controls the Display State Buffer (DSB) engines. */
+#define _DSBSL_INSTANCE_BASE   0x70B00
+#define DSBSL_INSTANCE(pipe, id)   (_DSBSL_INSTANCE_BASE + \
+(pipe) * 0x1000 + (id) * 100)
+#define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
+#define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
+#define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define   DSB_ENABLE   (1 << 31)
+#define   DSB_BUFFER_REITERATE (1 << 29)
+#define   DSB_WAIT_FOR_VBLANK  (1 << 28)
+#define   DSB_WAIT_FOR_LINE_IN_RANGE   (1 << 27)
+#define   DSB_HALT (1 << 16)
+#define   DSB_NON_POSTED_ENABLE(1 << 8)
+#define   DSB_STATUS   (1 << 0)
+
 #endif /* _I915_REG_H_ */
-- 
2.22.0

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