subject:"\[Intel\-gfx\] \[PATCH v4 07\/22\] drm\/i915\/mtl\: Add support for PM DEMAND"

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

2023-03-02 Thread Sripada, Radhakrishna



> -Original Message-
> From: Intel-gfx  On Behalf Of Kahola,
> Mika
> Sent: Thursday, March 2, 2023 1:40 AM
> To: Murthy, Arun R ; intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D ; De Marchi, Lucas
> 
> Subject: Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM
> DEMAND
> 
> > -Original Message-
> > From: Murthy, Arun R 
> > Sent: Thursday, March 2, 2023 10:50 AM
> > To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> > Cc: De Marchi, Lucas ; Roper, Matthew D
> > 
> > Subject: RE: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM
> > DEMAND
> >
> > > -Original Message-
> > > From: Intel-gfx  On Behalf Of
> > > Mika Kahola
> > > Sent: Friday, February 24, 2023 3:44 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: De Marchi, Lucas ; Roper, Matthew D
> > > 
> > > Subject: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM
> > > DEMAND
> > >
> > > Display14 introduces a new way to instruct the PUnit with power and
> > > bandwidth requirements of DE. Add the functionality to program the
> > > registers and handle waits using interrupts.
> > > The current wait time for timeouts is programmed for 10 msecs to
> > > factor in the worst case scenarios. Changes made to use REG_BIT for a
> > > register that we touched(GEN8_DE_MISC_IER _MMIO).
> > >
> > > v2:
> > >   - Removed repeated definition of dbuf, which has been moved to struct
> > > intel_display. (Gustavo)
> > >   - s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)
> > >
> > > Bspec: 66451, 64636, 64602, 64603
> > > Cc: Matt Atwood 
> > > Cc: Matt Roper 
> > > Cc: Lucas De Marchi 
> > > Cc: Gustavo Sousa 
> > > Signed-off-by: José Roberto de Souza 
> > > Signed-off-by: Radhakrishna Sripada 
> > > Link:
> > > https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-
> 8-
> > > mika.kah...@intel.com
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_bw.c   |   4 +-
> > >  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
> > >  drivers/gpu/drm/i915/display/intel_display.c  |  14 +
> > >  .../drm/i915/display/intel_display_power.c|   8 +
> > >  drivers/gpu/drm/i915/i915_drv.h   |   6 +
> > >  drivers/gpu/drm/i915/i915_irq.c   |  22 +-
> > >  drivers/gpu/drm/i915/i915_reg.h   |  33 +-
> > >  drivers/gpu/drm/i915/intel_pm.c   | 286 ++
> > >  drivers/gpu/drm/i915/intel_pm.h   |  35 +++
> > >  9 files changed, 405 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > > b/drivers/gpu/drm/i915/display/intel_bw.c
> > > index 202321ffbe2a..87c20bf52123 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > @@ -746,8 +746,8 @@ static unsigned int
> > > intel_bw_num_active_planes(struct drm_i915_private *dev_priv
> > >   return num_active_planes;
> > >  }
> > >
> > > -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > > -const struct intel_bw_state *bw_state)
> > > +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > > + const struct intel_bw_state *bw_state)
> > >  {
> > >   unsigned int data_rate = 0;
> > >   enum pipe pipe;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > > b/drivers/gpu/drm/i915/display/intel_bw.h
> > > index f20292143745..17fc0b61db04 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private
> > > *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state
> > > *state);  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > > const struct intel_crtc_state *crtc_state);
> > > +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > > + const struct intel_bw_state *bw_state);
> > >  int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> > > u32 points_mask);
> > >  int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, diff
> > > --git a/drive

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

2023-03-02 Thread Kahola, Mika

> -Original Message-
> From: Murthy, Arun R 
> Sent: Thursday, March 2, 2023 10:50 AM
> To: Kahola, Mika ; intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas ; Roper, Matthew D
> 
> Subject: RE: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM
> DEMAND
> 
> > -Original Message-
> > From: Intel-gfx  On Behalf Of
> > Mika Kahola
> > Sent: Friday, February 24, 2023 3:44 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: De Marchi, Lucas ; Roper, Matthew D
> > 
> > Subject: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM
> > DEMAND
> >
> > Display14 introduces a new way to instruct the PUnit with power and
> > bandwidth requirements of DE. Add the functionality to program the
> > registers and handle waits using interrupts.
> > The current wait time for timeouts is programmed for 10 msecs to
> > factor in the worst case scenarios. Changes made to use REG_BIT for a
> > register that we touched(GEN8_DE_MISC_IER _MMIO).
> >
> > v2:
> >   - Removed repeated definition of dbuf, which has been moved to struct
> > intel_display. (Gustavo)
> >   - s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)
> >
> > Bspec: 66451, 64636, 64602, 64603
> > Cc: Matt Atwood 
> > Cc: Matt Roper 
> > Cc: Lucas De Marchi 
> > Cc: Gustavo Sousa 
> > Signed-off-by: José Roberto de Souza 
> > Signed-off-by: Radhakrishna Sripada 
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-
> > mika.kah...@intel.com
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c   |   4 +-
> >  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
> >  drivers/gpu/drm/i915/display/intel_display.c  |  14 +
> >  .../drm/i915/display/intel_display_power.c|   8 +
> >  drivers/gpu/drm/i915/i915_drv.h   |   6 +
> >  drivers/gpu/drm/i915/i915_irq.c   |  22 +-
> >  drivers/gpu/drm/i915/i915_reg.h   |  33 +-
> >  drivers/gpu/drm/i915/intel_pm.c   | 286 ++
> >  drivers/gpu/drm/i915/intel_pm.h   |  35 +++
> >  9 files changed, 405 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 202321ffbe2a..87c20bf52123 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -746,8 +746,8 @@ static unsigned int
> > intel_bw_num_active_planes(struct drm_i915_private *dev_priv
> > return num_active_planes;
> >  }
> >
> > -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > -  const struct intel_bw_state *bw_state)
> > +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > +   const struct intel_bw_state *bw_state)
> >  {
> > unsigned int data_rate = 0;
> > enum pipe pipe;
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index f20292143745..17fc0b61db04 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state
> > *state);  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> >   const struct intel_crtc_state *crtc_state);
> > +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > +   const struct intel_bw_state *bw_state);
> >  int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> >   u32 points_mask);
> >  int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, diff
> > --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 8030968e7008..676bf512b9ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -959,6 +959,9 @@ intel_get_crtc_new_encoder(const struct
> > intel_atomic_state *state,
> > num_encoders++;
> > }
> >
> > +   if (!encoder)
> > +   return NULL;
> > +
> > drm_WARN(encoder->base.dev, num_encoders != 1,
> >  "%d encoders for pipe %c\n",
> >  num_encoders, pipe_name(master_crtc->pipe)); @@ -
> > 6823,6 +6826,10 @@ int intel_ato

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

2023-03-02 Thread Murthy, Arun R

> -Original Message-
> From: Intel-gfx  On Behalf Of Mika
> Kahola
> Sent: Friday, February 24, 2023 3:44 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas ; Roper, Matthew D
> 
> Subject: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM
> DEMAND
> 
> Display14 introduces a new way to instruct the PUnit with power and
> bandwidth requirements of DE. Add the functionality to program the
> registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to factor in
> the worst case scenarios. Changes made to use REG_BIT for a register that
> we touched(GEN8_DE_MISC_IER _MMIO).
> 
> v2:
>   - Removed repeated definition of dbuf, which has been moved to struct
> intel_display. (Gustavo)
>   - s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)
> 
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Cc: Gustavo Sousa 
> Signed-off-by: José Roberto de Souza 
> Signed-off-by: Radhakrishna Sripada 
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-
> mika.kah...@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c   |   4 +-
>  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  14 +
>  .../drm/i915/display/intel_display_power.c|   8 +
>  drivers/gpu/drm/i915/i915_drv.h   |   6 +
>  drivers/gpu/drm/i915/i915_irq.c   |  22 +-
>  drivers/gpu/drm/i915/i915_reg.h   |  33 +-
>  drivers/gpu/drm/i915/intel_pm.c   | 286 ++
>  drivers/gpu/drm/i915/intel_pm.h   |  35 +++
>  9 files changed, 405 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 202321ffbe2a..87c20bf52123 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -746,8 +746,8 @@ static unsigned int
> intel_bw_num_active_planes(struct drm_i915_private *dev_priv
>   return num_active_planes;
>  }
> 
> -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> -const struct intel_bw_state *bw_state)
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state)
>  {
>   unsigned int data_rate = 0;
>   enum pipe pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index f20292143745..17fc0b61db04 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);  void
> intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state);
>  int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
>  int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8030968e7008..676bf512b9ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -959,6 +959,9 @@ intel_get_crtc_new_encoder(const struct
> intel_atomic_state *state,
>   num_encoders++;
>   }
> 
> + if (!encoder)
> + return NULL;
> +
>   drm_WARN(encoder->base.dev, num_encoders != 1,
>"%d encoders for pipe %c\n",
>num_encoders, pipe_name(master_crtc->pipe)); @@ -
> 6823,6 +6826,10 @@ int intel_atomic_check(struct drm_device *dev,
>   ret = intel_modeset_calc_cdclk(state);
>   if (ret)
>   return ret;
> +
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
>   }
> 
>   ret = intel_atomic_check_crtcs(state); @@ -7439,6 +7446,7 @@ static
> void intel_atomic_commit_tail(struct intel_atomic_state *state)
>   }
> 
>   intel_sagv_pre_plane_update(state);
> + intel_pmdemand_pre_plane_update(state);
> 
>   /* Complete the events for pipes that have now been disabled */
>   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

2023-03-01 Thread Sripada, Radhakrishna

Hi Mika,

> -Original Message-
> From: Kahola, Mika 
> Sent: Friday, February 24, 2023 2:14 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika ; Atwood, Matthew S
> ; Roper, Matthew D
> ; De Marchi, Lucas ;
> Sousa, Gustavo ; Souza, Jose
> ; Sripada, Radhakrishna
> 
> Subject: [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND
> 
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
> 
> v2:
>   - Removed repeated definition of dbuf, which has been moved to struct
> intel_display. (Gustavo)
>   - s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)
> 
> Bspec: 66451, 64636, 64602, 64603
> Cc: Matt Atwood 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Cc: Gustavo Sousa 
> Signed-off-by: José Roberto de Souza 
> Signed-off-by: Radhakrishna Sripada 
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-
> mika.kah...@intel.com
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c   |   4 +-
>  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  14 +
>  .../drm/i915/display/intel_display_power.c|   8 +
>  drivers/gpu/drm/i915/i915_drv.h   |   6 +
>  drivers/gpu/drm/i915/i915_irq.c   |  22 +-
>  drivers/gpu/drm/i915/i915_reg.h   |  33 +-
>  drivers/gpu/drm/i915/intel_pm.c   | 286 ++
>  drivers/gpu/drm/i915/intel_pm.h   |  35 +++
>  9 files changed, 405 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 202321ffbe2a..87c20bf52123 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -746,8 +746,8 @@ static unsigned int intel_bw_num_active_planes(struct
> drm_i915_private *dev_priv
>   return num_active_planes;
>  }
> 
> -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> -const struct intel_bw_state *bw_state)
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state)
>  {
>   unsigned int data_rate = 0;
>   enum pipe pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index f20292143745..17fc0b61db04 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
>  int intel_bw_atomic_check(struct intel_atomic_state *state);
>  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state);
>  int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
>  int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8030968e7008..676bf512b9ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -959,6 +959,9 @@ intel_get_crtc_new_encoder(const struct
> intel_atomic_state *state,
>   num_encoders++;
>   }
> 
> + if (!encoder)
> + return NULL;
> +
>   drm_WARN(encoder->base.dev, num_encoders != 1,
>"%d encoders for pipe %c\n",
>num_encoders, pipe_name(master_crtc->pipe));
> @@ -6823,6 +6826,10 @@ int intel_atomic_check(struct drm_device *dev,
>   ret = intel_modeset_calc_cdclk(state);
>   if (ret)
>   return ret;
> +
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
>   }
> 
>   ret = intel_atomic_check_crtcs(state);
> @@ -7439,6 +7446,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>   }
> 
>   intel_sagv_pre_plane_update(state);
> + intel_pmdemand_pre_plane_update(state);
> 
>   /* Complete the events for pipes that have now been disabled */
>   for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -7551,6 +7559,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>   intel_verify_planes(state);
> 
>   intel_sagv_post_plane_update(state);
> + intel_pmdemand_post_plane_update(state);
> 
>

[Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

2023-02-24 Thread Mika Kahola

Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).

v2:
  - Removed repeated definition of dbuf, which has been moved to struct
intel_display. (Gustavo)
  - s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)

Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Gustavo Sousa 
Signed-off-by: José Roberto de Souza 
Signed-off-by: Radhakrishna Sripada 
Link: 
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-mika.kah...@intel.com
---
 drivers/gpu/drm/i915/display/intel_bw.c   |   4 +-
 drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  14 +
 .../drm/i915/display/intel_display_power.c|   8 +
 drivers/gpu/drm/i915/i915_drv.h   |   6 +
 drivers/gpu/drm/i915/i915_irq.c   |  22 +-
 drivers/gpu/drm/i915/i915_reg.h   |  33 +-
 drivers/gpu/drm/i915/intel_pm.c   | 286 ++
 drivers/gpu/drm/i915/intel_pm.h   |  35 +++
 9 files changed, 405 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 202321ffbe2a..87c20bf52123 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -746,8 +746,8 @@ static unsigned int intel_bw_num_active_planes(struct 
drm_i915_private *dev_priv
return num_active_planes;
 }
 
-static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
-  const struct intel_bw_state *bw_state)
+unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+   const struct intel_bw_state *bw_state)
 {
unsigned int data_rate = 0;
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h 
b/drivers/gpu/drm/i915/display/intel_bw.h
index f20292143745..17fc0b61db04 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
  const struct intel_crtc_state *crtc_state);
+unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+   const struct intel_bw_state *bw_state);
 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
  u32 points_mask);
 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 8030968e7008..676bf512b9ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -959,6 +959,9 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state 
*state,
num_encoders++;
}
 
+   if (!encoder)
+   return NULL;
+
drm_WARN(encoder->base.dev, num_encoders != 1,
 "%d encoders for pipe %c\n",
 num_encoders, pipe_name(master_crtc->pipe));
@@ -6823,6 +6826,10 @@ int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_calc_cdclk(state);
if (ret)
return ret;
+
+   ret = intel_pmdemand_atomic_check(state);
+   if (ret)
+   goto fail;
}
 
ret = intel_atomic_check_crtcs(state);
@@ -7439,6 +7446,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
}
 
intel_sagv_pre_plane_update(state);
+   intel_pmdemand_pre_plane_update(state);
 
/* Complete the events for pipes that have now been disabled */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -7551,6 +7559,7 @@ static void intel_atomic_commit_tail(struct 
intel_atomic_state *state)
intel_verify_planes(state);
 
intel_sagv_post_plane_update(state);
+   intel_pmdemand_post_plane_update(state);
 
drm_atomic_helper_commit_hw_done(>base);
 
@@ -8282,6 +8291,7 @@ void intel_init_display_hooks(struct drm_i915_private 
*dev_priv)
intel_color_init_hooks(dev_priv);
intel_init_cdclk_hooks(dev_priv);
intel_audio_hooks_init(dev_priv);
+   intel_init_pmdemand(dev_priv);
 
intel_dpll_init_clock_hook(dev_priv);
 
@@ -8508,6 +8518,10 @@ int intel_modeset_init_noirq(struct drm_i915_private 
*i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
 
+   ret =

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

Re: [Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

[Intel-gfx] [PATCH v4 07/22] drm/i915/mtl: Add support for PM DEMAND

5 matches

Site Navigation

Mail list logo

Footer information