Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-06-20 Thread C, Ramalingam 



Best Regards,
Ramalingam C

> -Original Message-
> From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
> Daniel Vetter
> Sent: Wednesday, June 20, 2018 5:14 PM
> To: C, Ramalingam 
> Cc: intel-gfx ; dri-devel  de...@lists.freedesktop.org>; Sean Paul ; Chris
> Wilson ; Nikula, Jani ;
> Winkler, Tomas ; Usyskin, Alexander
> ; Shankar, Uma ;
> Sharma, Shashank 
> Subject: Re: [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP
> 
> On Wed, Jun 20, 2018 at 12:19 PM, Ramalingam C 
> wrote:
> >
> >
> > On Thursday 31 May 2018 12:52 PM, Daniel Vetter wrote:
> >>
> >> On Mon, May 21, 2018 at 06:23:57PM +0530, Ramalingam C wrote:
> >>>
> >>> Implements the DP adaptation specific HDCP2.2 functions.
> >>>
> >>> These functions perform the DPCD read and write for communicating
> >>> the
> >>> HDCP2.2 auth message back and forth.
> >>>
> >>> Note: Chris Wilson suggested alternate method for waiting for
> >>> CP_IRQ, than completions concept. WIP to understand and implement
> >>> that, if needed. Just to unblock the review of other changes, v2
> >>> still continues with completions.
> >>>
> >>> v2:
> >>>wait for cp_irq is merged with this patch. Rebased.
> >>> v3:
> >>>wait_queue is used for wait for cp_irq [Chris Wilson]
> >>> v4:
> >>>Style fixed.
> >>>%s/PARING/PAIRING
> >>>Few style fixes [Uma]
> >>>
> >>> Signed-off-by: Ramalingam C 
> >>> ---
> >>>   drivers/gpu/drm/i915/intel_dp.c   | 358
> >>> ++
> >>>   drivers/gpu/drm/i915/intel_drv.h  |   7 +
> >>>   drivers/gpu/drm/i915/intel_hdcp.c |   5 +
> >>>   3 files changed, 370 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> >>> b/drivers/gpu/drm/i915/intel_dp.c index 528407d608c8..ee71a26ec23f
> >>> 100644
> >>> --- a/drivers/gpu/drm/i915/intel_dp.c
> >>> +++ b/drivers/gpu/drm/i915/intel_dp.c
> >>> @@ -31,6 +31,7 @@
> >>>   #include 
> >>>   #include 
> >>>   #include 
> >>> +#include 
> >>>   #include 
> >>>   #include 
> >>>   #include  @@ -5057,6 +5058,28 @@ void
> >>> intel_dp_encoder_suspend(struct intel_encoder
> >>> *intel_encoder)
> >>> pps_unlock(intel_dp);
> >>>   }
> >>>   +static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
> >>> +int timeout) {
> >>> +   long ret;
> >>> +
> >>> +   /* Reinit */
> >>> +   atomic_set(>cp_irq_recved, 0);
> >>> +
> >>> +#define C (atomic_read(>cp_irq_recved) > 0)
> >>> +   ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue,
> >>> +C,
> >>> +
> >>> msecs_to_jiffies(timeout));
> >>> +
> >>> +   if (ret > 0) {
> >>> +   atomic_set(>cp_irq_recved, 0);
> >>> +   return 0;
> >>> +   } else if (!ret) {
> >>> +   return -ETIMEDOUT;
> >>> +   }
> >>> +   return (int)ret;
> >>> +}
> >>> +
> >>> +
> >>>   static
> >>>   int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
> >>> *intel_dig_port,
> >>> u8 *an) @@ -5275,6 +5298,335 @@ int
> >>> intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
> >>> return 0;
> >>>   }
> >>>   +static
> >>> +int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int
> >>> *offset)
> >>
> >> Ugh, this is annoying that we have to map things around like that.
> >> But looking at the numbers the standards really don't seem to match at all.
> >
> > Sorry i am not getting about not matching part.
> > You mean some offsets and timeouts are not matching with spec?
> 
> match as in you can't just compute them using a base_offset + hdcp_msgid 
> trick,
> you do have to use the lookup table. The numbers itself match the spec, it's 
> just
> that the specs are all inconsistent with each another for no real good reason.
> 
> >>
> >>
> >> Instead of open-coding this I suggested you use a table with a struct
> >> like:
> >>
> >> const static struct hdcp_dp {
> >> int hdcp_msg;
> >> int dpcd_offset;
> >> int timeout;
> >> /* whatever else you might need */ } hdcp_2_dp_table[] = {
> >> { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, ... },
> >> ...
> >> };
> >>
> >> Then just search that table in the code instead of the huge switch
> >> table below.
> >
> > Suggesting this for cpu optimization or for coding style?
> 
> Just coding style, having to check a table is easier than checking huge case
> statements. None of this code matters from a performance pov.

Sure Daniel. I will use array of struct here.

Thanks
-Ram
> 
> >
> >
> >>
> >>> +{
> >>> +   switch (byte) {
> >>> +   case HDCP_2_2_AKE_INIT:
> >>> +   *offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
> >>> +   break;
> >>> +   case HDCP_2_2_AKE_SEND_CERT:
> >>> +   *offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
> >>> +   break;
> >>> +   case HDCP_2_2_AKE_NO_STORED_KM:
> >>> +   *offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
>

Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-06-20 Thread Daniel Vetter 
On Wed, Jun 20, 2018 at 12:19 PM, Ramalingam C  wrote:
>
>
> On Thursday 31 May 2018 12:52 PM, Daniel Vetter wrote:
>>
>> On Mon, May 21, 2018 at 06:23:57PM +0530, Ramalingam C wrote:
>>>
>>> Implements the DP adaptation specific HDCP2.2 functions.
>>>
>>> These functions perform the DPCD read and write for communicating the
>>> HDCP2.2 auth message back and forth.
>>>
>>> Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
>>> than completions concept. WIP to understand and implement that,
>>> if needed. Just to unblock the review of other changes, v2 still
>>> continues with completions.
>>>
>>> v2:
>>>wait for cp_irq is merged with this patch. Rebased.
>>> v3:
>>>wait_queue is used for wait for cp_irq [Chris Wilson]
>>> v4:
>>>Style fixed.
>>>%s/PARING/PAIRING
>>>Few style fixes [Uma]
>>>
>>> Signed-off-by: Ramalingam C 
>>> ---
>>>   drivers/gpu/drm/i915/intel_dp.c   | 358
>>> ++
>>>   drivers/gpu/drm/i915/intel_drv.h  |   7 +
>>>   drivers/gpu/drm/i915/intel_hdcp.c |   5 +
>>>   3 files changed, 370 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>>> b/drivers/gpu/drm/i915/intel_dp.c
>>> index 528407d608c8..ee71a26ec23f 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -31,6 +31,7 @@
>>>   #include 
>>>   #include 
>>>   #include 
>>> +#include 
>>>   #include 
>>>   #include 
>>>   #include 
>>> @@ -5057,6 +5058,28 @@ void intel_dp_encoder_suspend(struct intel_encoder
>>> *intel_encoder)
>>> pps_unlock(intel_dp);
>>>   }
>>>   +static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
>>> +int timeout)
>>> +{
>>> +   long ret;
>>> +
>>> +   /* Reinit */
>>> +   atomic_set(>cp_irq_recved, 0);
>>> +
>>> +#define C (atomic_read(>cp_irq_recved) > 0)
>>> +   ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
>>> +
>>> msecs_to_jiffies(timeout));
>>> +
>>> +   if (ret > 0) {
>>> +   atomic_set(>cp_irq_recved, 0);
>>> +   return 0;
>>> +   } else if (!ret) {
>>> +   return -ETIMEDOUT;
>>> +   }
>>> +   return (int)ret;
>>> +}
>>> +
>>> +
>>>   static
>>>   int intel_dp_hdcp_write_an_aksv(struct intel_digital_port
>>> *intel_dig_port,
>>> u8 *an)
>>> @@ -5275,6 +5298,335 @@ int intel_dp_hdcp_capable(struct
>>> intel_digital_port *intel_dig_port,
>>> return 0;
>>>   }
>>>   +static
>>> +int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int
>>> *offset)
>>
>> Ugh, this is annoying that we have to map things around like that. But
>> looking at the numbers the standards really don't seem to match at all.
>
> Sorry i am not getting about not matching part.
> You mean some offsets and timeouts are not matching with spec?

match as in you can't just compute them using a base_offset +
hdcp_msgid trick, you do have to use the lookup table. The numbers
itself match the spec, it's just that the specs are all inconsistent
with each another for no real good reason.

>>
>>
>> Instead of open-coding this I suggested you use a table with a struct
>> like:
>>
>> const static struct hdcp_dp {
>> int hdcp_msg;
>> int dpcd_offset;
>> int timeout;
>> /* whatever else you might need */
>> } hdcp_2_dp_table[] = {
>> { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, ... },
>> ...
>> };
>>
>> Then just search that table in the code instead of the huge switch table
>> below.
>
> Suggesting this for cpu optimization or for coding style?

Just coding style, having to check a table is easier than checking
huge case statements. None of this code matters from a performance
pov.

>
>
>>
>>> +{
>>> +   switch (byte) {
>>> +   case HDCP_2_2_AKE_INIT:
>>> +   *offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_AKE_SEND_CERT:
>>> +   *offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_AKE_NO_STORED_KM:
>>> +   *offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_AKE_STORED_KM:
>>> +   *offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_AKE_SEND_HPRIME:
>>> +   *offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_AKE_SEND_PAIRING_INFO:
>>> +   *offset = DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_LC_INIT:
>>> +   *offset = DP_HDCP_2_2_LC_INIT_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_LC_SEND_LPRIME:
>>> +   *offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
>>> +   break;
>>> +   case HDCP_2_2_SKE_SEND_EKS:
>>> +   *offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
>>> +

Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-06-20 Thread Ramalingam C 



On Thursday 31 May 2018 12:52 PM, Daniel Vetter wrote:

On Mon, May 21, 2018 at 06:23:57PM +0530, Ramalingam C wrote:

Implements the DP adaptation specific HDCP2.2 functions.

These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.

Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
than completions concept. WIP to understand and implement that,
if needed. Just to unblock the review of other changes, v2 still
continues with completions.

v2:
   wait for cp_irq is merged with this patch. Rebased.
v3:
   wait_queue is used for wait for cp_irq [Chris Wilson]
v4:
   Style fixed.
   %s/PARING/PAIRING
   Few style fixes [Uma]

Signed-off-by: Ramalingam C 
---
  drivers/gpu/drm/i915/intel_dp.c   | 358 ++
  drivers/gpu/drm/i915/intel_drv.h  |   7 +
  drivers/gpu/drm/i915/intel_hdcp.c |   5 +
  3 files changed, 370 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 528407d608c8..ee71a26ec23f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -5057,6 +5058,28 @@ void intel_dp_encoder_suspend(struct intel_encoder 
*intel_encoder)
pps_unlock(intel_dp);
  }
  
+static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,

+int timeout)
+{
+   long ret;
+
+   /* Reinit */
+   atomic_set(>cp_irq_recved, 0);
+
+#define C (atomic_read(>cp_irq_recved) > 0)
+   ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
+  msecs_to_jiffies(timeout));
+
+   if (ret > 0) {
+   atomic_set(>cp_irq_recved, 0);
+   return 0;
+   } else if (!ret) {
+   return -ETIMEDOUT;
+   }
+   return (int)ret;
+}
+
+
  static
  int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
u8 *an)
@@ -5275,6 +5298,335 @@ int intel_dp_hdcp_capable(struct intel_digital_port 
*intel_dig_port,
return 0;
  }
  
+static

+int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int *offset)

Ugh, this is annoying that we have to map things around like that. But
looking at the numbers the standards really don't seem to match at all.

Sorry i am not getting about not matching part.
You mean some offsets and timeouts are not matching with spec?


Instead of open-coding this I suggested you use a table with a struct
like:

const static struct hdcp_dp {
int hdcp_msg;
int dpcd_offset;
int timeout;
/* whatever else you might need */
} hdcp_2_dp_table[] = {
{ HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, ... },
...
};

Then just search that table in the code instead of the huge switch table
below.

Suggesting this for cpu optimization or for coding style?




+{
+   switch (byte) {
+   case HDCP_2_2_AKE_INIT:
+   *offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_CERT:
+   *offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
+   break;
+   case HDCP_2_2_AKE_NO_STORED_KM:
+   *offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
+   break;
+   case HDCP_2_2_AKE_STORED_KM:
+   *offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_HPRIME:
+   *offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_PAIRING_INFO:
+   *offset = DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET;
+   break;
+   case HDCP_2_2_LC_INIT:
+   *offset = DP_HDCP_2_2_LC_INIT_OFFSET;
+   break;
+   case HDCP_2_2_LC_SEND_LPRIME:
+   *offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
+   break;
+   case HDCP_2_2_SKE_SEND_EKS:
+   *offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
+   break;
+   case HDCP_2_2_REP_SEND_RECVID_LIST:
+   *offset = DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET;
+   break;
+   case HDCP_2_2_REP_SEND_ACK:
+   *offset = DP_HDCP_2_2_REP_SEND_ACK_OFFSET;
+   break;
+   case HDCP_2_2_REP_STREAM_MANAGE:
+   *offset = DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET;
+   break;
+   case HDCP_2_2_REP_STREAM_READY:
+   *offset = DP_HDCP_2_2_REP_STREAM_READY_OFFSET;
+   break;
+   case HDCP_2_2_ERRATA_DP_STREAM_TYPE:
+   *offset = DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET;
+   break;
+   default:
+   DRM_ERROR("Unrecognized Msg ID\n");
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static inline
+int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+

Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-05-31 Thread Daniel Vetter 
On Mon, May 21, 2018 at 06:23:57PM +0530, Ramalingam C wrote:
> Implements the DP adaptation specific HDCP2.2 functions.
> 
> These functions perform the DPCD read and write for communicating the
> HDCP2.2 auth message back and forth.
> 
> Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
> than completions concept. WIP to understand and implement that,
> if needed. Just to unblock the review of other changes, v2 still
> continues with completions.
> 
> v2:
>   wait for cp_irq is merged with this patch. Rebased.
> v3:
>   wait_queue is used for wait for cp_irq [Chris Wilson]
> v4:
>   Style fixed.
>   %s/PARING/PAIRING
>   Few style fixes [Uma]
> 
> Signed-off-by: Ramalingam C 
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 358 
> ++
>  drivers/gpu/drm/i915/intel_drv.h  |   7 +
>  drivers/gpu/drm/i915/intel_hdcp.c |   5 +
>  3 files changed, 370 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 528407d608c8..ee71a26ec23f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -31,6 +31,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -5057,6 +5058,28 @@ void intel_dp_encoder_suspend(struct intel_encoder 
> *intel_encoder)
>   pps_unlock(intel_dp);
>  }
>  
> +static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
> +  int timeout)
> +{
> + long ret;
> +
> + /* Reinit */
> + atomic_set(>cp_irq_recved, 0);
> +
> +#define C (atomic_read(>cp_irq_recved) > 0)
> + ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
> +msecs_to_jiffies(timeout));
> +
> + if (ret > 0) {
> + atomic_set(>cp_irq_recved, 0);
> + return 0;
> + } else if (!ret) {
> + return -ETIMEDOUT;
> + }
> + return (int)ret;
> +}
> +
> +
>  static
>  int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
>   u8 *an)
> @@ -5275,6 +5298,335 @@ int intel_dp_hdcp_capable(struct intel_digital_port 
> *intel_dig_port,
>   return 0;
>  }
>  
> +static
> +int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int *offset)

Ugh, this is annoying that we have to map things around like that. But
looking at the numbers the standards really don't seem to match at all.

Instead of open-coding this I suggested you use a table with a struct
like:

const static struct hdcp_dp {
int hdcp_msg;
int dpcd_offset;
int timeout;
/* whatever else you might need */
} hdcp_2_dp_table[] = {
{ HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, ... },
...
};

Then just search that table in the code instead of the huge switch table
below.

> +{
> + switch (byte) {
> + case HDCP_2_2_AKE_INIT:
> + *offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
> + break;
> + case HDCP_2_2_AKE_SEND_CERT:
> + *offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
> + break;
> + case HDCP_2_2_AKE_NO_STORED_KM:
> + *offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
> + break;
> + case HDCP_2_2_AKE_STORED_KM:
> + *offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
> + break;
> + case HDCP_2_2_AKE_SEND_HPRIME:
> + *offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
> + break;
> + case HDCP_2_2_AKE_SEND_PAIRING_INFO:
> + *offset = DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET;
> + break;
> + case HDCP_2_2_LC_INIT:
> + *offset = DP_HDCP_2_2_LC_INIT_OFFSET;
> + break;
> + case HDCP_2_2_LC_SEND_LPRIME:
> + *offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
> + break;
> + case HDCP_2_2_SKE_SEND_EKS:
> + *offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
> + break;
> + case HDCP_2_2_REP_SEND_RECVID_LIST:
> + *offset = DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET;
> + break;
> + case HDCP_2_2_REP_SEND_ACK:
> + *offset = DP_HDCP_2_2_REP_SEND_ACK_OFFSET;
> + break;
> + case HDCP_2_2_REP_STREAM_MANAGE:
> + *offset = DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET;
> + break;
> + case HDCP_2_2_REP_STREAM_READY:
> + *offset = DP_HDCP_2_2_REP_STREAM_READY_OFFSET;
> + break;
> + case HDCP_2_2_ERRATA_DP_STREAM_TYPE:
> + *offset = DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET;
> + break;
> + default:
> + DRM_ERROR("Unrecognized Msg ID\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static inline
> +int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
> +   uint8_t *rx_status)
> +{
> + ssize_t ret;
> +
> + ret =

Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-05-22 Thread kbuild test robot 
Hi Ramalingam,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20180517]
[cannot apply to v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180523-031938
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x012-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All warnings (new ones prefixed by >>):

   In file included from include/drm/drm_mm.h:49:0,
from include/drm/drmP.h:73,
from drivers/gpu/drm/i915/intel_dp.c:36:
   drivers/gpu/drm/i915/intel_dp.c: In function 'intel_dp_hdcp2_read_rx_status':
>> drivers/gpu/drm/i915/intel_dp.c:5396:13: warning: format '%ld' expects 
>> argument of type 'long int', but argument 2 has type 'ssize_t {aka int}' 
>> [-Wformat=]
  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
^
   include/drm/drm_print.h:239:10: note: in definition of macro 'DRM_ERROR'
 drm_err(fmt, ##__VA_ARGS__)
 ^~~

vim +5396 drivers/gpu/drm/i915/intel_dp.c

  5385  
  5386  static inline
  5387  int intel_dp_hdcp2_read_rx_status(struct intel_digital_port 
*intel_dig_port,
  5388uint8_t *rx_status)
  5389  {
  5390  ssize_t ret;
  5391  
  5392  ret = drm_dp_dpcd_read(_dig_port->dp.aux,
  5393 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, 
rx_status,
  5394 HDCP_2_2_DP_RXSTATUS_LEN);
  5395  if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
> 5396  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", 
> ret);
  5397  return ret >= 0 ? -EIO : ret;
  5398  }
  5399  
  5400  return 0;
  5401  }
  5402  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


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Re: [Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-05-22 Thread kbuild test robot 
Hi Ramalingam,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180517]
[cannot apply to v4.17-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Ramalingam-C/drm-i915-Implement-HDCP2-2/20180523-031938
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x000-201820 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386 

All errors (new ones prefixed by >>):

   In file included from include/drm/drm_mm.h:49:0,
from include/drm/drmP.h:73,
from drivers/gpu//drm/i915/intel_dp.c:36:
   drivers/gpu//drm/i915/intel_dp.c: In function 
'intel_dp_hdcp2_read_rx_status':
>> drivers/gpu//drm/i915/intel_dp.c:5396:13: error: format '%ld' expects 
>> argument of type 'long int', but argument 2 has type 'ssize_t {aka int}' 
>> [-Werror=format=]
  DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
^
   include/drm/drm_print.h:239:10: note: in definition of macro 'DRM_ERROR'
 drm_err(fmt, ##__VA_ARGS__)
 ^~~
   Cyclomatic Complexity 5 include/linux/compiler.h:__read_once_size
   Cyclomatic Complexity 5 include/linux/compiler.h:__write_once_size
   Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_read
   Cyclomatic Complexity 1 include/linux/kasan-checks.h:kasan_check_write
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:ffs
   Cyclomatic Complexity 1 arch/x86/include/asm/bitops.h:fls
   Cyclomatic Complexity 1 include/linux/log2.h:__ilog2_u32
   Cyclomatic Complexity 3 include/linux/log2.h:is_power_of_2
   Cyclomatic Complexity 1 include/linux/list.h:INIT_LIST_HEAD
   Cyclomatic Complexity 1 include/linux/err.h:ERR_PTR
   Cyclomatic Complexity 1 include/linux/err.h:IS_ERR
   Cyclomatic Complexity 3 include/linux/err.h:IS_ERR_OR_NULL
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_read
   Cyclomatic Complexity 1 arch/x86/include/asm/atomic.h:arch_atomic_set
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_read
   Cyclomatic Complexity 1 include/asm-generic/atomic-instrumented.h:atomic_set
   Cyclomatic Complexity 1 include/asm-generic/atomic-long.h:atomic_long_read
   Cyclomatic Complexity 1 include/linux/lockdep.h:lock_is_held
   Cyclomatic Complexity 1 include/asm-generic/getorder.h:__get_order
   Cyclomatic Complexity 1 include/linux/mutex.h:__mutex_owner
   Cyclomatic Complexity 1 include/linux/mutex.h:mutex_is_locked
   Cyclomatic Complexity 1 include/linux/jiffies.h:_msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/jiffies.h:msecs_to_jiffies
   Cyclomatic Complexity 3 include/linux/ktime.h:ktime_compare
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_after
   Cyclomatic Complexity 70 include/linux/ktime.h:ktime_divns
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_to_ms
   Cyclomatic Complexity 1 include/linux/ktime.h:ktime_ms_delta
   Cyclomatic Complexity 1 include/linux/timekeeping.h:ktime_get_boottime
   Cyclomatic Complexity 2 include/linux/workqueue.h:to_delayed_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:queue_delayed_work
   Cyclomatic Complexity 1 include/linux/workqueue.h:schedule_delayed_work
   Cyclomatic Complexity 67 include/linux/slab.h:kmalloc_large
   Cyclomatic Complexity 3 include/linux/slab.h:kmalloc
   Cyclomatic Complexity 1 include/linux/slab.h:kzalloc
   Cyclomatic Complexity 1 include/linux/ww_mutex.h:ww_mutex_is_locked
   Cyclomatic Complexity 1 include/drm/drm_modeset_lock.h:drm_modeset_is_locked
   Cyclomatic Complexity 1 
include/drm/drm_modeset_helper_vtables.h:drm_connector_helper_add
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_max_lane_count
   Cyclomatic Complexity 3 include/drm/drm_dp_helper.h:drm_dp_enhanced_frame_cap
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_is_branch
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_dpcd_readb
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_dpcd_writeb
   Cyclomatic Complexity 1 include/drm/drm_dp_helper.h:drm_dp_has_quirk
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_offset
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_equal
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_reg.h:i915_mmio_reg_valid
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_utils.h:onoff
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/intel_uncore.h:intel_wait_for_register
   Cyclomatic Complexity 2 drivers/gpu//drm/i915/i915_drv.h:to_i915
   Cyclomatic Complexity 1 drivers/gpu//drm/i915/i915_drv.h:intel_info
   Cyclomatic Complexity 1 
drivers/gpu//drm/i915/i915_drv.h:msecs_to_jiffies_timeout
   Cyclomatic Complexity 5

[Intel-gfx] [PATCH v4 38/41] drm/i915: Implement the HDCP2.2 support for DP

2018-05-21 Thread Ramalingam C 
Implements the DP adaptation specific HDCP2.2 functions.

These functions perform the DPCD read and write for communicating the
HDCP2.2 auth message back and forth.

Note: Chris Wilson suggested alternate method for waiting for CP_IRQ,
than completions concept. WIP to understand and implement that,
if needed. Just to unblock the review of other changes, v2 still
continues with completions.

v2:
  wait for cp_irq is merged with this patch. Rebased.
v3:
  wait_queue is used for wait for cp_irq [Chris Wilson]
v4:
  Style fixed.
  %s/PARING/PAIRING
  Few style fixes [Uma]

Signed-off-by: Ramalingam C 
---
 drivers/gpu/drm/i915/intel_dp.c   | 358 ++
 drivers/gpu/drm/i915/intel_drv.h  |   7 +
 drivers/gpu/drm/i915/intel_hdcp.c |   5 +
 3 files changed, 370 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 528407d608c8..ee71a26ec23f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -5057,6 +5058,28 @@ void intel_dp_encoder_suspend(struct intel_encoder 
*intel_encoder)
pps_unlock(intel_dp);
 }
 
+static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
+int timeout)
+{
+   long ret;
+
+   /* Reinit */
+   atomic_set(>cp_irq_recved, 0);
+
+#define C (atomic_read(>cp_irq_recved) > 0)
+   ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
+  msecs_to_jiffies(timeout));
+
+   if (ret > 0) {
+   atomic_set(>cp_irq_recved, 0);
+   return 0;
+   } else if (!ret) {
+   return -ETIMEDOUT;
+   }
+   return (int)ret;
+}
+
+
 static
 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
u8 *an)
@@ -5275,6 +5298,335 @@ int intel_dp_hdcp_capable(struct intel_digital_port 
*intel_dig_port,
return 0;
 }
 
+static
+int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int *offset)
+{
+   switch (byte) {
+   case HDCP_2_2_AKE_INIT:
+   *offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_CERT:
+   *offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
+   break;
+   case HDCP_2_2_AKE_NO_STORED_KM:
+   *offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
+   break;
+   case HDCP_2_2_AKE_STORED_KM:
+   *offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_HPRIME:
+   *offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
+   break;
+   case HDCP_2_2_AKE_SEND_PAIRING_INFO:
+   *offset = DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET;
+   break;
+   case HDCP_2_2_LC_INIT:
+   *offset = DP_HDCP_2_2_LC_INIT_OFFSET;
+   break;
+   case HDCP_2_2_LC_SEND_LPRIME:
+   *offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
+   break;
+   case HDCP_2_2_SKE_SEND_EKS:
+   *offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
+   break;
+   case HDCP_2_2_REP_SEND_RECVID_LIST:
+   *offset = DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET;
+   break;
+   case HDCP_2_2_REP_SEND_ACK:
+   *offset = DP_HDCP_2_2_REP_SEND_ACK_OFFSET;
+   break;
+   case HDCP_2_2_REP_STREAM_MANAGE:
+   *offset = DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET;
+   break;
+   case HDCP_2_2_REP_STREAM_READY:
+   *offset = DP_HDCP_2_2_REP_STREAM_READY_OFFSET;
+   break;
+   case HDCP_2_2_ERRATA_DP_STREAM_TYPE:
+   *offset = DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET;
+   break;
+   default:
+   DRM_ERROR("Unrecognized Msg ID\n");
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static inline
+int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
+ uint8_t *rx_status)
+{
+   ssize_t ret;
+
+   ret = drm_dp_dpcd_read(_dig_port->dp.aux,
+  DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
+  HDCP_2_2_DP_RXSTATUS_LEN);
+   if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
+   DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
+   return ret >= 0 ? -EIO : ret;
+   }
+
+   return 0;
+}
+
+static
+int intel_dp_hdcp2_timeout_for_msg(uint8_t msg_id, bool paired)
+{
+   int timeout;
+
+   switch (msg_id) {
+   case HDCP_2_2_AKE_SEND_CERT:
+   timeout = HDCP_2_2_CERT_TIMEOUT;
+   break;
+   case HDCP_2_2_AKE_SEND_HPRIME:
+   if (paired)
+   timeout = HDCP_2_2_HPRIME_PAIRED_TIMEOUT;
+