Re: [Intel-gfx] [PATCH v4 5/5] drm/i915/dmc: mass rename dev_priv to i915
On Thu, 02 Mar 2023, Imre Deak wrote:
> On Wed, Mar 01, 2023 at 02:29:44PM +0200, Jani Nikula wrote:
>> Follow the contemporary convention for struct drm_i915_private * naming.
>>
>> Cc: Imre Deak
>> Signed-off-by: Jani Nikula
>
> Looks ok to me, on the patchset:
> Reviewed-by: Imre Deak
Thanks, pushed to din.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_dmc.c | 166 +++
>> 1 file changed, 81 insertions(+), 85 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
>> b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index 302a465ceb1f..6b162f77340e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -313,12 +313,12 @@ intel_get_stepping_info(struct drm_i915_private *i915,
>> return si;
>> }
>>
>> -static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
>> +static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)
>> {
>> /* The below bit doesn't need to be cleared ever afterwards */
>> -intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
>> +intel_de_rmw(i915, DC_STATE_DEBUG, 0,
>> DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
>> -intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
>> +intel_de_posting_read(i915, DC_STATE_DEBUG);
>> }
>>
>> static void disable_event_handler(struct drm_i915_private *i915,
>> @@ -476,33 +476,33 @@ void intel_dmc_disable_pipe(struct drm_i915_private
>> *i915, enum pipe pipe)
>>
>> /**
>> * intel_dmc_load_program() - write the firmware from memory to register.
>> - * @dev_priv: i915 drm device.
>> + * @i915: i915 drm device.
>> *
>> * DMC firmware is read from a .bin file and kept in internal memory one
>> time.
>> * Everytime display comes back from low power state this function is
>> called to
>> * copy the firmware from internal memory to registers.
>> */
>> -void intel_dmc_load_program(struct drm_i915_private *dev_priv)
>> +void intel_dmc_load_program(struct drm_i915_private *i915)
>> {
>> -struct i915_power_domains *power_domains =
>> _priv->display.power.domains;
>> -struct intel_dmc *dmc = i915_to_dmc(dev_priv);
>> +struct i915_power_domains *power_domains = >display.power.domains;
>> +struct intel_dmc *dmc = i915_to_dmc(i915);
>> enum intel_dmc_id dmc_id;
>> u32 i;
>>
>> -if (!intel_dmc_has_payload(dev_priv))
>> +if (!intel_dmc_has_payload(i915))
>> return;
>>
>> -pipedmc_clock_gating_wa(dev_priv, true);
>> +pipedmc_clock_gating_wa(i915, true);
>>
>> -disable_all_event_handlers(dev_priv);
>> +disable_all_event_handlers(i915);
>>
>> -assert_rpm_wakelock_held(_priv->runtime_pm);
>> +assert_rpm_wakelock_held(>runtime_pm);
>>
>> preempt_disable();
>>
>> for_each_dmc_id(dmc_id) {
>> for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
>> -intel_de_write_fw(dev_priv,
>> +intel_de_write_fw(i915,
>>
>> DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
>>dmc->dmc_info[dmc_id].payload[i]);
>> }
>> @@ -512,23 +512,23 @@ void intel_dmc_load_program(struct drm_i915_private
>> *dev_priv)
>>
>> for_each_dmc_id(dmc_id) {
>> for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
>> -intel_de_write(dev_priv,
>> dmc->dmc_info[dmc_id].mmioaddr[i],
>> +intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
>> dmc->dmc_info[dmc_id].mmiodata[i]);
>> }
>> }
>>
>> power_domains->dc_state = 0;
>>
>> -gen9_set_dc_state_debugmask(dev_priv);
>> +gen9_set_dc_state_debugmask(i915);
>>
>> /*
>> * Flip queue events need to be disabled before enabling DC5/6.
>> * i915 doesn't use the flip queue feature, so disable it already
>> * here.
>> */
>> -disable_all_flip_queue_events(dev_priv);
>> +disable_all_flip_queue_events(i915);
>>
>> -pipedmc_clock_gating_wa(dev_priv, false);
>> +pipedmc_clock_gating_wa(i915, false);
>> }
>>
>> /**
>> @@ -839,12 +839,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
>>
>> static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
>> {
>> -struct drm_i915_private *dev_priv = dmc->i915;
>> +struct drm_i915_private *i915 = dmc->i915;
>> struct intel_css_header *css_header;
>> struct intel_package_header *package_header;
>> struct intel_dmc_header_base *dmc_header;
>> struct stepping_info display_info = { '*', '*'};
>> -const struct stepping_info *si = intel_get_stepping_info(dev_priv,
>> _info);
>> +const struct stepping_info *si = intel_get_stepping_info(i915,
>> _info);
>> enum intel_dmc_id dmc_id;
>> u32 readcount = 0;
>> u32 r, offset;
>> @@
Re: [Intel-gfx] [PATCH v4 5/5] drm/i915/dmc: mass rename dev_priv to i915
On Wed, Mar 01, 2023 at 02:29:44PM +0200, Jani Nikula wrote:
> Follow the contemporary convention for struct drm_i915_private * naming.
>
> Cc: Imre Deak
> Signed-off-by: Jani Nikula
Looks ok to me, on the patchset:
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 166 +++
> 1 file changed, 81 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 302a465ceb1f..6b162f77340e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -313,12 +313,12 @@ intel_get_stepping_info(struct drm_i915_private *i915,
> return si;
> }
>
> -static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> +static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)
> {
> /* The below bit doesn't need to be cleared ever afterwards */
> - intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
> + intel_de_rmw(i915, DC_STATE_DEBUG, 0,
>DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> - intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> + intel_de_posting_read(i915, DC_STATE_DEBUG);
> }
>
> static void disable_event_handler(struct drm_i915_private *i915,
> @@ -476,33 +476,33 @@ void intel_dmc_disable_pipe(struct drm_i915_private
> *i915, enum pipe pipe)
>
> /**
> * intel_dmc_load_program() - write the firmware from memory to register.
> - * @dev_priv: i915 drm device.
> + * @i915: i915 drm device.
> *
> * DMC firmware is read from a .bin file and kept in internal memory one
> time.
> * Everytime display comes back from low power state this function is called
> to
> * copy the firmware from internal memory to registers.
> */
> -void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> +void intel_dmc_load_program(struct drm_i915_private *i915)
> {
> - struct i915_power_domains *power_domains =
> _priv->display.power.domains;
> - struct intel_dmc *dmc = i915_to_dmc(dev_priv);
> + struct i915_power_domains *power_domains = >display.power.domains;
> + struct intel_dmc *dmc = i915_to_dmc(i915);
> enum intel_dmc_id dmc_id;
> u32 i;
>
> - if (!intel_dmc_has_payload(dev_priv))
> + if (!intel_dmc_has_payload(i915))
> return;
>
> - pipedmc_clock_gating_wa(dev_priv, true);
> + pipedmc_clock_gating_wa(i915, true);
>
> - disable_all_event_handlers(dev_priv);
> + disable_all_event_handlers(i915);
>
> - assert_rpm_wakelock_held(_priv->runtime_pm);
> + assert_rpm_wakelock_held(>runtime_pm);
>
> preempt_disable();
>
> for_each_dmc_id(dmc_id) {
> for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
> - intel_de_write_fw(dev_priv,
> + intel_de_write_fw(i915,
>
> DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
> dmc->dmc_info[dmc_id].payload[i]);
> }
> @@ -512,23 +512,23 @@ void intel_dmc_load_program(struct drm_i915_private
> *dev_priv)
>
> for_each_dmc_id(dmc_id) {
> for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
> - intel_de_write(dev_priv,
> dmc->dmc_info[dmc_id].mmioaddr[i],
> + intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
> dmc->dmc_info[dmc_id].mmiodata[i]);
> }
> }
>
> power_domains->dc_state = 0;
>
> - gen9_set_dc_state_debugmask(dev_priv);
> + gen9_set_dc_state_debugmask(i915);
>
> /*
>* Flip queue events need to be disabled before enabling DC5/6.
>* i915 doesn't use the flip queue feature, so disable it already
>* here.
>*/
> - disable_all_flip_queue_events(dev_priv);
> + disable_all_flip_queue_events(i915);
>
> - pipedmc_clock_gating_wa(dev_priv, false);
> + pipedmc_clock_gating_wa(i915, false);
> }
>
> /**
> @@ -839,12 +839,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
>
> static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
> {
> - struct drm_i915_private *dev_priv = dmc->i915;
> + struct drm_i915_private *i915 = dmc->i915;
> struct intel_css_header *css_header;
> struct intel_package_header *package_header;
> struct intel_dmc_header_base *dmc_header;
> struct stepping_info display_info = { '*', '*'};
> - const struct stepping_info *si = intel_get_stepping_info(dev_priv,
> _info);
> + const struct stepping_info *si = intel_get_stepping_info(i915,
> _info);
> enum intel_dmc_id dmc_id;
> u32 readcount = 0;
> u32 r, offset;
> @@ -874,7 +874,7 @@ static void parse_dmc_fw(struct intel_dmc *dmc, const
> struct firmware *fw)
>
> offset = readcount +
[Intel-gfx] [PATCH v4 5/5] drm/i915/dmc: mass rename dev_priv to i915
Follow the contemporary convention for struct drm_i915_private * naming.
Cc: Imre Deak
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dmc.c | 166 +++
1 file changed, 81 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 302a465ceb1f..6b162f77340e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -313,12 +313,12 @@ intel_get_stepping_info(struct drm_i915_private *i915,
return si;
}
-static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
+static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915)
{
/* The below bit doesn't need to be cleared ever afterwards */
- intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
+ intel_de_rmw(i915, DC_STATE_DEBUG, 0,
DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
- intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
+ intel_de_posting_read(i915, DC_STATE_DEBUG);
}
static void disable_event_handler(struct drm_i915_private *i915,
@@ -476,33 +476,33 @@ void intel_dmc_disable_pipe(struct drm_i915_private
*i915, enum pipe pipe)
/**
* intel_dmc_load_program() - write the firmware from memory to register.
- * @dev_priv: i915 drm device.
+ * @i915: i915 drm device.
*
* DMC firmware is read from a .bin file and kept in internal memory one time.
* Everytime display comes back from low power state this function is called to
* copy the firmware from internal memory to registers.
*/
-void intel_dmc_load_program(struct drm_i915_private *dev_priv)
+void intel_dmc_load_program(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains =
_priv->display.power.domains;
- struct intel_dmc *dmc = i915_to_dmc(dev_priv);
+ struct i915_power_domains *power_domains = >display.power.domains;
+ struct intel_dmc *dmc = i915_to_dmc(i915);
enum intel_dmc_id dmc_id;
u32 i;
- if (!intel_dmc_has_payload(dev_priv))
+ if (!intel_dmc_has_payload(i915))
return;
- pipedmc_clock_gating_wa(dev_priv, true);
+ pipedmc_clock_gating_wa(i915, true);
- disable_all_event_handlers(dev_priv);
+ disable_all_event_handlers(i915);
- assert_rpm_wakelock_held(_priv->runtime_pm);
+ assert_rpm_wakelock_held(>runtime_pm);
preempt_disable();
for_each_dmc_id(dmc_id) {
for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) {
- intel_de_write_fw(dev_priv,
+ intel_de_write_fw(i915,
DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i),
dmc->dmc_info[dmc_id].payload[i]);
}
@@ -512,23 +512,23 @@ void intel_dmc_load_program(struct drm_i915_private
*dev_priv)
for_each_dmc_id(dmc_id) {
for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
- intel_de_write(dev_priv,
dmc->dmc_info[dmc_id].mmioaddr[i],
+ intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
dmc->dmc_info[dmc_id].mmiodata[i]);
}
}
power_domains->dc_state = 0;
- gen9_set_dc_state_debugmask(dev_priv);
+ gen9_set_dc_state_debugmask(i915);
/*
* Flip queue events need to be disabled before enabling DC5/6.
* i915 doesn't use the flip queue feature, so disable it already
* here.
*/
- disable_all_flip_queue_events(dev_priv);
+ disable_all_flip_queue_events(i915);
- pipedmc_clock_gating_wa(dev_priv, false);
+ pipedmc_clock_gating_wa(i915, false);
}
/**
@@ -839,12 +839,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
static void parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw)
{
- struct drm_i915_private *dev_priv = dmc->i915;
+ struct drm_i915_private *i915 = dmc->i915;
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
struct stepping_info display_info = { '*', '*'};
- const struct stepping_info *si = intel_get_stepping_info(dev_priv,
_info);
+ const struct stepping_info *si = intel_get_stepping_info(i915,
_info);
enum intel_dmc_id dmc_id;
u32 readcount = 0;
u32 r, offset;
@@ -874,7 +874,7 @@ static void parse_dmc_fw(struct intel_dmc *dmc, const
struct firmware *fw)
offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4;
if (offset > fw->size) {
- drm_err(_priv->drm, "Reading beyond the fw_size\n");
+ drm_err(>drm, "Reading beyond the fw_size\n");
continue;
