Re: [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells
On Tue, Jul 28, 2020 at 01:51:53PM -0700, Matt Roper wrote: On Fri, Jul 24, 2020 at 02:38:59PM -0700, Lucas De Marchi wrote: From: Uma Shankar Most of TGL power wells are re-used for DG1. However, AUDIO Power Domain is moved from PG3 to PG0. Handle the change and initialize power wells with the new power well structure. Some of the Audio Streaming logic still remains in PW3 so still it needs to be enabled. DDIA, DDIB, TC1 and TC2 are the active ports on DG1. Need to keep Transcoder C and D to Pipe Power wells, this is against the spec but else hitting unclaimed register warnings (kept the logic same as TGL) I think this paragraph is old; the bspec shows transcoders C and D in the same power wells as pipes C and D now so this is no longer a spec violation. Although the bspec went through a few revisions early on, it looks like DG1 is just a strict subset of the TGL power wells now, so there probably isn't a need to duplicate it as a whole new table here; I think the only thing keeping us from re-using TGL's table as-is for DG1 is the fake "TC COLD" well that blindly makes assumptions about which outputs are TC rather than paying attention to the real output type. I think Aditya has some code that would fix the TCCOLD's assumptions and then we can just point DG1 to the TGL table. Aditya, are you going to submit this soon? Matt Bspec: 49182 Cc: Matt Roper Cc: Anshuman Gupta Signed-off-by: Uma Shankar Signed-off-by: Lucas De Marchi --- .../drm/i915/display/intel_display_power.c| 201 +- 1 file changed, 200 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0c713e83274d..b51b82cb2398 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_INIT)) +#define DG1_PW_5_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_D) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\ + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_4_POWER_DOMAINS ( \ + DG1_PW_5_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_3_POWER_DOMAINS ( \ + DG1_PW_4_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUX_E) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_2_POWER_DOMAINS ( \ + DG1_PW_3_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + DG1_PW_3_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = i9xx_always_on_power_well_noop, @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = { }, }; +static const struct i915_power_well_desc dg1_power_wells[] = { + { + .name = "always-on", + .always_on = true, + .domains = POWER_DOMAIN_MASK, + .ops = &i9xx_always_on_power_well_ops, + .id = DISP_PW_ID_NONE, + }, + { + .name = "power well 1", + /* Handled by the DMC firmware */ + .always_on = true, + .domains = 0, + .ops = &hsw_power_well_ops, + .id = SKL_DISP_PW_1, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_1, + .hsw.has_fuses = true, + }, + }, + { + .name = "DC off", + .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS, +
Re: [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells
On Fri, Jul 24, 2020 at 02:38:59PM -0700, Lucas De Marchi wrote: > From: Uma Shankar > > Most of TGL power wells are re-used for DG1. However, AUDIO Power > Domain is moved from PG3 to PG0. Handle the change and initialize > power wells with the new power well structure. > > Some of the Audio Streaming logic still remains in PW3 so still > it needs to be enabled. > > DDIA, DDIB, TC1 and TC2 are the active ports on DG1. > > Need to keep Transcoder C and D to Pipe Power wells, this is against > the spec but else hitting unclaimed register warnings (kept the logic > same as TGL) I think this paragraph is old; the bspec shows transcoders C and D in the same power wells as pipes C and D now so this is no longer a spec violation. Although the bspec went through a few revisions early on, it looks like DG1 is just a strict subset of the TGL power wells now, so there probably isn't a need to duplicate it as a whole new table here; I think the only thing keeping us from re-using TGL's table as-is for DG1 is the fake "TC COLD" well that blindly makes assumptions about which outputs are TC rather than paying attention to the real output type. I think Aditya has some code that would fix the TCCOLD's assumptions and then we can just point DG1 to the TGL table. Matt > > Bspec: 49182 > > Cc: Matt Roper > Cc: Anshuman Gupta > Signed-off-by: Uma Shankar > Signed-off-by: Lucas De Marchi > --- > .../drm/i915/display/intel_display_power.c| 201 +- > 1 file changed, 200 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > b/drivers/gpu/drm/i915/display/intel_display_power.c > index 0c713e83274d..b51b82cb2398 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private > *dev_priv, > BIT_ULL(POWER_DOMAIN_AUX_B) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > > +#define DG1_PW_5_POWER_DOMAINS ( \ > + BIT_ULL(POWER_DOMAIN_PIPE_D) | \ > + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\ > + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) > + > +#define DG1_PW_4_POWER_DOMAINS ( \ > + DG1_PW_5_POWER_DOMAINS |\ > + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ > + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\ > + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) > + > +#define DG1_PW_3_POWER_DOMAINS ( \ > + DG1_PW_4_POWER_DOMAINS |\ > + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\ > + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ > + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\ > + BIT_ULL(POWER_DOMAIN_AUX_D) | \ > + BIT_ULL(POWER_DOMAIN_AUX_E) | \ > + BIT_ULL(POWER_DOMAIN_VGA) | \ > + BIT_ULL(POWER_DOMAIN_AUDIO) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) > + > +#define DG1_PW_2_POWER_DOMAINS ( \ > + DG1_PW_3_POWER_DOMAINS |\ > + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) > + > +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \ > + DG1_PW_3_POWER_DOMAINS |\ > + BIT_ULL(POWER_DOMAIN_MODESET) | \ > + BIT_ULL(POWER_DOMAIN_AUX_A) | \ > + BIT_ULL(POWER_DOMAIN_AUX_B) | \ > + BIT_ULL(POWER_DOMAIN_INIT)) > + > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { > .sync_hw = i9xx_power_well_sync_hw_noop, > .enable = i9xx_always_on_power_well_noop, > @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc > rkl_power_wells[] = { > }, > }; > > +static const struct i915_power_well_desc dg1_power_wells[] = { > + { > + .name = "always-on", > + .always_on = true, > + .domains = POWER_DOMAIN_MASK, > + .ops = &i9xx_always_on_power_well_ops, > + .id = DISP_PW_ID_NONE, > + }, > + { > + .name = "power well 1", > + /* Handled by the DMC firmware */ > + .always_on = true, > + .domains = 0, > + .ops = &hsw_power_well_ops, > + .id = SKL_DISP_PW_1, > + { > + .hsw.regs = &hsw_power_well_regs, > + .hsw.idx = ICL_PW_CTL_IDX_PW_1, > + .hsw.has_fuses = true, > + }, > + }, > + { > + .name = "DC off", > + .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS, > + .ops = &gen9
[Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells
From: Uma Shankar Most of TGL power wells are re-used for DG1. However, AUDIO Power Domain is moved from PG3 to PG0. Handle the change and initialize power wells with the new power well structure. Some of the Audio Streaming logic still remains in PW3 so still it needs to be enabled. DDIA, DDIB, TC1 and TC2 are the active ports on DG1. Need to keep Transcoder C and D to Pipe Power wells, this is against the spec but else hitting unclaimed register warnings (kept the logic same as TGL) Bspec: 49182 Cc: Matt Roper Cc: Anshuman Gupta Signed-off-by: Uma Shankar Signed-off-by: Lucas De Marchi --- .../drm/i915/display/intel_display_power.c| 201 +- 1 file changed, 200 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0c713e83274d..b51b82cb2398 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_AUX_B) | \ BIT_ULL(POWER_DOMAIN_INIT)) +#define DG1_PW_5_POWER_DOMAINS ( \ + BIT_ULL(POWER_DOMAIN_PIPE_D) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |\ + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_4_POWER_DOMAINS ( \ + DG1_PW_5_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\ + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_3_POWER_DOMAINS ( \ + DG1_PW_4_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\ + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\ + BIT_ULL(POWER_DOMAIN_AUX_D) | \ + BIT_ULL(POWER_DOMAIN_AUX_E) | \ + BIT_ULL(POWER_DOMAIN_VGA) | \ + BIT_ULL(POWER_DOMAIN_AUDIO) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_PW_2_POWER_DOMAINS ( \ + DG1_PW_3_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \ + DG1_PW_3_POWER_DOMAINS |\ + BIT_ULL(POWER_DOMAIN_MODESET) | \ + BIT_ULL(POWER_DOMAIN_AUX_A) | \ + BIT_ULL(POWER_DOMAIN_AUX_B) | \ + BIT_ULL(POWER_DOMAIN_INIT)) + static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_power_well_sync_hw_noop, .enable = i9xx_always_on_power_well_noop, @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = { }, }; +static const struct i915_power_well_desc dg1_power_wells[] = { + { + .name = "always-on", + .always_on = true, + .domains = POWER_DOMAIN_MASK, + .ops = &i9xx_always_on_power_well_ops, + .id = DISP_PW_ID_NONE, + }, + { + .name = "power well 1", + /* Handled by the DMC firmware */ + .always_on = true, + .domains = 0, + .ops = &hsw_power_well_ops, + .id = SKL_DISP_PW_1, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_1, + .hsw.has_fuses = true, + }, + }, + { + .name = "DC off", + .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS, + .ops = &gen9_dc_off_power_well_ops, + .id = SKL_DISP_DC_OFF, + }, + { + .name = "power well 2", + .domains = DG1_PW_2_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = SKL_DISP_PW_2, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_2, + .hsw.has_fuses = true, + }, + }, + { + .name = "power well 3", + .domains = DG1_PW_3_POWER_DOMAINS, + .ops = &hsw_power_well_ops, + .id = ICL_DISP_PW_3, + { + .hsw.regs = &hsw_power_well_regs, + .hsw.idx = ICL_PW_CTL_IDX_PW_3, + .hsw.irq_pipe_mask = BIT(PIPE_B), +