Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-08-13 Thread Lucas De Marchi 

On Mon, Aug 10, 2020 at 11:18:11AM +0530, Anshuman Gupta wrote:

On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:

On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > From: Anshuman Gupta <
> > > anshuman.gu...@intel.com
> > >
> > >
> > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > counter and handle i915_dmc_info accordingly.
> > >
> > > Cc: Uma Shankar <
> > > uma.shan...@intel.com
> > >
> > >
> > > Signed-off-by: Anshuman Gupta <
> > > anshuman.gu...@intel.com
> > >
> > >
> > > Signed-off-by: Lucas De Marchi <
> > > lucas.demar...@intel.com
> > >
> > >
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> > >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 3644752cc5ec..e3536edcb394 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void 
*unused)
> > > CSR_VERSION_MINOR(csr->version));
> > >
> > >  if (INTEL_GEN(dev_priv) >= 12) {
> > > -dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > -dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > +if (IS_DG1(dev_priv)) {
> > > +dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > +} else {
> > > +dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > +dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > +}
> > > +
> > >  /*
> > >   * NOTE: DMC_DEBUG3 is a general purpose reg.
> > >   * According to B.Specs:49196 DMC f/w reuses DC5/6 
counter
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4e95312eba24..78bdce67da08 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7549,6 +7549,8 @@ enum {
> > >  #define BXT_CSR_DC3_DC5_COUNT   _MMIO(0x80038)
> > >  #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
> > >  #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
> > > +#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
> > > +#define DG1_DMC_DEBUG_DC6_COUNT _MMIO(0x134158)
> >
> > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > Removing it:
>
> DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> igfx platforms, considering name consistency it has been kept with name DG1_*
> inline to B.Spec Index:49787.

A discrete graphics card will never be able to reach DC6 as it is a SOC power 
saving feature.

Is it documented some where, AFAIK DC6 is still diplay C state where it power 
off its innermost power well,
with involvment of some non display third party f/w.
IMHO if any discrete-gfx would support DC6, it would be useful in the use cases 
where driver is yet to request runtime suspend (DC9)
but display is already being powered off.


Correct, but I think the more relevant argument here is that it is _not
used_. If it was a bitfield, then ok. But it is a register. I don't think
we want to add all the unused registers. Chances are a new platform that
supports it will already have it in another address already.

I will remove it in the next version. And this is also 


Reviewed-by: Lucas De Marchi 


Lucas De Marchi

Thanks,
Anshuman Gupta.


>
> Thanks,
> Anshuman Gupta.
> > Reviewed-by: José Roberto de Souza <
> > jose.so...@intel.com
> > >
> >
> >
> > >
> > >  #define DMC_DEBUG3  _MMIO(0x101090)
> > >
> > >
> >
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> >
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >

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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-08-10 Thread Anshuman Gupta 
On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:
> On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> > On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > > From: Anshuman Gupta <
> > > > anshuman.gu...@intel.com
> > > > 
> > > > 
> > > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > > counter and handle i915_dmc_info accordingly.
> > > > 
> > > > Cc: Uma Shankar <
> > > > uma.shan...@intel.com
> > > > 
> > > > 
> > > > Signed-off-by: Anshuman Gupta <
> > > > anshuman.gu...@intel.com
> > > > 
> > > > 
> > > > Signed-off-by: Lucas De Marchi <
> > > > lucas.demar...@intel.com
> > > > 
> > > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> > > >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> > > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > index 3644752cc5ec..e3536edcb394 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void 
> > > > *unused)
> > > >CSR_VERSION_MINOR(csr->version));
> > > >  
> > > > if (INTEL_GEN(dev_priv) >= 12) {
> > > > -   dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > -   dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > +   if (IS_DG1(dev_priv)) {
> > > > +   dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > > +   } else {
> > > > +   dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > +   dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > +   }
> > > > +
> > > > /*
> > > >  * NOTE: DMC_DEBUG3 is a general purpose reg.
> > > >  * According to B.Specs:49196 DMC f/w reuses DC5/6 
> > > > counter
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 4e95312eba24..78bdce67da08 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7549,6 +7549,8 @@ enum {
> > > >  #define BXT_CSR_DC3_DC5_COUNT  _MMIO(0x80038)
> > > >  #define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
> > > >  #define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
> > > > +#define DG1_DMC_DEBUG_DC5_COUNT_MMIO(0x134154)
> > > > +#define DG1_DMC_DEBUG_DC6_COUNT_MMIO(0x134158)
> > > 
> > > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > > Removing it:
> > 
> > DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> > igfx platforms, considering name consistency it has been kept with name 
> > DG1_*
> > inline to B.Spec Index:49787.
> 
> A discrete graphics card will never be able to reach DC6 as it is a SOC power 
> saving feature.
Is it documented some where, AFAIK DC6 is still diplay C state where it power 
off its innermost power well,
with involvment of some non display third party f/w.
IMHO if any discrete-gfx would support DC6, it would be useful in the use cases 
where driver is yet to request runtime suspend (DC9)
but display is already being powered off.
Thanks,
Anshuman Gupta.
> 
> > 
> > Thanks,
> > Anshuman Gupta.
> > > Reviewed-by: José Roberto de Souza <
> > > jose.so...@intel.com
> > > >
> > > 
> > > 
> > > >  
> > > >  #define DMC_DEBUG3 _MMIO(0x101090)
> > > >  
> > > > 
> > > 
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > 
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-08-07 Thread Souza, Jose 
On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > From: Anshuman Gupta <
> > > anshuman.gu...@intel.com
> > > 
> > > 
> > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > counter and handle i915_dmc_info accordingly.
> > > 
> > > Cc: Uma Shankar <
> > > uma.shan...@intel.com
> > > 
> > > 
> > > Signed-off-by: Anshuman Gupta <
> > > anshuman.gu...@intel.com
> > > 
> > > 
> > > Signed-off-by: Lucas De Marchi <
> > > lucas.demar...@intel.com
> > > 
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> > >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 3644752cc5ec..e3536edcb394 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void 
> > > *unused)
> > >  CSR_VERSION_MINOR(csr->version));
> > >  
> > >   if (INTEL_GEN(dev_priv) >= 12) {
> > > - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > + if (IS_DG1(dev_priv)) {
> > > + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > + } else {
> > > + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > + }
> > > +
> > >   /*
> > >* NOTE: DMC_DEBUG3 is a general purpose reg.
> > >* According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4e95312eba24..78bdce67da08 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7549,6 +7549,8 @@ enum {
> > >  #define BXT_CSR_DC3_DC5_COUNT_MMIO(0x80038)
> > >  #define TGL_DMC_DEBUG_DC5_COUNT  _MMIO(0x101084)
> > >  #define TGL_DMC_DEBUG_DC6_COUNT  _MMIO(0x101088)
> > > +#define DG1_DMC_DEBUG_DC5_COUNT  _MMIO(0x134154)
> > > +#define DG1_DMC_DEBUG_DC6_COUNT  _MMIO(0x134158)
> > 
> > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > Removing it:
> 
> DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> igfx platforms, considering name consistency it has been kept with name DG1_*
> inline to B.Spec Index:49787.

A discrete graphics card will never be able to reach DC6 as it is a SOC power 
saving feature.

> 
> Thanks,
> Anshuman Gupta.
> > Reviewed-by: José Roberto de Souza <
> > jose.so...@intel.com
> > >
> > 
> > 
> > >  
> > >  #define DMC_DEBUG3   _MMIO(0x101090)
> > >  
> > > 
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > 
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-08-07 Thread Anshuman Gupta 
On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > From: Anshuman Gupta <
> > anshuman.gu...@intel.com
> > >
> > 
> > DGFX devices have different DMC_DEBUG* counter MMIO address
> > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > counter and handle i915_dmc_info accordingly.
> > 
> > Cc: Uma Shankar <
> > uma.shan...@intel.com
> > >
> > Signed-off-by: Anshuman Gupta <
> > anshuman.gu...@intel.com
> > >
> > Signed-off-by: Lucas De Marchi <
> > lucas.demar...@intel.com
> > >
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> >  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
> >  2 files changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 3644752cc5ec..e3536edcb394 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void 
> > *unused)
> >CSR_VERSION_MINOR(csr->version));
> >  
> > if (INTEL_GEN(dev_priv) >= 12) {
> > -   dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > -   dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > +   if (IS_DG1(dev_priv)) {
> > +   dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > +   } else {
> > +   dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > +   dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > +   }
> > +
> > /*
> >  * NOTE: DMC_DEBUG3 is a general purpose reg.
> >  * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4e95312eba24..78bdce67da08 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7549,6 +7549,8 @@ enum {
> >  #define BXT_CSR_DC3_DC5_COUNT  _MMIO(0x80038)
> >  #define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
> >  #define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
> > +#define DG1_DMC_DEBUG_DC5_COUNT_MMIO(0x134154)
> > +#define DG1_DMC_DEBUG_DC6_COUNT_MMIO(0x134158)
> 
> DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> Removing it:
DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
igfx platforms, considering name consistency it has been kept with name DG1_*
inline to B.Spec Index:49787.

Thanks,
Anshuman Gupta.
> 
> Reviewed-by: José Roberto de Souza 
> 
> 
> >  
> >  #define DMC_DEBUG3 _MMIO(0x101090)
> >  
> > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-08-03 Thread Souza, Jose 
On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gu...@intel.com
> >
> 
> DGFX devices have different DMC_DEBUG* counter MMIO address
> offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> counter and handle i915_dmc_info accordingly.
> 
> Cc: Uma Shankar <
> uma.shan...@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gu...@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demar...@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
>  drivers/gpu/drm/i915/i915_reg.h  | 2 ++
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3644752cc5ec..e3536edcb394 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void 
> *unused)
>  CSR_VERSION_MINOR(csr->version));
>  
>   if (INTEL_GEN(dev_priv) >= 12) {
> - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> + if (IS_DG1(dev_priv)) {
> + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> + } else {
> + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> + }
> +
>   /*
>* NOTE: DMC_DEBUG3 is a general purpose reg.
>* According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4e95312eba24..78bdce67da08 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7549,6 +7549,8 @@ enum {
>  #define BXT_CSR_DC3_DC5_COUNT_MMIO(0x80038)
>  #define TGL_DMC_DEBUG_DC5_COUNT  _MMIO(0x101084)
>  #define TGL_DMC_DEBUG_DC6_COUNT  _MMIO(0x101088)
> +#define DG1_DMC_DEBUG_DC5_COUNT  _MMIO(0x134154)
> +#define DG1_DMC_DEBUG_DC6_COUNT  _MMIO(0x134158)

DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
Removing it:

Reviewed-by: José Roberto de Souza 


>  
>  #define DMC_DEBUG3   _MMIO(0x101090)
>  
> 
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[Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

2020-07-24 Thread Lucas De Marchi 
From: Anshuman Gupta 

DGFX devices have different DMC_DEBUG* counter MMIO address
offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
counter and handle i915_dmc_info accordingly.

Cc: Uma Shankar 
Signed-off-by: Anshuman Gupta 
Signed-off-by: Lucas De Marchi 
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
 drivers/gpu/drm/i915/i915_reg.h  | 2 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3644752cc5ec..e3536edcb394 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
   CSR_VERSION_MINOR(csr->version));
 
if (INTEL_GEN(dev_priv) >= 12) {
-   dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
-   dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+   if (IS_DG1(dev_priv)) {
+   dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+   } else {
+   dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+   dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+   }
+
/*
 * NOTE: DMC_DEBUG3 is a general purpose reg.
 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e95312eba24..78bdce67da08 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7549,6 +7549,8 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT  _MMIO(0x80038)
 #define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT_MMIO(0x134154)
+#define DG1_DMC_DEBUG_DC6_COUNT_MMIO(0x134158)
 
 #define DMC_DEBUG3 _MMIO(0x101090)
 
-- 
2.26.2

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