Re: [Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets

2021-08-24 Thread Yokoyama, Caz 
Reviewed-by: Caz Yokoyama 
-caz

On Thu, 2021-08-05 at 09:36 -0700, Matt Roper wrote:
> From: Akeem G Abodunrin 
> 
> New LRI register offsets were introduced for DG2, this patch adds
> those extra registers, and create new register table for setting
> offsets
> to compare with HW generated context image - especially for gt_lrc
> test.
> Also updates general purpose register with scratch offset for DG2, in
> order to use it for live_lrc_fixed selftest.
> 
> Cc: Chris P Wilson 
> Cc: Prathap Kumar Valsan 
> Signed-off-by: Akeem G Abodunrin 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c | 85
> -
>  1 file changed, 83 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index bb4af4977920..6ba8daea2f56 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -226,6 +226,40 @@ static const u8 gen12_xcs_offsets[] = {
>   END
>  };
>  
> +static const u8 dg2_xcs_offsets[] = {
> + NOP(1),
> + LRI(15, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> + REG(0x120),
> + REG(0x124),
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + END
> +};
> +
>  static const u8 gen8_rcs_offsets[] = {
>   NOP(1),
>   LRI(14, POSTED),
> @@ -525,6 +559,49 @@ static const u8 xehp_rcs_offsets[] = {
>   END
>  };
>  
> +static const u8 dg2_rcs_offsets[] = {
> + NOP(1),
> + LRI(15, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> + REG(0x120),
> + REG(0x124),
> +
> + NOP(1),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + LRI(3, POSTED),
> + REG(0x1b0),
> + REG16(0x5a8),
> + REG16(0x5ac),
> +
> + NOP(6),
> + LRI(1, 0),
> + REG(0x0c8),
> +
> + END
> +};
> +
>  #undef END
>  #undef REG16
>  #undef REG
> @@ -543,7 +620,9 @@ static const u8 *reg_offsets(const struct
> intel_engine_cs *engine)
>  !intel_engine_has_relative_mmio(engine));
>  
>   if (engine->class == RENDER_CLASS) {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + return dg2_rcs_offsets;
> + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12,
> 50))
>   return xehp_rcs_offsets;
>   else if (GRAPHICS_VER(engine->i915) >= 12)
>   return gen12_rcs_offsets;
> @@ -554,7 +633,9 @@ static const u8 *reg_offsets(const struct
> intel_engine_cs *engine)
>   else
>   return gen8_rcs_offsets;
>   } else {
> - if (GRAPHICS_VER(engine->i915) >= 12)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + return dg2_xcs_offsets;
> + else if (GRAPHICS_VER(engine->i915) >= 12)
>   return gen12_xcs_offsets;
>   else if (GRAPHICS_VER(engine->i915) >= 9)
>   return gen9_xcs_offsets;

[Intel-gfx] [PATCH v5 7/9] drm/i915/dg2: Add new LRI reg offsets

2021-08-05 Thread Matt Roper 
From: Akeem G Abodunrin 

New LRI register offsets were introduced for DG2, this patch adds
those extra registers, and create new register table for setting offsets
to compare with HW generated context image - especially for gt_lrc test.
Also updates general purpose register with scratch offset for DG2, in
order to use it for live_lrc_fixed selftest.

Cc: Chris P Wilson 
Cc: Prathap Kumar Valsan 
Signed-off-by: Akeem G Abodunrin 
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 85 -
 1 file changed, 83 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c 
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index bb4af4977920..6ba8daea2f56 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -226,6 +226,40 @@ static const u8 gen12_xcs_offsets[] = {
END
 };
 
+static const u8 dg2_xcs_offsets[] = {
+   NOP(1),
+   LRI(15, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   REG(0x120),
+   REG(0x124),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   END
+};
+
 static const u8 gen8_rcs_offsets[] = {
NOP(1),
LRI(14, POSTED),
@@ -525,6 +559,49 @@ static const u8 xehp_rcs_offsets[] = {
END
 };
 
+static const u8 dg2_rcs_offsets[] = {
+   NOP(1),
+   LRI(15, POSTED),
+   REG16(0x244),
+   REG(0x034),
+   REG(0x030),
+   REG(0x038),
+   REG(0x03c),
+   REG(0x168),
+   REG(0x140),
+   REG(0x110),
+   REG(0x1c0),
+   REG(0x1c4),
+   REG(0x1c8),
+   REG(0x180),
+   REG16(0x2b4),
+   REG(0x120),
+   REG(0x124),
+
+   NOP(1),
+   LRI(9, POSTED),
+   REG16(0x3a8),
+   REG16(0x28c),
+   REG16(0x288),
+   REG16(0x284),
+   REG16(0x280),
+   REG16(0x27c),
+   REG16(0x278),
+   REG16(0x274),
+   REG16(0x270),
+
+   LRI(3, POSTED),
+   REG(0x1b0),
+   REG16(0x5a8),
+   REG16(0x5ac),
+
+   NOP(6),
+   LRI(1, 0),
+   REG(0x0c8),
+
+   END
+};
+
 #undef END
 #undef REG16
 #undef REG
@@ -543,7 +620,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
   !intel_engine_has_relative_mmio(engine));
 
if (engine->class == RENDER_CLASS) {
-   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   return dg2_rcs_offsets;
+   else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
return xehp_rcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_rcs_offsets;
@@ -554,7 +633,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs 
*engine)
else
return gen8_rcs_offsets;
} else {
-   if (GRAPHICS_VER(engine->i915) >= 12)
+   if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
+   return dg2_xcs_offsets;
+   else if (GRAPHICS_VER(engine->i915) >= 12)
return gen12_xcs_offsets;
else if (GRAPHICS_VER(engine->i915) >= 9)
return gen9_xcs_offsets;
-- 
2.25.4