Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring

2023-11-14 Thread Coelho, Luciano
On Tue, 2023-11-14 at 11:35 +, Manna, Animesh wrote:
> 
> > -Original Message-
> > From: Coelho, Luciano 
> > Sent: Tuesday, November 14, 2023 4:47 PM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Cc: Nikula, Jani 
> > Subject: Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring
> > 
> > On Fri, 2023-11-10 at 08:55 +0530, Animesh Manna wrote:
> > > Refactor DSB implementation to be compatible with Xe driver.
> > > 
> > > v1: RFC version.
> > > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > > v3: Rebased on latest.
> > > v4:
> > > - Add boundary check in dsb_buffer_memset(). [Luca]
> > > - Use size_t instead of u32. [Luca]
> > > v5: WARN_ON() added for out of boudary case with some optimization.
> > [Luca]
> > 
> > ...and what is different in v6?
> 
> Rebased on latest and fix a rebase-miss which CI did not caught well. Before 
> merging want the green signal from CI.

Okay, it's good to mention that.

Anyway, my r-b is still valid. ;)

--
Cheers,
Luca.


Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring

2023-11-14 Thread Manna, Animesh


> -Original Message-
> From: Coelho, Luciano 
> Sent: Tuesday, November 14, 2023 4:47 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani 
> Subject: Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring
> 
> On Fri, 2023-11-10 at 08:55 +0530, Animesh Manna wrote:
> > Refactor DSB implementation to be compatible with Xe driver.
> >
> > v1: RFC version.
> > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > v3: Rebased on latest.
> > v4:
> > - Add boundary check in dsb_buffer_memset(). [Luca]
> > - Use size_t instead of u32. [Luca]
> > v5: WARN_ON() added for out of boudary case with some optimization.
> [Luca]
> 
> ...and what is different in v6?

Rebased on latest and fix a rebase-miss which CI did not caught well. Before 
merging want the green signal from CI.

Regards,
Animesh
> 
> --
> Cheers,
> Luca.


Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring

2023-11-14 Thread Coelho, Luciano
On Fri, 2023-11-10 at 08:55 +0530, Animesh Manna wrote:
> Refactor DSB implementation to be compatible with Xe driver.
> 
> v1: RFC version.
> v2: Make intel_dsb structure opaque from external usage. [Jani]
> v3: Rebased on latest.
> v4:
> - Add boundary check in dsb_buffer_memset(). [Luca]
> - Use size_t instead of u32. [Luca]
> v5: WARN_ON() added for out of boudary case with some optimization. [Luca]

...and what is different in v6?

--
Cheers,
Luca.


[Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring

2023-11-09 Thread Animesh Manna
Refactor DSB implementation to be compatible with Xe driver.

v1: RFC version.
v2: Make intel_dsb structure opaque from external usage. [Jani]
v3: Rebased on latest.
v4:
- Add boundary check in dsb_buffer_memset(). [Luca]
- Use size_t instead of u32. [Luca]
v5: WARN_ON() added for out of boudary case with some optimization. [Luca]

Cc: Jani Nikula 
Reviewed-by: Luca Coelho 
Signed-off-by: Animesh Manna 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/display/intel_dsb.c  | 98 +++
 .../gpu/drm/i915/display/intel_dsb_buffer.c   | 82 
 .../gpu/drm/i915/display/intel_dsb_buffer.h   | 29 ++
 4 files changed, 148 insertions(+), 62 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dsb_buffer.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dsb_buffer.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 239da40a401f..7e5d6a39d450 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -277,6 +277,7 @@ i915-y += \
display/intel_dpt.o \
display/intel_drrs.o \
display/intel_dsb.o \
+   display/intel_dsb_buffer.o \
display/intel_fb.o \
display/intel_fb_pin.o \
display/intel_fbc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c 
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 78b6fe24dcd8..9598d50f68f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -4,9 +4,6 @@
  *
  */
 
-#include "gem/i915_gem_internal.h"
-#include "gem/i915_gem_lmem.h"
-
 #include "i915_drv.h"
 #include "i915_irq.h"
 #include "i915_reg.h"
@@ -14,12 +11,13 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dsb.h"
+#include "intel_dsb_buffer.h"
 #include "intel_dsb_regs.h"
 #include "intel_vblank.h"
 #include "intel_vrr.h"
 #include "skl_watermark.h"
 
-struct i915_vma;
+#define CACHELINE_BYTES 64
 
 enum dsb_id {
INVALID_DSB = -1,
@@ -32,8 +30,7 @@ enum dsb_id {
 struct intel_dsb {
enum dsb_id id;
 
-   u32 *cmd_buf;
-   struct i915_vma *vma;
+   struct intel_dsb_buffer dsb_buf;
struct intel_crtc *crtc;
 
/*
@@ -109,15 +106,17 @@ static void intel_dsb_dump(struct intel_dsb *dsb)
 {
struct intel_crtc *crtc = dsb->crtc;
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-   const u32 *buf = dsb->cmd_buf;
int i;
 
drm_dbg_kms(>drm, "[CRTC:%d:%s] DSB %d commands {\n",
crtc->base.base.id, crtc->base.name, dsb->id);
for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
drm_dbg_kms(>drm,
-   " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
-   i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
+   " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4,
+   intel_dsb_buffer_read(>dsb_buf, i),
+   intel_dsb_buffer_read(>dsb_buf, i + 1),
+   intel_dsb_buffer_read(>dsb_buf, i + 2),
+   intel_dsb_buffer_read(>dsb_buf, i + 3));
drm_dbg_kms(>drm, "}\n");
 }
 
@@ -129,8 +128,6 @@ static bool is_dsb_busy(struct drm_i915_private *i915, enum 
pipe pipe,
 
 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
 {
-   u32 *buf = dsb->cmd_buf;
-
if (!assert_dsb_has_room(dsb))
return;
 
@@ -139,14 +136,13 @@ static void intel_dsb_emit(struct intel_dsb *dsb, u32 
ldw, u32 udw)
 
dsb->ins_start_offset = dsb->free_pos;
 
-   buf[dsb->free_pos++] = ldw;
-   buf[dsb->free_pos++] = udw;
+   intel_dsb_buffer_write(>dsb_buf, dsb->free_pos++, ldw);
+   intel_dsb_buffer_write(>dsb_buf, dsb->free_pos++, udw);
 }
 
 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
u32 opcode, i915_reg_t reg)
 {
-   const u32 *buf = dsb->cmd_buf;
u32 prev_opcode, prev_reg;
 
/*
@@ -157,8 +153,10 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb 
*dsb,
if (dsb->free_pos == 0)
return false;
 
-   prev_opcode = buf[dsb->ins_start_offset + 1] & ~DSB_REG_VALUE_MASK;
-   prev_reg = buf[dsb->ins_start_offset + 1] & DSB_REG_VALUE_MASK;
+   prev_opcode = intel_dsb_buffer_read(>dsb_buf,
+   dsb->ins_start_offset + 1) & 
~DSB_REG_VALUE_MASK;
+   prev_reg =  intel_dsb_buffer_read(>dsb_buf,
+ dsb->ins_start_offset + 1) & 
DSB_REG_VALUE_MASK;
 
return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg);
 }
@@ -191,6 +189,8 @@ static bool intel_dsb_prev_ins_is_indexed_write(struct 
intel_dsb *dsb, i915_reg_
 void intel_dsb_reg_write(struct intel_dsb *dsb,
 i915_reg_t reg, u32 val)
 {
+   u32 old_val;
+
/*
 * For