Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 04:08:43PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:34:58PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > > DSC params like the enable, compressed bpp, slice count and
> > > > dsc_split are added to the intel_crtc_state. These parameters
> > > > are set based on the requested mode and available link parameters
> > > > during the pipe configuration in atomic check phase.
> > > > These values are then later used to populate the remaining DSC
> > > > and RC parameters before enbaling DSC in atomic commit.
> > > >
> > > > v9:
> > > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > > for edp (Manasi)
> > > > v8:
> > > > * Check for DSC bpc not 0 (manasi)
> > > >
> > > > v7:
> > > > * Fix indentation in compute_m_n (Manasi)
> > > >
> > > > v6 (From Gaurav):
> > > > * Remove function call of intel_dp_compute_dsc_params() and
> > > > invoke intel_dp_compute_dsc_params() in the patch where
> > > > it is defined to fix compilation warning (Gaurav)
> > > >
> > > > v5:
> > > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > > >
> > > > v4:
> > > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > > >
> > > > v3:
> > > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > > >
> > > > v2:
> > > > * Add if-else for eDP/DP (Gaurav)
> > > >
> > > > Cc: Jani Nikula
> > > > Cc: Ville Syrjala
> > > > Cc: Anusha Srivatsa
> > > > Cc: Gaurav K Singh
> > > > Signed-off-by: Manasi Navare
> > > > Reviewed-by: Anusha Srivatsa
> > > > Acked-by: Jani Nikula
> > > > ---
> > > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > > 4 files changed, 155 insertions(+), 40 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > > b/drivers/gpu/drm/i915/intel_display.c
> > > > index fe045abb6472..18737bd82b68 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > > > intel_crtc *intel_crtc,
> > > >
> > > > pipe_config->fdi_lanes = lane;
> > > >
> > > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane,
> > > > fdi_dotclock,
> > > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane,
> > > > fdi_dotclock,
> > > >link_bw, _config->fdi_m_n, false);
> > > >
> > > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe,
> > > > pipe_config);
> > > > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m,
> > > > unsigned int n,
> > > > }
> > > >
> > > > void
> > > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > > + int nlanes,
> > > >int pixel_clock, int link_clock,
> > > >struct intel_link_m_n *m_n,
> > > >bool constant_n)
> > > > {
> > > > m_n->tu = 64;
> > > >
> > > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > > - link_clock * nlanes * 8,
> > > > - _n->gmch_m, _n->gmch_n,
> > > > - constant_n);
> > > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > > + if (compressed_bpp)
> > > > + compute_m_n(compressed_bpp * pixel_clock,
> > > > + link_clock * nlanes * 8,
> > > > + _n->gmch_m, _n->gmch_n,
> > > > + constant_n);
> > > > + else
> > > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > > + link_clock * nlanes * 8,
> > > > + _n->gmch_m, _n->gmch_n,
> > > > + constant_n);
> > > >
> > > > compute_m_n(pixel_clock, link_clock,
> > > > _n->link_m, _n->link_n,
> > > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > > b/drivers/gpu/drm/i915/intel_display.h
> > > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > > > (__i)++) \
> > > > for_each_if(plane)
> > > >
> > > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > > + int nlanes,
> > > > int pixel_clock, int link_clock,
> > > >
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 03:12:51PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the intel_crtc_state. These parameters
> > > are set based on the requested mode and available link parameters
> > > during the pipe configuration in atomic check phase.
> > > These values are then later used to populate the remaining DSC
> > > and RC parameters before enbaling DSC in atomic commit.
> > >
> > > v9:
> > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > for edp (Manasi)
> > > v8:
> > > * Check for DSC bpc not 0 (manasi)
> > >
> > > v7:
> > > * Fix indentation in compute_m_n (Manasi)
> > >
> > > v6 (From Gaurav):
> > > * Remove function call of intel_dp_compute_dsc_params() and
> > > invoke intel_dp_compute_dsc_params() in the patch where
> > > it is defined to fix compilation warning (Gaurav)
> > >
> > > v5:
> > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > >
> > > v4:
> > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > >
> > > v3:
> > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > >
> > > v2:
> > > * Add if-else for eDP/DP (Gaurav)
> > >
> > > Cc: Jani Nikula
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Cc: Gaurav K Singh
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Anusha Srivatsa
> > > Acked-by: Jani Nikula
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > 4 files changed, 155 insertions(+), 40 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index fe045abb6472..18737bd82b68 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > > intel_crtc *intel_crtc,
> > >
> > > pipe_config->fdi_lanes = lane;
> > >
> > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> > > link_bw, _config->fdi_m_n, false);
> > >
> > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > > int n,
> > > }
> > >
> > > void
> > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > +int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n)
> > > {
> > > m_n->tu = 64;
> > >
> > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > - link_clock * nlanes * 8,
> > > - _n->gmch_m, _n->gmch_n,
> > > - constant_n);
> > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > + if (compressed_bpp)
> > > + compute_m_n(compressed_bpp * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + _n->gmch_m, _n->gmch_n,
> > > + constant_n);
> > > + else
> > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + _n->gmch_m, _n->gmch_n,
> > > + constant_n);
> > >
> > > compute_m_n(pixel_clock, link_clock,
> > > _n->link_m, _n->link_n,
> > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > b/drivers/gpu/drm/i915/intel_display.h
> > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > >(__i)++) \
> > > for_each_if(plane)
> > >
> > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > + int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n);
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 6f66a38ba0b2..a88f9371dd32 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -47,6 +47,8 @@
> > >
> > > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > > +#define
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:34:58PM +0200, Ville Syrjälä wrote:
> On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the intel_crtc_state. These parameters
> > > are set based on the requested mode and available link parameters
> > > during the pipe configuration in atomic check phase.
> > > These values are then later used to populate the remaining DSC
> > > and RC parameters before enbaling DSC in atomic commit.
> > >
> > > v9:
> > > * Rebase on top of drm-tip that now uses fast_narrow config
> > > for edp (Manasi)
> > > v8:
> > > * Check for DSC bpc not 0 (manasi)
> > >
> > > v7:
> > > * Fix indentation in compute_m_n (Manasi)
> > >
> > > v6 (From Gaurav):
> > > * Remove function call of intel_dp_compute_dsc_params() and
> > > invoke intel_dp_compute_dsc_params() in the patch where
> > > it is defined to fix compilation warning (Gaurav)
> > >
> > > v5:
> > > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> > >
> > > v4:
> > > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> > >
> > > v3:
> > > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> > >
> > > v2:
> > > * Add if-else for eDP/DP (Gaurav)
> > >
> > > Cc: Jani Nikula
> > > Cc: Ville Syrjala
> > > Cc: Anusha Srivatsa
> > > Cc: Gaurav K Singh
> > > Signed-off-by: Manasi Navare
> > > Reviewed-by: Anusha Srivatsa
> > > Acked-by: Jani Nikula
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > > 4 files changed, 155 insertions(+), 40 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index fe045abb6472..18737bd82b68 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > > intel_crtc *intel_crtc,
> > >
> > > pipe_config->fdi_lanes = lane;
> > >
> > > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> > > link_bw, _config->fdi_m_n, false);
> > >
> > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > > int n,
> > > }
> > >
> > > void
> > > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > > +int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n)
> > > {
> > > m_n->tu = 64;
> > >
> > > - compute_m_n(bits_per_pixel * pixel_clock,
> > > - link_clock * nlanes * 8,
> > > - _n->gmch_m, _n->gmch_n,
> > > - constant_n);
> > > + /* For DSC, Data M/N calculation uses compressed BPP */
> > > + if (compressed_bpp)
> > > + compute_m_n(compressed_bpp * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + _n->gmch_m, _n->gmch_n,
> > > + constant_n);
> > > + else
> > > + compute_m_n(bits_per_pixel * pixel_clock,
> > > + link_clock * nlanes * 8,
> > > + _n->gmch_m, _n->gmch_n,
> > > + constant_n);
> > >
> > > compute_m_n(pixel_clock, link_clock,
> > > _n->link_m, _n->link_n,
> > > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > > b/drivers/gpu/drm/i915/intel_display.h
> > > index 5d50decbcbb5..b0b23e1e9392 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/intel_display.h
> > > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > >(__i)++) \
> > > for_each_if(plane)
> > >
> > > -void intel_link_compute_m_n(int bpp, int nlanes,
> > > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > > + int nlanes,
> > > int pixel_clock, int link_clock,
> > > struct intel_link_m_n *m_n,
> > > bool constant_n);
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 6f66a38ba0b2..a88f9371dd32 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -47,6 +47,8 @@
> > >
> > > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > > +#define
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 155 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..18737bd82b68 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, _config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - _n->gmch_m, _n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > _n->link_m, _n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6f66a38ba0b2..a88f9371dd32 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1924,6
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 155 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..18737bd82b68 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, _config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - _n->gmch_m, _n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > _n->link_m, _n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6f66a38ba0b2..a88f9371dd32 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1924,6
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > DSC params like the enable, compressed bpp, slice count and
> > dsc_split are added to the intel_crtc_state. These parameters
> > are set based on the requested mode and available link parameters
> > during the pipe configuration in atomic check phase.
> > These values are then later used to populate the remaining DSC
> > and RC parameters before enbaling DSC in atomic commit.
> >
> > v9:
> > * Rebase on top of drm-tip that now uses fast_narrow config
> > for edp (Manasi)
> > v8:
> > * Check for DSC bpc not 0 (manasi)
> >
> > v7:
> > * Fix indentation in compute_m_n (Manasi)
> >
> > v6 (From Gaurav):
> > * Remove function call of intel_dp_compute_dsc_params() and
> > invoke intel_dp_compute_dsc_params() in the patch where
> > it is defined to fix compilation warning (Gaurav)
> >
> > v5:
> > Add drm_dsc_cfg in intel_crtc_state (Manasi)
> >
> > v4:
> > * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> > * Add a comment why we need to check PSR while enabling DSC (Gaurav)
> >
> > v3:
> > * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
> >
> > v2:
> > * Add if-else for eDP/DP (Gaurav)
> >
> > Cc: Jani Nikula
> > Cc: Ville Syrjala
> > Cc: Anusha Srivatsa
> > Cc: Gaurav K Singh
> > Signed-off-by: Manasi Navare
> > Reviewed-by: Anusha Srivatsa
> > Acked-by: Jani Nikula
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 20 +++-
> > drivers/gpu/drm/i915/intel_display.h | 3 +-
> > drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> > 4 files changed, 155 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fe045abb6472..18737bd82b68 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> > intel_crtc *intel_crtc,
> >
> > pipe_config->fdi_lanes = lane;
> >
> > - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> >link_bw, _config->fdi_m_n, false);
> >
> > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> > @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned
> > int n,
> > }
> >
> > void
> > -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> > +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> > + int nlanes,
> >int pixel_clock, int link_clock,
> >struct intel_link_m_n *m_n,
> >bool constant_n)
> > {
> > m_n->tu = 64;
> >
> > - compute_m_n(bits_per_pixel * pixel_clock,
> > - link_clock * nlanes * 8,
> > - _n->gmch_m, _n->gmch_n,
> > - constant_n);
> > + /* For DSC, Data M/N calculation uses compressed BPP */
> > + if (compressed_bpp)
> > + compute_m_n(compressed_bpp * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> > + else
> > + compute_m_n(bits_per_pixel * pixel_clock,
> > + link_clock * nlanes * 8,
> > + _n->gmch_m, _n->gmch_n,
> > + constant_n);
> >
> > compute_m_n(pixel_clock, link_clock,
> > _n->link_m, _n->link_n,
> > diff --git a/drivers/gpu/drm/i915/intel_display.h
> > b/drivers/gpu/drm/i915/intel_display.h
> > index 5d50decbcbb5..b0b23e1e9392 100644
> > --- a/drivers/gpu/drm/i915/intel_display.h
> > +++ b/drivers/gpu/drm/i915/intel_display.h
> > @@ -407,7 +407,8 @@ struct intel_link_m_n {
> > (__i)++) \
> > for_each_if(plane)
> >
> > -void intel_link_compute_m_n(int bpp, int nlanes,
> > +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> > + int nlanes,
> > int pixel_clock, int link_clock,
> > struct intel_link_m_n *m_n,
> > bool constant_n);
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 6f66a38ba0b2..a88f9371dd32 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -47,6 +47,8 @@
> >
> > /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> > #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> > +#define DP_DSC_MIN_SUPPORTED_BPC 8
> > +#define DP_DSC_MAX_SUPPORTED_BPC 10
> >
> > /* DP DSC throughput values used for slice count calculations KPixels/s */
> > #define DP_DSC_PEAK_PIXEL_RATE 272
> > @@ -1924,6
Re: [Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> DSC params like the enable, compressed bpp, slice count and
> dsc_split are added to the intel_crtc_state. These parameters
> are set based on the requested mode and available link parameters
> during the pipe configuration in atomic check phase.
> These values are then later used to populate the remaining DSC
> and RC parameters before enbaling DSC in atomic commit.
>
> v9:
> * Rebase on top of drm-tip that now uses fast_narrow config
> for edp (Manasi)
> v8:
> * Check for DSC bpc not 0 (manasi)
>
> v7:
> * Fix indentation in compute_m_n (Manasi)
>
> v6 (From Gaurav):
> * Remove function call of intel_dp_compute_dsc_params() and
> invoke intel_dp_compute_dsc_params() in the patch where
> it is defined to fix compilation warning (Gaurav)
>
> v5:
> Add drm_dsc_cfg in intel_crtc_state (Manasi)
>
> v4:
> * Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
> * Add a comment why we need to check PSR while enabling DSC (Gaurav)
>
> v3:
> * Check PPR > max_cdclock to use 2 VDSC instances (Ville)
>
> v2:
> * Add if-else for eDP/DP (Gaurav)
>
> Cc: Jani Nikula
> Cc: Ville Syrjala
> Cc: Anusha Srivatsa
> Cc: Gaurav K Singh
> Signed-off-by: Manasi Navare
> Reviewed-by: Anusha Srivatsa
> Acked-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_display.c | 20 +++-
> drivers/gpu/drm/i915/intel_display.h | 3 +-
> drivers/gpu/drm/i915/intel_dp.c | 170 ++-
> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
> 4 files changed, 155 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index fe045abb6472..18737bd82b68 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct
> intel_crtc *intel_crtc,
>
> pipe_config->fdi_lanes = lane;
>
> - intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> + intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
> link_bw, _config->fdi_m_n, false);
>
> ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
> @@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned int
> n,
> }
>
> void
> -intel_link_compute_m_n(int bits_per_pixel, int nlanes,
> +intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
> +int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n)
> {
> m_n->tu = 64;
>
> - compute_m_n(bits_per_pixel * pixel_clock,
> - link_clock * nlanes * 8,
> - _n->gmch_m, _n->gmch_n,
> - constant_n);
> + /* For DSC, Data M/N calculation uses compressed BPP */
> + if (compressed_bpp)
> + compute_m_n(compressed_bpp * pixel_clock,
> + link_clock * nlanes * 8,
> + _n->gmch_m, _n->gmch_n,
> + constant_n);
> + else
> + compute_m_n(bits_per_pixel * pixel_clock,
> + link_clock * nlanes * 8,
> + _n->gmch_m, _n->gmch_n,
> + constant_n);
>
> compute_m_n(pixel_clock, link_clock,
> _n->link_m, _n->link_n,
> diff --git a/drivers/gpu/drm/i915/intel_display.h
> b/drivers/gpu/drm/i915/intel_display.h
> index 5d50decbcbb5..b0b23e1e9392 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -407,7 +407,8 @@ struct intel_link_m_n {
>(__i)++) \
> for_each_if(plane)
>
> -void intel_link_compute_m_n(int bpp, int nlanes,
> +void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
> + int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> bool constant_n);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6f66a38ba0b2..a88f9371dd32 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -47,6 +47,8 @@
>
> /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
> #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
> +#define DP_DSC_MIN_SUPPORTED_BPC 8
> +#define DP_DSC_MAX_SUPPORTED_BPC 10
>
> /* DP DSC throughput values used for slice count calculations KPixels/s */
> #define DP_DSC_PEAK_PIXEL_RATE 272
> @@ -1924,6 +1926,16 @@ static int intel_dp_compute_bpp(struct intel_dp
> *intel_dp,
> }
> }
>
> + /* If DSC is supported, use the max value reported by panel */
> + if (INTEL_GEN(dev_priv) >= 10 &&
> +
[Intel-gfx] [PATCH v6 13/28] drm/i915/dp: Compute DSC pipe config in atomic check
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
Cc: Gaurav K Singh
Signed-off-by: Manasi Navare
Reviewed-by: Anusha Srivatsa
Acked-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_display.c | 20 +++-
drivers/gpu/drm/i915/intel_display.h | 3 +-
drivers/gpu/drm/i915/intel_dp.c | 170 ++-
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
4 files changed, 155 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index fe045abb6472..18737bd82b68 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6434,7 +6434,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
- intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
+ intel_link_compute_m_n(pipe_config->pipe_bpp, 0, lane, fdi_dotclock,
link_bw, _config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
@@ -6671,17 +6671,25 @@ static void compute_m_n(unsigned int m, unsigned int n,
}
void
-intel_link_compute_m_n(int bits_per_pixel, int nlanes,
+intel_link_compute_m_n(int bits_per_pixel, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n)
{
m_n->tu = 64;
- compute_m_n(bits_per_pixel * pixel_clock,
- link_clock * nlanes * 8,
- _n->gmch_m, _n->gmch_n,
- constant_n);
+ /* For DSC, Data M/N calculation uses compressed BPP */
+ if (compressed_bpp)
+ compute_m_n(compressed_bpp * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
+ else
+ compute_m_n(bits_per_pixel * pixel_clock,
+ link_clock * nlanes * 8,
+ _n->gmch_m, _n->gmch_n,
+ constant_n);
compute_m_n(pixel_clock, link_clock,
_n->link_m, _n->link_n,
diff --git a/drivers/gpu/drm/i915/intel_display.h
b/drivers/gpu/drm/i915/intel_display.h
index 5d50decbcbb5..b0b23e1e9392 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -407,7 +407,8 @@ struct intel_link_m_n {
(__i)++) \
for_each_if(plane)
-void intel_link_compute_m_n(int bpp, int nlanes,
+void intel_link_compute_m_n(int bpp, uint16_t compressed_bpp,
+ int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
bool constant_n);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 6f66a38ba0b2..a88f9371dd32 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -47,6 +47,8 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
+#define DP_DSC_MIN_SUPPORTED_BPC 8
+#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1924,6 +1926,16 @@ static int intel_dp_compute_bpp(struct intel_dp
*intel_dp,
}
}
+ /* If DSC is supported, use the max value reported by panel */
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+ bpc = min_t(u8,
+ drm_dp_dsc_sink_max_color_depth(intel_dp->dsc_dpcd),
+ DP_DSC_MAX_SUPPORTED_BPC);
+ if (bpc)
+ bpp =
