Re: [Intel-gfx] [PATCH v6 15/15] drm/i915/display: Let PCON convert from RGB to YUV if it can
> -Original Message-
> From: Nautiyal, Ankit K
> Sent: Wednesday, December 16, 2020 5:01 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Shankar, Uma ;
> airl...@linux.ie; jani.nik...@linux.intel.com; ville.syrj...@linux.intel.com;
> Kulkarni, Vandita ; Sharma, Swati2
>
> Subject: [PATCH v6 15/15] drm/i915/display: Let PCON convert from RGB to YUV
> if it can
>
> If PCON has capability to convert RGB->YUV colorspace and also to 444->420
> downsampling then for any YUV420 only mode, we can let the PCON do all the
> conversion.
>
> v2: As suggested by Uma Shankar, considered case for colorspace
> BT709 and BT2020, and default to BT609. Also appended dir 'display' in commit
> message.
>
> v3: Fixed typo in condition for printing one of the error msg.
>
> Signed-off-by: Ankit Nautiyal
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 68 +++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
> 4 files changed, 58 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index fbc07a93504b..17eaa56c5a99 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3644,6 +3644,7 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
>
> + intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
> /*
>* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
> @@ -3731,7 +3732,7 @@ static void hsw_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> intel_ddi_init_dp_buf_reg(encoder, crtc_state);
> if (!is_mst)
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> - intel_dp_configure_protocol_converter(intel_dp);
> + intel_dp_configure_protocol_converter(intel_dp, crtc_state);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> true);
> intel_dp_sink_set_fec_ready(intel_dp, crtc_state); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 4c01c7c23dfd..2009ae9e9678 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1460,6 +1460,7 @@ struct intel_dp {
> int pcon_max_frl_bw;
> u8 max_bpc;
> bool ycbcr_444_to_420;
> + bool rgb_to_ycbcr;
> } dfp;
>
> /* Display stream compression testing */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index abc9b772d1c8..366b2e4e7f4a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -651,6 +651,10 @@ intel_dp_output_format(struct drm_connector
> *connector,
> !drm_mode_is_420_only(info, mode))
> return INTEL_OUTPUT_FORMAT_RGB;
>
> + if (intel_dp->dfp.rgb_to_ycbcr &&
> + intel_dp->dfp.ycbcr_444_to_420)
> + return INTEL_OUTPUT_FORMAT_RGB;
> +
> if (intel_dp->dfp.ycbcr_444_to_420)
> return INTEL_OUTPUT_FORMAT_YCBCR444;
> else
> @@ -4311,7 +4315,8 @@ static void intel_dp_enable_port(struct intel_dp
> *intel_dp,
> intel_de_posting_read(dev_priv, intel_dp->output_reg); }
>
> -void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
> +void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> +const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> u8 tmp;
> @@ -4338,14 +4343,34 @@ void intel_dp_configure_protocol_converter(struct
> intel_dp *intel_dp)
> drm_dbg_kms(&i915->drm,
> "Failed to set protocol converter YCbCr 4:2:0
> conversion mode to %s\n",
> enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
> -
> - tmp = 0;
> -
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> -DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
> + if (intel_dp->dfp.rgb_to_ycbcr) {
> + bool bt2020, bt709;
> +
> + bt2020 =
> drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> + intel_dp-
> >downstream_ports,
> +
> DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
Next line should match the parenthesis, seems off.
> + bt709 =
> drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> + intel_dp-
> >downstream_ports,
[Intel-gfx] [PATCH v6 15/15] drm/i915/display: Let PCON convert from RGB to YUV if it can
If PCON has capability to convert RGB->YUV colorspace and also
to 444->420 downsampling then for any YUV420 only mode, we can
let the PCON do all the conversion.
v2: As suggested by Uma Shankar, considered case for colorspace
BT709 and BT2020, and default to BT609. Also appended dir
'display' in commit message.
v3: Fixed typo in condition for printing one of the error msg.
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +-
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 68 +++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +-
4 files changed, 58 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fbc07a93504b..17eaa56c5a99 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3644,6 +3644,7 @@ static void tgl_ddi_pre_enable_dp(struct
intel_atomic_state *state,
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
+ intel_dp_configure_protocol_converter(intel_dp, crtc_state);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
/*
* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
@@ -3731,7 +3732,7 @@ static void hsw_ddi_pre_enable_dp(struct
intel_atomic_state *state,
intel_ddi_init_dp_buf_reg(encoder, crtc_state);
if (!is_mst)
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
- intel_dp_configure_protocol_converter(intel_dp);
+ intel_dp_configure_protocol_converter(intel_dp, crtc_state);
intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
true);
intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4c01c7c23dfd..2009ae9e9678 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1460,6 +1460,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+ bool rgb_to_ycbcr;
} dfp;
/* Display stream compression testing */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index abc9b772d1c8..366b2e4e7f4a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -651,6 +651,10 @@ intel_dp_output_format(struct drm_connector *connector,
!drm_mode_is_420_only(info, mode))
return INTEL_OUTPUT_FORMAT_RGB;
+ if (intel_dp->dfp.rgb_to_ycbcr &&
+ intel_dp->dfp.ycbcr_444_to_420)
+ return INTEL_OUTPUT_FORMAT_RGB;
+
if (intel_dp->dfp.ycbcr_444_to_420)
return INTEL_OUTPUT_FORMAT_YCBCR444;
else
@@ -4311,7 +4315,8 @@ static void intel_dp_enable_port(struct intel_dp
*intel_dp,
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
-void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
+void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
+ const struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 tmp;
@@ -4338,14 +4343,34 @@ void intel_dp_configure_protocol_converter(struct
intel_dp *intel_dp)
drm_dbg_kms(&i915->drm,
"Failed to set protocol converter YCbCr 4:2:0
conversion mode to %s\n",
enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
-
- tmp = 0;
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
+ if (intel_dp->dfp.rgb_to_ycbcr) {
+ bool bt2020, bt709;
+
+ bt2020 =
drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
+
intel_dp->downstream_ports,
+
DP_DS_HDMI_BT2020_RGB_YCBCR_CONV);
+ bt709 =
drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
+
intel_dp->downstream_ports,
+
DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
+ switch (crtc_state->infoframes.vsc.colorimetry) {
+ case DP_COLORIMETRY_BT2020_RGB:
+ case DP_COLORIMETRY_BT2020_YCC:
+ tmp = bt2020 ? DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE :
0;
+ break;
+ case DP_COLORIMETRY_BT709_YCC:
+ case DP_COLORIMETRY_XVYCC_709:
+ tmp = bt709 ? DP_CONVERSION_BT709_RGB_YC
