Re: [Intel-gfx] [PATCH v9] drm/i915/color: Extract icl_read_luts()
On Tue, Mar 17, 2020 at 07:27:36PM +0530, Swati Sharma wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl specific feature.
>
> v2: -readout code for multisegmented gamma has to come
> up with some intermediate entries that aren't preserved
> in hardware (Jani N)
> -linear interpolation (Ville)
> -moved common code to check gamma_enable to specific funcs,
> since icl doesn't support that
> v3: -use u16 instead of __u16 [Jani N]
> -used single lut [Jani N]
> -improved and more readable for loops [Jani N]
> -read values directly to actual locations and then fill gaps [Jani N]
> -moved cleaning to patch 1 [Jani N]
> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
> make it similar to icl_load_luts()
> -renamed icl_compute_interpolated_gamma_blob() to
> icl_compute_interpolated_gamma_lut_values() more sensible, I guess
> v4: -removed interpolated func for creating gamma lut values
> -removed readouts of fine and coarse segments, failure to read
> PAL_PREC_DATA
> correctly
> v5: -added gamma_enable check inside read_luts()
> v6: -renamed intel_color_lut_entry_equal() to intel_color_lut_entries_equal()
> [Ville]
> -changed if-else to switch [Ville]
> -removed intel_color_lut_entry_multi_equal() [Ville]
> v7: -checkpatch warnings
> v8: -rebased
> v9: -rebased, aligned with Ville's style of gamma cleanup
>
> Signed-off-by: Swati Sharma
> Reviewed-by: Mika Kahola
Hmm. Did I not send out the mail saying that I pushed this? Maybe not.
Well, doing that now. Pushed to dinq. Thanks for the patch and review.
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 121 ++---
> drivers/gpu/drm/i915/i915_reg.h| 6 +
> 2 files changed, 109 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index c1cce93a1c25..98ece9cd7cdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -460,6 +460,16 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry,
> u32 val)
> entry->blue =
> intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
> }
>
> +static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32
> udw)
> +{
> + entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
> +
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
> + entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) <<
> 6 |
> +
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
> + entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6
> |
> +
> REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
> +}
> +
> static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -893,7 +903,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> struct intel_dsb *dsb = intel_dsb_get(crtc);
> enum pipe pipe = crtc->pipe;
>
> - /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
> + /* FIXME LUT entries are 16 bit only, so we can prog 0x max */
> intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
> intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
> intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
> @@ -1630,6 +1640,24 @@ static int glk_gamma_precision(const struct
> intel_crtc_state *crtc_state)
> }
> }
>
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +}
> +
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
> *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1641,7 +1669,9 @@ int intel_color_get_gamma_bit_precision(const struct
> intel_crtc_state *crtc_stat
> else
> return i9xx_gamma_precision(crtc_state);
> } else {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
[Intel-gfx] [PATCH v9] drm/i915/color: Extract icl_read_luts()
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
v2: -readout code for multisegmented gamma has to come
up with some intermediate entries that aren't preserved
in hardware (Jani N)
-linear interpolation (Ville)
-moved common code to check gamma_enable to specific funcs,
since icl doesn't support that
v3: -use u16 instead of __u16 [Jani N]
-used single lut [Jani N]
-improved and more readable for loops [Jani N]
-read values directly to actual locations and then fill gaps [Jani N]
-moved cleaning to patch 1 [Jani N]
-renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
make it similar to icl_load_luts()
-renamed icl_compute_interpolated_gamma_blob() to
icl_compute_interpolated_gamma_lut_values() more sensible, I guess
v4: -removed interpolated func for creating gamma lut values
-removed readouts of fine and coarse segments, failure to read PAL_PREC_DATA
correctly
v5: -added gamma_enable check inside read_luts()
v6: -renamed intel_color_lut_entry_equal() to intel_color_lut_entries_equal()
[Ville]
-changed if-else to switch [Ville]
-removed intel_color_lut_entry_multi_equal() [Ville]
v7: -checkpatch warnings
v8: -rebased
v9: -rebased, aligned with Ville's style of gamma cleanup
Signed-off-by: Swati Sharma
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_color.c | 121 ++---
drivers/gpu/drm/i915/i915_reg.h| 6 +
2 files changed, 109 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index c1cce93a1c25..98ece9cd7cdd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -460,6 +460,16 @@ static void ilk_lut_10_pack(struct drm_color_lut *entry,
u32 val)
entry->blue =
intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
}
+static void icl_lut_multi_seg_pack(struct drm_color_lut *entry, u32 ldw, u32
udw)
+{
+ entry->red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, udw) << 6 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, ldw);
+ entry->green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, udw) <<
6 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, ldw);
+ entry->blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, udw) << 6
|
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, ldw);
+}
+
static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -893,7 +903,7 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
struct intel_dsb *dsb = intel_dsb_get(crtc);
enum pipe pipe = crtc->pipe;
- /* Fixme: LUT entries are 16 bit only, so we can prog 0x max */
+ /* FIXME LUT entries are 16 bit only, so we can prog 0x max */
intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
@@ -1630,6 +1640,24 @@ static int glk_gamma_precision(const struct
intel_crtc_state *crtc_state)
}
}
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ return 16;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+}
+
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state
*crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1641,7 +1669,9 @@ int intel_color_get_gamma_bit_precision(const struct
intel_crtc_state *crtc_stat
else
return i9xx_gamma_precision(crtc_state);
} else {
- if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_gamma_precision(crtc_state);
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -1658,9 +1688,9 @@ static bool err_check(struct
