Re: [Intel-gfx] [Qemu-devel] [IGDVFIO] [PATCH 3/8] RFC and help completing: Intel IGD Direct Assignment with VFIO
Il 24/09/2014 22:57, Alex Williamson ha scritto: > Right, that's the physical mapping, Andy's patches are mimicking that > behavior virtually. Seabios reserves memory, creates e820 entries, and > "maps" the hardware by writing to these registers. That triggers QEMU > to adjust the MemoryRegion in the guest address space which is an mmap > to the host address space, using /dev/mem for now, but hopefully the > vfio file descriptor in the future (I should be careful what I hope > for). Yeah, I remember discussing that with Andrew on IRC. So he did implement that idea. > The opregion is pretty trivial because the write is to the IGD itself. > The others are to the host bridge, so we need to figure out what sort of > abstraction makes sense to get that back into vfio code. Do we have to support all chipsets? IIUC the more recent devices need fewer and fewer "backdoors". Paolo > Perhaps vfio creates all the memory regions and registers them into an > igd service and the host bridge can make calls like: > > gtt = igd_get_gtt_mr(); > > which returns NULL and nothing happens or the registered MemoryRegion > and the host bridge places it into the address space. Thanks, ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [Qemu-devel] [IGDVFIO] [PATCH 3/8] RFC and help completing: Intel IGD Direct Assignment with VFIO
On Wed, 2014-09-24 at 22:31 +0200, Paolo Bonzini wrote: > Il 24/09/2014 21:47, Alex Williamson ha scritto: > > So the opregion is mapped by a config write on the IGD device itself and > > the other 3 regions, that we know about so far, are mapped via writes to > > the host bridge. > > AFAIU the opregion is mapped by the (host) BIOS, that writes the address > to a well-known scratch dword in the configuration space. The host > reads from the dword and finds the opregion that way. Right, that's the physical mapping, Andy's patches are mimicking that behavior virtually. Seabios reserves memory, creates e820 entries, and "maps" the hardware by writing to these registers. That triggers QEMU to adjust the MemoryRegion in the guest address space which is an mmap to the host address space, using /dev/mem for now, but hopefully the vfio file descriptor in the future (I should be careful what I hope for). The opregion is pretty trivial because the write is to the IGD itself. The others are to the host bridge, so we need to figure out what sort of abstraction makes sense to get that back into vfio code. Perhaps vfio creates all the memory regions and registers them into an igd service and the host bridge can make calls like: gtt = igd_get_gtt_mr(); which returns NULL and nothing happens or the registered MemoryRegion and the host bridge places it into the address space. Thanks, Alex ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
