Re: [Intel-gfx] [RFC 03/39] drm/i915: Explicit power enable during deferred context initialisation

2015-07-21 Thread Daniel Vetter 
On Fri, Jul 17, 2015 at 03:33:12PM +0100, john.c.harri...@intel.com wrote:
 From: John Harrison john.c.harri...@intel.com
 
 A later patch in this series re-organises the batch buffer submission
 code. Part of that is to reduce the scope of a pm_get/put pair.
 Specifically, they previously wrapped the entire submission path from
 the very start to the very end, now they only wrap the actual hardware
 submission part in the back half.
 
 While that is a good thing in general, it causes a problem with the
 deferred context initialisation. That is done quite early on in the
 execbuf code path - it happens at context validation time rather than
 context switch time. Some of the deferred work requires the power to
 be enabled. Hence this patch adds an explicit power reference count to
 the deferred initialisation code itself.

The main reason for grabbing rpm for the entire execbuf is writing ptes
for global gtt. This happens on gen6 due to some hilarious tlb aliasing hw
bug where we have to bind objects into both ggtt and ppgtt.
-Daniel

 
 Change-Id: Id7b1535dfd8809a2bd5546272de2bbec39da2868
 Issue: GMINL-5159
 Signed-off-by: John Harrison john.c.harri...@intel.com
 ---
  drivers/gpu/drm/i915/intel_lrc.c | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
 b/drivers/gpu/drm/i915/intel_lrc.c
 index 18dbd5c..8aa9a18 100644
 --- a/drivers/gpu/drm/i915/intel_lrc.c
 +++ b/drivers/gpu/drm/i915/intel_lrc.c
 @@ -2317,12 +2317,15 @@ int intel_lr_context_deferred_create(struct 
 intel_context *ctx,
   WARN_ON(ctx-legacy_hw_ctx.rcs_state != NULL);
   WARN_ON(ctx-engine[ring-id].state);
  
 + intel_runtime_pm_get(dev-dev_private);
 +
   context_size = round_up(get_lr_context_size(ring), 4096);
  
   ctx_obj = i915_gem_alloc_object(dev, context_size);
   if (!ctx_obj) {
   DRM_DEBUG_DRIVER(Alloc LRC backing obj failed.\n);
 - return -ENOMEM;
 + ret = -ENOMEM;
 + goto error_pm;
   }
  
   if (is_global_default_ctx) {
 @@ -2331,7 +2334,7 @@ int intel_lr_context_deferred_create(struct 
 intel_context *ctx,
   DRM_DEBUG_DRIVER(Pin LRC backing obj failed: %d\n,
   ret);
   drm_gem_object_unreference(ctx_obj-base);
 - return ret;
 + goto error_pm;
   }
   }
  
 @@ -2415,6 +2418,7 @@ int intel_lr_context_deferred_create(struct 
 intel_context *ctx,
   ctx-rcs_initialized = true;
   }
  
 + intel_runtime_pm_put(dev-dev_private);
   return 0;
  
  error:
 @@ -2428,6 +2432,8 @@ error_unpin_ctx:
   if (is_global_default_ctx)
   i915_gem_object_ggtt_unpin(ctx_obj);
   drm_gem_object_unreference(ctx_obj-base);
 +error_pm:
 + intel_runtime_pm_put(dev-dev_private);
   return ret;
  }
  
 -- 
 1.9.1
 
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Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] [RFC 03/39] drm/i915: Explicit power enable during deferred context initialisation

2015-07-17 Thread John . C . Harrison 
From: John Harrison john.c.harri...@intel.com

A later patch in this series re-organises the batch buffer submission
code. Part of that is to reduce the scope of a pm_get/put pair.
Specifically, they previously wrapped the entire submission path from
the very start to the very end, now they only wrap the actual hardware
submission part in the back half.

While that is a good thing in general, it causes a problem with the
deferred context initialisation. That is done quite early on in the
execbuf code path - it happens at context validation time rather than
context switch time. Some of the deferred work requires the power to
be enabled. Hence this patch adds an explicit power reference count to
the deferred initialisation code itself.

Change-Id: Id7b1535dfd8809a2bd5546272de2bbec39da2868
Issue: GMINL-5159
Signed-off-by: John Harrison john.c.harri...@intel.com
---
 drivers/gpu/drm/i915/intel_lrc.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 18dbd5c..8aa9a18 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2317,12 +2317,15 @@ int intel_lr_context_deferred_create(struct 
intel_context *ctx,
WARN_ON(ctx-legacy_hw_ctx.rcs_state != NULL);
WARN_ON(ctx-engine[ring-id].state);
 
+   intel_runtime_pm_get(dev-dev_private);
+
context_size = round_up(get_lr_context_size(ring), 4096);
 
ctx_obj = i915_gem_alloc_object(dev, context_size);
if (!ctx_obj) {
DRM_DEBUG_DRIVER(Alloc LRC backing obj failed.\n);
-   return -ENOMEM;
+   ret = -ENOMEM;
+   goto error_pm;
}
 
if (is_global_default_ctx) {
@@ -2331,7 +2334,7 @@ int intel_lr_context_deferred_create(struct intel_context 
*ctx,
DRM_DEBUG_DRIVER(Pin LRC backing obj failed: %d\n,
ret);
drm_gem_object_unreference(ctx_obj-base);
-   return ret;
+   goto error_pm;
}
}
 
@@ -2415,6 +2418,7 @@ int intel_lr_context_deferred_create(struct intel_context 
*ctx,
ctx-rcs_initialized = true;
}
 
+   intel_runtime_pm_put(dev-dev_private);
return 0;
 
 error:
@@ -2428,6 +2432,8 @@ error_unpin_ctx:
if (is_global_default_ctx)
i915_gem_object_ggtt_unpin(ctx_obj);
drm_gem_object_unreference(ctx_obj-base);
+error_pm:
+   intel_runtime_pm_put(dev-dev_private);
return ret;
 }
 
-- 
1.9.1

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