subject:"\[Intel\-gfx\] \[RFC 1\/3\] drm\/i915\: Define and compute Transcoder CMRR registers"

[Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

2023-11-15 Thread Mitul Golani

Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.

--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 23 ++-
 .../drm/i915/display/intel_display_types.h|  6 +
 drivers/gpu/drm/i915/display/intel_vrr.c  | 22 ++
 drivers/gpu/drm/i915/i915_reg.h   | 10 
 4 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 125903007a29..f99d2de840bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct 
intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != 
new_crtc_state->vrr.pipeline_full;
 }
 
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+   const struct intel_crtc_state *new_crtc_state)
+{
+   return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+   old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 const struct intel_crtc_state *new_crtc_state)
 {
@@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
} \
 } while (0)
 
+#define PIPE_CONF_CHECK_LLI(name) do { \
+   if (current_config->name != pipe_config->name) { \
+   pipe_config_mismatch(fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+   ret = false; \
+   } \
+} while (0)
+
 #define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc,  __stringify(name), \
@@ -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+   PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
 
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
 #undef PIPE_CONF_CHECK_BOOL
 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
 #undef PIPE_CONF_CHECK_P
@@ -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct 
intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
 
-   if (vrr_params_changed(old_crtc_state, new_crtc_state))
+   if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+   cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9a44350ba05d..e42a0807227b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1406,6 +1406,12 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
 
+   /* Content Match Refresh Rate state */
+   struct {
+   bool enable;
+   u64 cmrr_n, cmrr_m;
+   } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..c889b0aa69a4 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
return;
}
 
+   if (crtc_state->cmrr.enable) {
+   intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+  VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+   intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+  upper_32_bits(crtc_state->cmrr.cmrr_m));
+   intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+  lower_32_bits(crtc_state->cmrr.cmrr_m));
+   intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+  upper_32_bits(crtc_state->cmrr.cmrr_n));
+

Re: [Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

2023-11-15 Thread Golani, Mitulkumar Ajitkumar

Thanks @Jani Nikula

Addressed all review comments.

Regards,
Mitul

> -Original Message-
> From: Jani Nikula 
> Sent: Wednesday, November 15, 2023 2:17 PM
> To: Golani, Mitulkumar Ajitkumar ;
> intel-gfx@lists.freedesktop.org
> Cc: Syrjala, Ville 
> Subject: Re: [Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder
> CMRR registers
> 
> On Wed, 15 Nov 2023, Mitul Golani
>  wrote:
> > Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR
> > function, with the necessary bitfields.
> > Compute these registers when CMRR is enabled, extending Adaptive
> > refresh rate capabilities.
> >
> > Signed-off-by: Mitul Golani 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  | 23 -
> >  .../drm/i915/display/intel_display_types.h|  6 +
> >  drivers/gpu/drm/i915/display/intel_vrr.c  | 25 ++-
> >  drivers/gpu/drm/i915/i915_reg.h   | 14 +++
> >  4 files changed, 66 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 125903007a29..f99d2de840bc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct
> intel_crtc_state *old_crtc_state,
> > old_crtc_state->vrr.pipeline_full !=
> > new_crtc_state->vrr.pipeline_full;
> >  }
> >
> > +static bool cmrr_params_changed(const struct intel_crtc_state
> *old_crtc_state,
> > +   const struct intel_crtc_state *new_crtc_state)
> {
> > +   return old_crtc_state->cmrr.cmrr_m != new_crtc_state-
> >cmrr.cmrr_m ||
> > +   old_crtc_state->cmrr.cmrr_n != new_crtc_state-
> >cmrr.cmrr_n; }
> > +
> >  static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
> >  const struct intel_crtc_state *new_crtc_state)  { @@
> -5067,6
> > +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> > } \
> >  } while (0)
> >
> > +#define PIPE_CONF_CHECK_LLI(name) do { \
> > +   if (current_config->name != pipe_config->name) { \
> > +   pipe_config_mismatch(fastset, crtc, __stringify(name), \
> > +"(expected %lli, found %lli)", \
> > +current_config->name, \
> > +pipe_config->name); \
> > +   ret = false; \
> > +   } \
> > +} while (0)
> > +
> >  #define PIPE_CONF_CHECK_BOOL(name) do { \
> > if (current_config->name != pipe_config->name) { \
> > pipe_config_mismatch(fastset, crtc,  __stringify(name), \ @@
> > -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_I(vrr.flipline);
> > PIPE_CONF_CHECK_I(vrr.pipeline_full);
> > PIPE_CONF_CHECK_I(vrr.guardband);
> > +   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> > +   PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> > }
> >
> >  #undef PIPE_CONF_CHECK_X
> >  #undef PIPE_CONF_CHECK_I
> > +#undef PIPE_CONF_CHECK_LLI
> >  #undef PIPE_CONF_CHECK_BOOL
> >  #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE  #undef
> PIPE_CONF_CHECK_P @@
> > -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct
> intel_atomic_state *state,
> > intel_crtc_needs_fastset(new_crtc_state))
> > icl_set_pipe_chicken(new_crtc_state);
> >
> > -   if (vrr_params_changed(old_crtc_state, new_crtc_state))
> > +   if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
> > +   cmrr_params_changed(old_crtc_state, new_crtc_state))
> > intel_vrr_set_transcoder_timings(new_crtc_state);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 9a44350ba05d..e42a0807227b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1406,6 +1406,12 @@ struct intel_crtc_state {
> > u16 flipline, vmin, vmax, guardband;
> > } vrr;
> >
> > +   /* Content Match Refresh Rate state */
> > +   struct {
> > +   bool enable;
> > +   u64 cmrr_n, cmrr_m;
> >

Re: [Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

2023-11-15 Thread Jani Nikula

On Wed, 15 Nov 2023, Mitul Golani  wrote:
> Add register definitions for Transcoder Fixed Average
> Vtotal mode/CMRR function, with the necessary bitfields.
> Compute these registers when CMRR is enabled, extending
> Adaptive refresh rate capabilities.
>
> Signed-off-by: Mitul Golani 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 23 -
>  .../drm/i915/display/intel_display_types.h|  6 +
>  drivers/gpu/drm/i915/display/intel_vrr.c  | 25 ++-
>  drivers/gpu/drm/i915/i915_reg.h   | 14 +++
>  4 files changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 125903007a29..f99d2de840bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct 
> intel_crtc_state *old_crtc_state,
>   old_crtc_state->vrr.pipeline_full != 
> new_crtc_state->vrr.pipeline_full;
>  }
>  
> +static bool cmrr_params_changed(const struct intel_crtc_state 
> *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state)
> +{
> + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
> +}
> +
>  static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state)
>  {
> @@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct 
> intel_crtc_state *current_config,
>   } \
>  } while (0)
>  
> +#define PIPE_CONF_CHECK_LLI(name) do { \
> + if (current_config->name != pipe_config->name) { \
> + pipe_config_mismatch(fastset, crtc, __stringify(name), \
> +  "(expected %lli, found %lli)", \
> +  current_config->name, \
> +  pipe_config->name); \
> + ret = false; \
> + } \
> +} while (0)
> +
>  #define PIPE_CONF_CHECK_BOOL(name) do { \
>   if (current_config->name != pipe_config->name) { \
>   pipe_config_mismatch(fastset, crtc,  __stringify(name), \
> @@ -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct 
> intel_crtc_state *current_config,
>   PIPE_CONF_CHECK_I(vrr.flipline);
>   PIPE_CONF_CHECK_I(vrr.pipeline_full);
>   PIPE_CONF_CHECK_I(vrr.guardband);
> + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>   }
>  
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
> +#undef PIPE_CONF_CHECK_LLI
>  #undef PIPE_CONF_CHECK_BOOL
>  #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
>  #undef PIPE_CONF_CHECK_P
> @@ -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct 
> intel_atomic_state *state,
>   intel_crtc_needs_fastset(new_crtc_state))
>   icl_set_pipe_chicken(new_crtc_state);
>  
> - if (vrr_params_changed(old_crtc_state, new_crtc_state))
> + if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
> + cmrr_params_changed(old_crtc_state, new_crtc_state))
>   intel_vrr_set_transcoder_timings(new_crtc_state);
>   }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9a44350ba05d..e42a0807227b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1406,6 +1406,12 @@ struct intel_crtc_state {
>   u16 flipline, vmin, vmax, guardband;
>   } vrr;
>  
> + /* Content Match Refresh Rate state */
> + struct {
> + bool enable;
> + u64 cmrr_n, cmrr_m;
> + } cmrr;
> +
>   /* Stream Splitter for eDP MSO */
>   struct {
>   bool enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5d905f932cb4..4aeccbbf1d2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct 
> intel_crtc_state *crtc_state)
>   return;
>   }
>  
> + if (crtc_state->cmrr.enable) {
> + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
> +VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
> + intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
> +upper_32_bits(crtc_state->cmrr.cmrr_m));
> + intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
> +lower_32_bits(crtc_state->cmrr.cmrr_m));
> + intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
> +

[Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

2023-11-14 Thread Mitul Golani

Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.

Signed-off-by: Mitul Golani 
---
 drivers/gpu/drm/i915/display/intel_display.c  | 23 -
 .../drm/i915/display/intel_display_types.h|  6 +
 drivers/gpu/drm/i915/display/intel_vrr.c  | 25 ++-
 drivers/gpu/drm/i915/i915_reg.h   | 14 +++
 4 files changed, 66 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 125903007a29..f99d2de840bc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -921,6 +921,13 @@ static bool vrr_params_changed(const struct 
intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != 
new_crtc_state->vrr.pipeline_full;
 }
 
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+   const struct intel_crtc_state *new_crtc_state)
+{
+   return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+   old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 const struct intel_crtc_state *new_crtc_state)
 {
@@ -5067,6 +5074,16 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
} \
 } while (0)
 
+#define PIPE_CONF_CHECK_LLI(name) do { \
+   if (current_config->name != pipe_config->name) { \
+   pipe_config_mismatch(fastset, crtc, __stringify(name), \
+"(expected %lli, found %lli)", \
+current_config->name, \
+pipe_config->name); \
+   ret = false; \
+   } \
+} while (0)
+
 #define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
pipe_config_mismatch(fastset, crtc,  __stringify(name), \
@@ -5447,10 +5464,13 @@ intel_pipe_config_compare(const struct intel_crtc_state 
*current_config,
PIPE_CONF_CHECK_I(vrr.flipline);
PIPE_CONF_CHECK_I(vrr.pipeline_full);
PIPE_CONF_CHECK_I(vrr.guardband);
+   PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+   PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
 
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
 #undef PIPE_CONF_CHECK_BOOL
 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
 #undef PIPE_CONF_CHECK_P
@@ -6790,7 +6810,8 @@ static void intel_pre_update_crtc(struct 
intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
 
-   if (vrr_params_changed(old_crtc_state, new_crtc_state))
+   if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+   cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9a44350ba05d..e42a0807227b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1406,6 +1406,12 @@ struct intel_crtc_state {
u16 flipline, vmin, vmax, guardband;
} vrr;
 
+   /* Content Match Refresh Rate state */
+   struct {
+   bool enable;
+   u64 cmrr_n, cmrr_m;
+   } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5d905f932cb4..4aeccbbf1d2a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -199,6 +199,19 @@ void intel_vrr_set_transcoder_timings(const struct 
intel_crtc_state *crtc_state)
return;
}
 
+   if (crtc_state->cmrr.enable) {
+   intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
+  VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state));
+   intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder),
+  upper_32_bits(crtc_state->cmrr.cmrr_m));
+   intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder),
+  lower_32_bits(crtc_state->cmrr.cmrr_m));
+   intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder),
+  upper_32_bits(crtc_state->cmrr.cmrr_n));
+   intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder),
+

[Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

Re: [Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

Re: [Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

[Intel-gfx] [RFC 1/3] drm/i915: Define and compute Transcoder CMRR registers

4 matches

Site Navigation

Mail list logo

Footer information