Re: [Intel-gfx] [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
On Mon, Oct 29, 2018 at 12:19:37PM +0200, Jani Nikula wrote:
> On Tue, 23 Oct 2018, Rodrigo Vivi wrote:
> > RANGE makes it longer, but clear.
>
> IS_GEN_RANGE() was the first proposal, but in review this was changed to
> IS_GEN() following IS_REVID() and IS__REVID().
>
> IMO unnecessary change.
consider this one dropped then.
other 2 patches from this series got pushed.
Thanks,
Rodrigo.
>
> BR,
> Jani.
>
> >
> > Diff generated with:
> >
> > sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
> >
> > Cc: Tvrtko Ursulin
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/i915_perf.c| 4 ++--
> > drivers/gpu/drm/i915/intel_bios.c | 2 +-
> > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> > drivers/gpu/drm/i915/intel_fbc.c| 2 +-
> > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 8
> > drivers/gpu/drm/i915/intel_uncore.c | 12 ++--
> > 9 files changed, 18 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 5b37d5f8e132..3deab30388f2 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void
> > *unused)
> > if (IS_BROXTON(dev_priv)) {
> > seq_printf(m, "DC3 -> DC5 count: %d\n",
> >I915_READ(BXT_CSR_DC3_DC5_COUNT));
> > - } else if (IS_GEN(dev_priv, 9, 11)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> > seq_printf(m, "DC3 -> DC5 count: %d\n",
> >I915_READ(SKL_CSR_DC3_DC5_COUNT));
> > seq_printf(m, "DC5 -> DC6 count: %d\n",
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 3017ef037fed..f766bb1e873b 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> > *
> > * Use GEN_FOREVER for unbound start and or end.
> > */
> > -#define IS_GEN(dev_priv, s, e) \
> > +#define IS_GEN_RANGE(dev_priv, s, e) \
> > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
> > b/drivers/gpu/drm/i915/i915_perf.c
> > index 664b96bb65a3..0888b6e6080f 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct
> > drm_i915_private *dev_priv,
> > * be read back from automatically triggered reports, as part of the
> > * RPT_ID field.
> > */
> > - if (IS_GEN(dev_priv, 9, 11)) {
> > + if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> > I915_WRITE(GEN8_OA_DEBUG,
> >
> > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
> > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
> > @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
> >
> > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
> > }
> > - } else if (IS_GEN(dev_priv, 10, 11)) {
> > + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
> > dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> > gen7_is_valid_b_counter_addr;
> > dev_priv->perf.oa.ops.is_valid_mux_reg =
> > diff --git a/drivers/gpu/drm/i915/intel_bios.c
> > b/drivers/gpu/drm/i915/intel_bios.c
> > index 1faa494e2bc9..43cf0b026143 100644
> > --- a/drivers/gpu/drm/i915/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/intel_bios.c
> > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private
> > *dev_priv, u8 bdb_version)
> > * Only parse SDVO mappings on gens that could have SDVO. This isn't
> > * accurate and doesn't have to be, as long as it's not too strict.
> > */
> > - if (!IS_GEN(dev_priv, 3, 7)) {
> > + if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
> > DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
> > return;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 8bfab22068a3..65f6c9bc10cf 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct
> > intel_engine_cs *engine,
> > >execlists;
> > u64 addr;
> >
> > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
> > + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
> > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
> > drm_printf(m, "\tRING_START: 0x%08x\n",
> >
Re: [Intel-gfx] [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
On Tue, 23 Oct 2018, Rodrigo Vivi wrote:
> RANGE makes it longer, but clear.
IS_GEN_RANGE() was the first proposal, but in review this was changed to
IS_GEN() following IS_REVID() and IS__REVID().
IMO unnecessary change.
BR,
Jani.
>
> Diff generated with:
>
> sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
>
> Cc: Tvrtko Ursulin
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_perf.c| 4 ++--
> drivers/gpu/drm/i915/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/intel_fbc.c| 2 +-
> drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8
> drivers/gpu/drm/i915/intel_uncore.c | 12 ++--
> 9 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5b37d5f8e132..3deab30388f2 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> if (IS_BROXTON(dev_priv)) {
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(BXT_CSR_DC3_DC5_COUNT));
> - } else if (IS_GEN(dev_priv, 9, 11)) {
> + } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> seq_printf(m, "DC3 -> DC5 count: %d\n",
> I915_READ(SKL_CSR_DC3_DC5_COUNT));
> seq_printf(m, "DC5 -> DC6 count: %d\n",
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3017ef037fed..f766bb1e873b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> *
> * Use GEN_FOREVER for unbound start and or end.
> */
> -#define IS_GEN(dev_priv, s, e) \
> +#define IS_GEN_RANGE(dev_priv, s, e) \
> (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e
>
> /*
> diff --git a/drivers/gpu/drm/i915/i915_perf.c
> b/drivers/gpu/drm/i915/i915_perf.c
> index 664b96bb65a3..0888b6e6080f 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct
> drm_i915_private *dev_priv,
>* be read back from automatically triggered reports, as part of the
>* RPT_ID field.
>*/
> - if (IS_GEN(dev_priv, 9, 11)) {
> + if (IS_GEN_RANGE(dev_priv, 9, 11)) {
> I915_WRITE(GEN8_OA_DEBUG,
>
> _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
> GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
> @@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>
> dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
> }
> - } else if (IS_GEN(dev_priv, 10, 11)) {
> + } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
> dev_priv->perf.oa.ops.is_valid_b_counter_reg =
> gen7_is_valid_b_counter_addr;
> dev_priv->perf.oa.ops.is_valid_mux_reg =
> diff --git a/drivers/gpu/drm/i915/intel_bios.c
> b/drivers/gpu/drm/i915/intel_bios.c
> index 1faa494e2bc9..43cf0b026143 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private
> *dev_priv, u8 bdb_version)
>* Only parse SDVO mappings on gens that could have SDVO. This isn't
>* accurate and doesn't have to be, as long as it's not too strict.
>*/
> - if (!IS_GEN(dev_priv, 3, 7)) {
> + if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
> DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 8bfab22068a3..65f6c9bc10cf 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct
> intel_engine_cs *engine,
> >execlists;
> u64 addr;
>
> - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
> + if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
> drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
> drm_printf(m, "\tRING_START: 0x%08x\n",
> I915_READ(RING_START(engine->mmio_base)));
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index e3cfc3c176e7..c90954cdfb15 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -784,7 +784,7 @@ static bool
[Intel-gfx] [RFC 1/3] drm/i915: Rename IS_GEN to IS_GEN_RANGE.
RANGE makes it longer, but clear.
Diff generated with:
sed 's/IS_GEN(/IS_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i
Cc: Tvrtko Ursulin
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_perf.c| 4 ++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_fbc.c| 2 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 8
drivers/gpu/drm/i915/intel_uncore.c | 12 ++--
9 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5b37d5f8e132..3deab30388f2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2919,7 +2919,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
if (IS_BROXTON(dev_priv)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(BXT_CSR_DC3_DC5_COUNT));
- } else if (IS_GEN(dev_priv, 9, 11)) {
+ } else if (IS_GEN_RANGE(dev_priv, 9, 11)) {
seq_printf(m, "DC3 -> DC5 count: %d\n",
I915_READ(SKL_CSR_DC3_DC5_COUNT));
seq_printf(m, "DC5 -> DC6 count: %d\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef037fed..f766bb1e873b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2387,7 +2387,7 @@ intel_info(const struct drm_i915_private *dev_priv)
*
* Use GEN_FOREVER for unbound start and or end.
*/
-#define IS_GEN(dev_priv, s, e) \
+#define IS_GEN_RANGE(dev_priv, s, e) \
(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e
/*
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 664b96bb65a3..0888b6e6080f 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1795,7 +1795,7 @@ static int gen8_enable_metric_set(struct drm_i915_private
*dev_priv,
* be read back from automatically triggered reports, as part of the
* RPT_ID field.
*/
- if (IS_GEN(dev_priv, 9, 11)) {
+ if (IS_GEN_RANGE(dev_priv, 9, 11)) {
I915_WRITE(GEN8_OA_DEBUG,
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -3439,7 +3439,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
}
- } else if (IS_GEN(dev_priv, 10, 11)) {
+ } else if (IS_GEN_RANGE(dev_priv, 10, 11)) {
dev_priv->perf.oa.ops.is_valid_b_counter_reg =
gen7_is_valid_b_counter_addr;
dev_priv->perf.oa.ops.is_valid_mux_reg =
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 1faa494e2bc9..43cf0b026143 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private
*dev_priv, u8 bdb_version)
* Only parse SDVO mappings on gens that could have SDVO. This isn't
* accurate and doesn't have to be, as long as it's not too strict.
*/
- if (!IS_GEN(dev_priv, 3, 7)) {
+ if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
return;
}
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 8bfab22068a3..65f6c9bc10cf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct
intel_engine_cs *engine,
>execlists;
u64 addr;
- if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
+ if (engine->id == RCS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
drm_printf(m, "\tRING_START: 0x%08x\n",
I915_READ(RING_START(engine->mmio_base)));
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index e3cfc3c176e7..c90954cdfb15 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
* having a Y offset that isn't divisible by 4 causes FIFO underrun
* and screen flicker.
*/
- if (IS_GEN(dev_priv, 9, 10) &&
+ if (IS_GEN_RANGE(dev_priv, 9, 10) &&
(fbc->state_cache.plane.adjusted_y & 3)) {
fbc->no_fbc_reason = "plane Y offset is
