Re: [Intel-gfx] [RFC PATCH 1/3] drm/i915: group vlv iosf sideband register accessors to a new file

2013-05-21 Thread Daniel Vetter 
On Wed, May 15, 2013 at 09:40:30PM +0300, Jani Nikula wrote:
 No functional changes.
 
 Signed-off-by: Jani Nikula jani.nik...@intel.com

I'd vote to move the sbi sideband stuff on the haswell pch to this place,
too. Maybe in a follow-up patch though.
-Daniel

 ---
  drivers/gpu/drm/i915/Makefile |1 +
  drivers/gpu/drm/i915/intel_display.c  |   37 --
  drivers/gpu/drm/i915/intel_pm.c   |   60 
  drivers/gpu/drm/i915/intel_sideband.c |  123 
 +
  4 files changed, 124 insertions(+), 97 deletions(-)
  create mode 100644 drivers/gpu/drm/i915/intel_sideband.c
 
 diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
 index 91f3ac6..40034ec 100644
 --- a/drivers/gpu/drm/i915/Makefile
 +++ b/drivers/gpu/drm/i915/Makefile
 @@ -36,6 +36,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
 intel_overlay.o \
 intel_sprite.o \
 intel_opregion.o \
 +   intel_sideband.o \
 dvo_ch7xxx.o \
 dvo_ch7017.o \
 dvo_ivch.o \
 diff --git a/drivers/gpu/drm/i915/intel_display.c 
 b/drivers/gpu/drm/i915/intel_display.c
 index 7358e4e..39af0e2 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -381,43 +381,6 @@ static const intel_limit_t intel_limits_vlv_dp = {
   .find_pll = intel_vlv_find_best_pll,
  };
  
 -u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 -{
 - WARN_ON(!mutex_is_locked(dev_priv-dpio_lock));
 -
 - if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100)) {
 - DRM_ERROR(DPIO idle wait timed out\n);
 - return 0;
 - }
 -
 - I915_WRITE(DPIO_REG, reg);
 - I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 -DPIO_BYTE);
 - if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100)) {
 - DRM_ERROR(DPIO read wait timed out\n);
 - return 0;
 - }
 -
 - return I915_READ(DPIO_DATA);
 -}
 -
 -void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 -{
 - WARN_ON(!mutex_is_locked(dev_priv-dpio_lock));
 -
 - if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100)) {
 - DRM_ERROR(DPIO idle wait timed out\n);
 - return;
 - }
 -
 - I915_WRITE(DPIO_DATA, val);
 - I915_WRITE(DPIO_REG, reg);
 - I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 -DPIO_BYTE);
 - if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100))
 - DRM_ERROR(DPIO write wait timed out\n);
 -}
 -
  static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
   int refclk)
  {
 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
 index 1a76572..a06118d 100644
 --- a/drivers/gpu/drm/i915/intel_pm.c
 +++ b/drivers/gpu/drm/i915/intel_pm.c
 @@ -4952,66 +4952,6 @@ int sandybridge_pcode_write(struct drm_i915_private 
 *dev_priv, u8 mbox, u32 val)
   return 0;
  }
  
 -static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 
 opcode,
 - u8 addr, u32 *val)
 -{
 - u32 cmd, devfn, be, bar;
 -
 - bar = 0;
 - be = 0xf;
 - devfn = PCI_DEVFN(2, 0);
 -
 - cmd = (devfn  IOSF_DEVFN_SHIFT) | (opcode  IOSF_OPCODE_SHIFT) |
 - (port  IOSF_PORT_SHIFT) | (be  IOSF_BYTE_ENABLES_SHIFT) |
 - (bar  IOSF_BAR_SHIFT);
 -
 - WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
 -
 - if (I915_READ(VLV_IOSF_DOORBELL_REQ)  IOSF_SB_BUSY) {
 - DRM_DEBUG_DRIVER(warning: pcode (%s) mailbox access failed\n,
 -  opcode == PUNIT_OPCODE_REG_READ ?
 -  read : write);
 - return -EAGAIN;
 - }
 -
 - I915_WRITE(VLV_IOSF_ADDR, addr);
 - if (opcode == PUNIT_OPCODE_REG_WRITE)
 - I915_WRITE(VLV_IOSF_DATA, *val);
 - I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
 -
 - if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ)  IOSF_SB_BUSY) == 0,
 -  5)) {
 - DRM_ERROR(timeout waiting for pcode %s (%d) to finish\n,
 -   opcode == PUNIT_OPCODE_REG_READ ? read : write,
 -   addr);
 - return -ETIMEDOUT;
 - }
 -
 - if (opcode == PUNIT_OPCODE_REG_READ)
 - *val = I915_READ(VLV_IOSF_DATA);
 - I915_WRITE(VLV_IOSF_DATA, 0);
 -
 - return 0;
 -}
 -
 -int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 
 *val)
 -{
 - return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
 - addr, val);
 -}
 -
 -int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 
 val)
 -{
 - return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
 - addr, val);
 -}
 -
 -int valleyview_nc_read(struct

[Intel-gfx] [RFC PATCH 1/3] drm/i915: group vlv iosf sideband register accessors to a new file

2013-05-15 Thread Jani Nikula 
No functional changes.

Signed-off-by: Jani Nikula jani.nik...@intel.com
---
 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/intel_display.c  |   37 --
 drivers/gpu/drm/i915/intel_pm.c   |   60 
 drivers/gpu/drm/i915/intel_sideband.c |  123 +
 4 files changed, 124 insertions(+), 97 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_sideband.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 91f3ac6..40034ec 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -36,6 +36,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \
  intel_overlay.o \
  intel_sprite.o \
  intel_opregion.o \
+ intel_sideband.o \
  dvo_ch7xxx.o \
  dvo_ch7017.o \
  dvo_ivch.o \
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 7358e4e..39af0e2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -381,43 +381,6 @@ static const intel_limit_t intel_limits_vlv_dp = {
.find_pll = intel_vlv_find_best_pll,
 };
 
-u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
-{
-   WARN_ON(!mutex_is_locked(dev_priv-dpio_lock));
-
-   if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100)) {
-   DRM_ERROR(DPIO idle wait timed out\n);
-   return 0;
-   }
-
-   I915_WRITE(DPIO_REG, reg);
-   I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
-  DPIO_BYTE);
-   if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100)) {
-   DRM_ERROR(DPIO read wait timed out\n);
-   return 0;
-   }
-
-   return I915_READ(DPIO_DATA);
-}
-
-void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
-{
-   WARN_ON(!mutex_is_locked(dev_priv-dpio_lock));
-
-   if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100)) {
-   DRM_ERROR(DPIO idle wait timed out\n);
-   return;
-   }
-
-   I915_WRITE(DPIO_DATA, val);
-   I915_WRITE(DPIO_REG, reg);
-   I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
-  DPIO_BYTE);
-   if (wait_for_atomic_us((I915_READ(DPIO_PKT)  DPIO_BUSY) == 0, 100))
-   DRM_ERROR(DPIO write wait timed out\n);
-}
-
 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
int refclk)
 {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a76572..a06118d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4952,66 +4952,6 @@ int sandybridge_pcode_write(struct drm_i915_private 
*dev_priv, u8 mbox, u32 val)
return 0;
 }
 
-static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
-   u8 addr, u32 *val)
-{
-   u32 cmd, devfn, be, bar;
-
-   bar = 0;
-   be = 0xf;
-   devfn = PCI_DEVFN(2, 0);
-
-   cmd = (devfn  IOSF_DEVFN_SHIFT) | (opcode  IOSF_OPCODE_SHIFT) |
-   (port  IOSF_PORT_SHIFT) | (be  IOSF_BYTE_ENABLES_SHIFT) |
-   (bar  IOSF_BAR_SHIFT);
-
-   WARN_ON(!mutex_is_locked(dev_priv-rps.hw_lock));
-
-   if (I915_READ(VLV_IOSF_DOORBELL_REQ)  IOSF_SB_BUSY) {
-   DRM_DEBUG_DRIVER(warning: pcode (%s) mailbox access failed\n,
-opcode == PUNIT_OPCODE_REG_READ ?
-read : write);
-   return -EAGAIN;
-   }
-
-   I915_WRITE(VLV_IOSF_ADDR, addr);
-   if (opcode == PUNIT_OPCODE_REG_WRITE)
-   I915_WRITE(VLV_IOSF_DATA, *val);
-   I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
-
-   if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ)  IOSF_SB_BUSY) == 0,
-5)) {
-   DRM_ERROR(timeout waiting for pcode %s (%d) to finish\n,
- opcode == PUNIT_OPCODE_REG_READ ? read : write,
- addr);
-   return -ETIMEDOUT;
-   }
-
-   if (opcode == PUNIT_OPCODE_REG_READ)
-   *val = I915_READ(VLV_IOSF_DATA);
-   I915_WRITE(VLV_IOSF_DATA, 0);
-
-   return 0;
-}
-
-int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
-{
-   return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
-   addr, val);
-}
-
-int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
-{
-   return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
-   addr, val);
-}
-
-int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
-{
-   return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
-   addr, val);
-}
-
 int vlv_gpu_freq(int ddr_freq,