Re: [Intel-gfx] [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines
> -Original Message-
> From: Bhadane, Dnyaneshwar
> Sent: Friday, June 30, 2023 4:40 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ursulin, Tvrtko ; jani.nik...@linux.intel.com;
> Srivatsa, Anusha ; Bhadane, Dnyaneshwar
>
> Subject: [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform
> defines
>
> Follow consistent naming convention. Replace MTL with METEORLAKE. Added
> defines that are replacing IS_MTL_GRAPHICS_STEP with
> IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
The patch also changes MTL_MEDIA macros. That should be mentioned in the commit
message.
> v2:
> - Replace IS_MLT_GRAPHICS_STEP with
Typo ^ s/MLT/MTL
> IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
> - Changed subject prefix mtl with MTL (Anusha)
Rewording:"mtl instead of MTL" or "use lower case instead of upper case"
Anusha
>
> Cc: Tvrtko Ursulin
> Cc: Jani Nikula
> Cc: Anusha Srivatsa
>
> Signed-off-by: Dnyaneshwar Bhadane
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 ++---
> .../drm/i915/display/skl_universal_plane.c| 4 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 4 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 +--
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 15 +--
> drivers/gpu/drm/i915/i915_perf.c | 4 +-
> 15 files changed, 60 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7f8b2d7713c7..6358a8b26172 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>
> /* Wa_14016291713 */
> if ((IS_DISPLAY_VER(i915, 12, 13) ||
> - IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> + IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
> crtc_state->has_psr) {
> plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index f7608d363634..8c3158b188ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
>&pmdemand_state->base,
>&intel_pmdemand_funcs);
>
> - if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> + if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> /* Wa_14016740474 */
> intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> DMD_RSP_TIMEOUT_DISABLE);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 62151abe4748..ecd4e36119b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp
> *intel_dp,
> bool set_wa_bit = false;
>
> /* Wa_14015648006 */
> - if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> + if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> IS_DISPLAY_VER(dev_priv, 11, 13))
> set_wa_bit |= crtc_state->wm_level_disabled;
>
> @@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>* All supported adlp panels have 1-based X granularity, this
> may
>* cause issues if non-supported panels are used.
>*/
> - if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
> intel_de_rmw(dev_priv,
> MTL_CHICKEN_TRANS(cpu_transcoder), 0,
>ADLP_1_BASED_X_GRANULARITY);
> else if (IS_ALDERLAKE_P(dev_priv))
> @@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>ADLP_1_BASED_X_GRANULARITY);
>
> /* Wa_16012604467:adlp,mtl[a0,b0] */
> - if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> + if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0,
> STEP_B0))
> intel_de_rmw(dev_priv,
>MTL_CL
[Intel-gfx] [v2] drm/i915/mtl: s/MTL/METEORLAKE for platform/subplatform defines
Follow consistent naming convention. Replace MTL with
METEORLAKE. Added defines that are replacing IS_MTL_GRAPHICS_STEP with
IS_METEORLAKE_P_GRAPHICS_STEP and IS_METEORLAKE_M_GRAPHICS_STEP.
v2:
- Replace IS_MLT_GRAPHICS_STEP with IS_METEROLAKE_(P/M)_GRAPHICS_STEP (Tvrtko).
- Changed subject prefix mtl with MTL (Anusha)
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Anusha Srivatsa
Signed-off-by: Dnyaneshwar Bhadane
---
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 ++---
.../drm/i915/display/skl_universal_plane.c| 4 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++--
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 +--
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 15 +--
drivers/gpu/drm/i915/i915_perf.c | 4 +-
15 files changed, 60 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..6358a8b26172 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1093,7 +1093,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..8c3158b188ef 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
&pmdemand_state->base,
&intel_pmdemand_funcs);
- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ if (IS_METEORLAKE_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 62151abe4748..ecd4e36119b2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1247,7 +1247,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1320,7 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
* All supported adlp panels have 1-based X granularity, this
may
* cause issues if non-supported panels are used.
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CHICKEN_TRANS(cpu_transcoder), 0,
ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1328,7 +1328,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1489,7 +1489,7 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
if (intel_dp->psr.psr2_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_METEORLAKE_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
