Re: [Intel-gfx] [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support

2019-01-29 Thread Shankar, Uma 


>-Original Message-
>From: Roper, Matthew D
>Sent: Tuesday, January 29, 2019 3:49 AM
>To: Shankar, Uma 
>Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
>; Syrjala, Ville ; 
>Sharma,
>Shashank 
>Subject: Re: [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support
>
>On Wed, Jan 16, 2019 at 09:51:34PM +0530, Uma Shankar wrote:
>> Add support for icl pipe degamma and gamma.
>>
>> v2: Removed a POSTING_READ and corrected the Bit Definition as per
>> Maarten's comments.
>>
>> v3: Addressed Matt's review comments. Removed rmw patterns as
>> suggested by Matt.
>>
>> v4: Fixed Matt's review comments.
>>
>> v5: Corrected macro alignment as per Jani Nikula's comments.
>> Addressed Ville and Matt's  review comments.
>>
>> v6: Merged ICL degamma handling with GLK and dropped ICL degamma
>> function as per Ville and Matt's comments.
>>
>> Signed-off-by: Uma Shankar 
>
>The general changes and direction here look good, but this will need a rebase
>after Ville's series lands, so I'll wait on that to give the final r-b.

Ok, sure. Thanks Matt.

Regards,
Uma Shankar

>
>Matt
>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h| 12 +++-
>>  drivers/gpu/drm/i915/intel_color.c | 21 +
>>  2 files changed, 28 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index fad5a9e..a84200f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7088,11 +7088,13 @@ enum {
>>  #define _GAMMA_MODE_A   0x4a480
>>  #define _GAMMA_MODE_B   0x4ac80
>>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A,
>_GAMMA_MODE_B)
>> -#define GAMMA_MODE_MODE_MASK(3 << 0)
>> -#define GAMMA_MODE_MODE_8BIT(0 << 0)
>> -#define GAMMA_MODE_MODE_10BIT   (1 << 0)
>> -#define GAMMA_MODE_MODE_12BIT   (2 << 0)
>> -#define GAMMA_MODE_MODE_SPLIT   (3 << 0)
>> +#define  PRE_CSC_GAMMA_ENABLE   (1 << 31)
>> +#define  POST_CSC_GAMMA_ENABLE  (1 << 30)
>> +#define  GAMMA_MODE_MODE_MASK   (3 << 0)
>> +#define  GAMMA_MODE_MODE_8BIT   (0 << 0)
>> +#define  GAMMA_MODE_MODE_10BIT  (1 << 0)
>> +#define  GAMMA_MODE_MODE_12BIT  (2 << 0)
>> +#define  GAMMA_MODE_MODE_SPLIT  (3 << 0)
>>
>>  /* DMC/CSR */
>>  #define CSR_PROGRAM(i)  _MMIO(0x8 + (i) * 4)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 3712bd0..494891c 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -557,6 +557,25 @@ static void glk_load_luts(struct intel_crtc_state
>*crtc_state)
>>  POSTING_READ(GAMMA_MODE(pipe));
>>  }
>>
>> +static void icl_load_luts(struct intel_crtc_state *crtc_state) {
>> +struct drm_crtc *crtc = crtc_state->base.crtc;
>> +struct drm_device *dev = crtc_state->base.crtc->dev;
>> +struct drm_i915_private *dev_priv = to_i915(dev);
>> +enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +
>> +if (crtc_state_is_legacy_gamma(crtc_state)) {
>> +haswell_load_luts(crtc_state);
>> +return;
>> +}
>> +
>> +glk_load_degamma_lut(crtc_state);
>> +bdw_load_gamma_lut(crtc_state, 0);
>> +
>> +I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT |
>> +   PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE); }
>> +
>>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
>> static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>> { @@ -672,6 +691,8 @@ void intel_color_init(struct intel_crtc *crtc)
>>  } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>>  dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>>  dev_priv->display.load_luts = glk_load_luts;
>> +} else if (IS_ICELAKE(dev_priv)) {
>> +dev_priv->display.load_luts = icl_load_luts;
>>  } else {
>>  dev_priv->display.load_luts = i9xx_load_luts;
>>  }
>> --
>> 1.9.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>IoTG Platform Enabling & Development
>Intel Corporation
>(916) 356-2795
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Re: [Intel-gfx] [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support

2019-01-28 Thread Matt Roper 
On Wed, Jan 16, 2019 at 09:51:34PM +0530, Uma Shankar wrote:
> Add support for icl pipe degamma and gamma.
> 
> v2: Removed a POSTING_READ and corrected the Bit
> Definition as per Maarten's comments.
> 
> v3: Addressed Matt's review comments. Removed rmw patterns
> as suggested by Matt.
> 
> v4: Fixed Matt's review comments.
> 
> v5: Corrected macro alignment as per Jani Nikula's comments.
> Addressed Ville and Matt's  review comments.
> 
> v6: Merged ICL degamma handling with GLK and dropped ICL
> degamma function as per Ville and Matt's comments.
> 
> Signed-off-by: Uma Shankar 

The general changes and direction here look good, but this will need a
rebase after Ville's series lands, so I'll wait on that to give the
final r-b.


Matt

> ---
>  drivers/gpu/drm/i915/i915_reg.h| 12 +++-
>  drivers/gpu/drm/i915/intel_color.c | 21 +
>  2 files changed, 28 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fad5a9e..a84200f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7088,11 +7088,13 @@ enum {
>  #define _GAMMA_MODE_A0x4a480
>  #define _GAMMA_MODE_B0x4ac80
>  #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
> -#define GAMMA_MODE_MODE_MASK (3 << 0)
> -#define GAMMA_MODE_MODE_8BIT (0 << 0)
> -#define GAMMA_MODE_MODE_10BIT(1 << 0)
> -#define GAMMA_MODE_MODE_12BIT(2 << 0)
> -#define GAMMA_MODE_MODE_SPLIT(3 << 0)
> +#define  PRE_CSC_GAMMA_ENABLE(1 << 31)
> +#define  POST_CSC_GAMMA_ENABLE   (1 << 30)
> +#define  GAMMA_MODE_MODE_MASK(3 << 0)
> +#define  GAMMA_MODE_MODE_8BIT(0 << 0)
> +#define  GAMMA_MODE_MODE_10BIT   (1 << 0)
> +#define  GAMMA_MODE_MODE_12BIT   (2 << 0)
> +#define  GAMMA_MODE_MODE_SPLIT   (3 << 0)
>  
>  /* DMC/CSR */
>  #define CSR_PROGRAM(i)   _MMIO(0x8 + (i) * 4)
> diff --git a/drivers/gpu/drm/i915/intel_color.c 
> b/drivers/gpu/drm/i915/intel_color.c
> index 3712bd0..494891c 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -557,6 +557,25 @@ static void glk_load_luts(struct intel_crtc_state 
> *crtc_state)
>   POSTING_READ(GAMMA_MODE(pipe));
>  }
>  
> +static void icl_load_luts(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_crtc *crtc = crtc_state->base.crtc;
> + struct drm_device *dev = crtc_state->base.crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +
> + if (crtc_state_is_legacy_gamma(crtc_state)) {
> + haswell_load_luts(crtc_state);
> + return;
> + }
> +
> + glk_load_degamma_lut(crtc_state);
> + bdw_load_gamma_lut(crtc_state, 0);
> +
> + I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT |
> +PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE);
> +}
> +
>  /* Loads the palette/gamma unit for the CRTC on CherryView. */
>  static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
>  {
> @@ -672,6 +691,8 @@ void intel_color_init(struct intel_crtc *crtc)
>   } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>   dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>   dev_priv->display.load_luts = glk_load_luts;
> + } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.load_luts = icl_load_luts;
>   } else {
>   dev_priv->display.load_luts = i9xx_load_luts;
>   }
> -- 
> 1.9.1
> 

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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[Intel-gfx] [v6 3/6] drm/i915/icl: Add icl pipe degamma and gamma support

2019-01-16 Thread Uma Shankar 
Add support for icl pipe degamma and gamma.

v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.

v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.

v4: Fixed Matt's review comments.

v5: Corrected macro alignment as per Jani Nikula's comments.
Addressed Ville and Matt's  review comments.

v6: Merged ICL degamma handling with GLK and dropped ICL
degamma function as per Ville and Matt's comments.

Signed-off-by: Uma Shankar 
---
 drivers/gpu/drm/i915/i915_reg.h| 12 +++-
 drivers/gpu/drm/i915/intel_color.c | 21 +
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fad5a9e..a84200f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7088,11 +7088,13 @@ enum {
 #define _GAMMA_MODE_A  0x4a480
 #define _GAMMA_MODE_B  0x4ac80
 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
-#define GAMMA_MODE_MODE_MASK   (3 << 0)
-#define GAMMA_MODE_MODE_8BIT   (0 << 0)
-#define GAMMA_MODE_MODE_10BIT  (1 << 0)
-#define GAMMA_MODE_MODE_12BIT  (2 << 0)
-#define GAMMA_MODE_MODE_SPLIT  (3 << 0)
+#define  PRE_CSC_GAMMA_ENABLE  (1 << 31)
+#define  POST_CSC_GAMMA_ENABLE (1 << 30)
+#define  GAMMA_MODE_MODE_MASK  (3 << 0)
+#define  GAMMA_MODE_MODE_8BIT  (0 << 0)
+#define  GAMMA_MODE_MODE_10BIT (1 << 0)
+#define  GAMMA_MODE_MODE_12BIT (2 << 0)
+#define  GAMMA_MODE_MODE_SPLIT (3 << 0)
 
 /* DMC/CSR */
 #define CSR_PROGRAM(i) _MMIO(0x8 + (i) * 4)
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 3712bd0..494891c 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -557,6 +557,25 @@ static void glk_load_luts(struct intel_crtc_state 
*crtc_state)
POSTING_READ(GAMMA_MODE(pipe));
 }
 
+static void icl_load_luts(struct intel_crtc_state *crtc_state)
+{
+   struct drm_crtc *crtc = crtc_state->base.crtc;
+   struct drm_device *dev = crtc_state->base.crtc->dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
+   enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+   if (crtc_state_is_legacy_gamma(crtc_state)) {
+   haswell_load_luts(crtc_state);
+   return;
+   }
+
+   glk_load_degamma_lut(crtc_state);
+   bdw_load_gamma_lut(crtc_state, 0);
+
+   I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT |
+  PRE_CSC_GAMMA_ENABLE | POST_CSC_GAMMA_ENABLE);
+}
+
 /* Loads the palette/gamma unit for the CRTC on CherryView. */
 static void cherryview_load_luts(struct intel_crtc_state *crtc_state)
 {
@@ -672,6 +691,8 @@ void intel_color_init(struct intel_crtc *crtc)
} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
dev_priv->display.load_luts = glk_load_luts;
+   } else if (IS_ICELAKE(dev_priv)) {
+   dev_priv->display.load_luts = icl_load_luts;
} else {
dev_priv->display.load_luts = i9xx_load_luts;
}
-- 
1.9.1

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