== Series Details ==
Series: Clear Color Support for TGL Render Decompression (rev9)
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
10f566048768 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
7d2dee12e37d drm/i915: Use intel_tile_height() instead of re-implementing
12645a88b91a drm/i915: Move CCS stride alignment W/A inside
intel_fb_stride_alignment
32c32c8b500b drm/i915/tgl: Gen-12 render decompression
ba040ad811f0 drm/i915: Extract framebufer CCS offset checks into a function
39c6f2f2c9f9 drm/framebuffer: Format modifier for Intel Gen-12 media compression
124bad1a7799 drm/fb: Extend format_info member arrays to handle four planes
c36e200e5975 Gen-12 display can decompress surfaces compressed by the media
engine.
-:13: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#13:
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
-:113: WARNING:LONG_LINE: line over 100 characters
#113: FILE: drivers/gpu/drm/i915/display/intel_display.c:2726:
+intel_fb_plane_get_subsampling(int *hsub, int *vsub, const struct
drm_framebuffer *fb, int color_plane)
-:120: WARNING:LONG_LINE: line over 100 characters
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:2733:
+ } mc_ccs_subsampling = {.cpp = {1, 1, 2, 1}, .hsub = {1, 8, 2,
16}, .vsub = {1, 32, 2, 32} };
total: 0 errors, 3 warnings, 0 checks, 509 lines checked
2858e81f6a9e drm/framebuffer/tgl: Format modifier for Intel Gen 12 render
compression with Clear Color
e9980fa6b761 drm/i915/tgl: Add Clear Color support for TGL Render Decompression
-:253: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible
side-effects?
#253: FILE: drivers/gpu/drm/i915/i915_reg.h:6801:
+#define PLANE_CC_VAL(pipe, plane) \
+ _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
total: 0 errors, 0 warnings, 1 checks, 198 lines checked
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