Re: [Intel-gfx] Workaround for flicker with panning on the i830 - found a way for tiled displays

2013-11-15 Thread Thomas Richter

Hi Daniel,

Gosh, should have read the code more closely. We have a totally botched wm
setup on i830M - the watermark code for the 2nd pipe is just not there!


Well, nice try, but no cigar. (-: That's actually much worse than 
before. The display is now unstable on *both* the internal
and external display, and inspecting the FW_BLC register, it is 
completely off. The current code leaves it at 0x1050101, but
it should be at least 0x1060106, that is, the watermark needs to be 
higher, not lower. I still don't understand why a higher
latency causes a lower watermark, but maybe things work different than 
in my mental model.


Greetings,
Thomas

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Re: [Intel-gfx] Workaround for flicker with panning on the i830 - found a way for tiled displays

2013-11-15 Thread Thomas Richter

Am 15.11.2013 16:41, schrieb Daniel Vetter:


Gosh, should have read the code more closely. We have a totally botched wm
setup on i830M - the watermark code for the 2nd pipe is just not there!


(-: Guess that explains something. Just disregard my earlier patch, 
simply superfluous.
In the meantime, I recompiled the code and *decreased* the latency from 
5000 to 3000, then getting a stable image,
even the boot console is then stable (has never been before). Its still 
off by half a screen, but no longer flickering

left and right.

However, what I do not understand about the watermark computation is 
that a *lower* latency results in a *higher* number

of entries in the FIFO. Shouldn't this quite the reverse?
In specific, I do not understand the subtraction in intel_calculate_wm, 
line 1058.


Anyhow, I let you proceed with the patch and I'm ready and happy to test it.

Greetings,
Thomas



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Re: [Intel-gfx] Workaround for flicker with panning on the i830 - found a way for tiled displays

2013-11-15 Thread Daniel Vetter
On Fri, Nov 15, 2013 at 02:16:11PM +0100, Thomas Richter wrote:
> Hi Daniel, hi others,
> 
> did even more experiments. I guess I understand now better. Indeed,
> the trouble seems to be the watermark levels. I played more
> with all that, and the real culprit seems to be the FW_BLC register
> controlling the watermarks.
> 
> On the i830 with the current settings, it is defined to be 0x1080304
> which sets the watermark a bit too low. If I set it to
> 0x1080306 instead, I get a stable display in all panning positions
> (hurray!).
> 
> I would like to fix this, but I guess I would need to understand the
> logic a little bit better. At the time being, you probably better
> put the linear frame buffer workaround on hold, it looks I really
> got something here.

Gosh, should have read the code more closely. We have a totally botched wm
setup on i830M - the watermark code for the 2nd pipe is just not there!

I'll try to wip up a patch to fix this.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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[Intel-gfx] Workaround for flicker with panning on the i830 - found a way for tiled displays

2013-11-15 Thread Thomas Richter

Hi Daniel, hi others,

did even more experiments. I guess I understand now better. Indeed, the 
trouble seems to be the watermark levels. I played more
with all that, and the real culprit seems to be the FW_BLC register 
controlling the watermarks.


On the i830 with the current settings, it is defined to be 0x1080304 
which sets the watermark a bit too low. If I set it to
0x1080306 instead, I get a stable display in all panning positions 
(hurray!).


I would like to fix this, but I guess I would need to understand the 
logic a little bit better. At the time being, you probably better
put the linear frame buffer workaround on hold, it looks I really got 
something here.


Greetings,
Thomas

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