Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
On Tue, Mar 12, 2024 at 03:58:19PM -0700, Matt Roper wrote:
On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.
The registers not used anymore are also removed.
Signed-off-by: Lucas De Marchi
---
Potential problem here that needs a deeper look, the changes in
__gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
I removed them, but it needs to be double checked with spec and CI
results.
...
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 76400e9c40f0..4f1e56187442 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range
__gen12_fw_ranges[] = {
GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*
\
0x13200 - 0x133ff: VD2 (DG2 only)
\
0x13400 - 0x13fff: reserved */
\
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only
*/ \
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only
*/ \
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only
*/ \
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only
*/ \
We can't just remove ranges in the middle of the table since that breaks
the "watertight" table requirement that our selftests check for. We
need to either roll the now-unused ranges into an adjacent range, or add
a new "reserved" range.
see 23n224gu57lfd4wbroqflav4pih6usrkf53q2ve4ntekhueylb@eqigxyktri6b
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),
\
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
\
0x15000 - 0x15fff: gt (DG2 only)
\
0x16000 - 0x16dff: reserved */
\
GEN_FW_RANGE(0x16e00, 0x1, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
\
- 0x2 - 0x20fff: VD0 (XEHPSDV only)
\
+ GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
\
0x21000 - 0x21fff: reserved */
\
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
\
GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
\
@@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range
__gen12_fw_ranges[] = {
0x1f6e00 - 0x1f7fff: reserved */
\
GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
-static const struct intel_forcewake_range __xehp_fw_ranges[] = {
- XEHP_FWRANGES(FORCEWAKE_GT)
-};
-
static const struct intel_forcewake_range __dg2_fw_ranges[] = {
XEHP_FWRANGES(FORCEWAKE_RENDER)
We can drop the macro here now and just make this a normal table like
everything else.
will add that in v2 too, thanks
Lucas De Marchi
Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
> PCI IDs for XEHPSDV were never added and platform always marked with
> force_probe. Drop what's not used and rename some places to either be
> xehp or dg2, depending on the platform/IP checks.
>
> The registers not used anymore are also removed.
>
> Signed-off-by: Lucas De Marchi
> ---
>
> Potential problem here that needs a deeper look, the changes in
> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
> I removed them, but it needs to be double checked with spec and CI
> results.
>
...
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 76400e9c40f0..4f1e56187442 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1536,17 +1536,12 @@ static const struct intel_forcewake_range
> __gen12_fw_ranges[] = {
> GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*
> \
> 0x13200 - 0x133ff: VD2 (DG2 only)
> \
> 0x13400 - 0x13fff: reserved */
> \
> - GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only
> */ \
> - GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only
> */ \
> - GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only
> */ \
> - GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only
> */ \
We can't just remove ranges in the middle of the table since that breaks
the "watertight" table requirement that our selftests check for. We
need to either roll the now-unused ranges into an adjacent range, or add
a new "reserved" range.
> GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),
> \
> GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
> \
> 0x15000 - 0x15fff: gt (DG2 only)
> \
> 0x16000 - 0x16dff: reserved */
> \
> GEN_FW_RANGE(0x16e00, 0x1, FORCEWAKE_RENDER),
> \
> - GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
> \
> - 0x2 - 0x20fff: VD0 (XEHPSDV only)
> \
> + GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
> \
> 0x21000 - 0x21fff: reserved */
> \
> GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
> \
> GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
> \
> @@ -1627,10 +1622,6 @@ static const struct intel_forcewake_range
> __gen12_fw_ranges[] = {
> 0x1f6e00 - 0x1f7fff: reserved */
> \
> GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3),
>
> -static const struct intel_forcewake_range __xehp_fw_ranges[] = {
> - XEHP_FWRANGES(FORCEWAKE_GT)
> -};
> -
> static const struct intel_forcewake_range __dg2_fw_ranges[] = {
> XEHP_FWRANGES(FORCEWAKE_RENDER)
We can drop the macro here now and just make this a normal table like
everything else.
Matt
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
On Mon, Mar 11, 2024 at 11:16:06AM -0400, Rodrigo Vivi wrote:
On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.
The registers not used anymore are also removed.
Signed-off-by: Lucas De Marchi
---
Potential problem here that needs a deeper look, the changes in
__gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
I removed them, but it needs to be double checked with spec and CI
results.
I have checked the specs and your patch looks right because those
bits should be reserved for DG2.
But the main issue I see is that we were using that (wrongly?) for
DG2 so far. So it probably deserves a separate patch anyway.
With this patch only removing the comments and a separate patch
to remove that for DG2 (and standalone CI run on that patch by itself):
After double checking I think the main issue is that the changed table
became wrong since it poke holes. From the docs:
* All platforms' forcewake tables below must be sorted by offset ranges.
* Furthermore, new forcewake tables added should be "watertight" and hav
* no gaps between ranges.
I *think* this would be the more correct change:
@@ -1533,21 +1533,16 @@ static const struct intel_forcewake_range
__gen12_fw_ranges[] = {
0x12000 - 0x127ff: always on
\
0x12800 - 0x12fff: reserved */
\
GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */
\
- GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /*
\
+ GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /*
\
0x13200 - 0x133ff: VD2 (DG2 only)
\
- 0x13400 - 0x13fff: reserved */
\
- GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only
*/ \
- GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only
*/ \
- GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only
*/ \
- GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only
*/ \
+ 0x13400 - 0x147ff: reserved */
\
GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER),
\
GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /*
\
0x15000 - 0x15fff: gt (DG2 only)
\
0x16000 - 0x16dff: reserved */
\
- GEN_FW_RANGE(0x16e00, 0x1, FORCEWAKE_RENDER),
\
- GEN_FW_RANGE(0x2, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /*
\
- 0x2 - 0x20fff: VD0 (XEHPSDV only)
\
- 0x21000 - 0x21fff: reserved */
\
+ GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /*
\
+ 0x16e00 - 0x1: render
\
+ 0x2 - 0x21fff: reserved */
\
GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT),
\
GEN_FW_RANGE(0x24000, 0x2417f, 0), /*
\
0x24000 - 0x2407f: always on
\
did you find any access on DG2 within the reserved ranges?
Lucas De Marchi
Reviewed-by: Rodrigo Vivi
Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 20 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 --
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 43 -
drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 31 --
drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 ---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_hwmon.c | 6 --
drivers/gpu/drm/i915/i915_pci.c | 17
drivers/gpu/drm/i915/i915_perf.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 10 --
drivers/gpu/drm/i915/intel_uncore.c | 15 +--
Re: [PATCH 2/5] drm/i915: Drop dead code for xehpsdv
On Wed, Mar 06, 2024 at 11:36:40AM -0800, Lucas De Marchi wrote:
> PCI IDs for XEHPSDV were never added and platform always marked with
> force_probe. Drop what's not used and rename some places to either be
> xehp or dg2, depending on the platform/IP checks.
>
> The registers not used anymore are also removed.
>
> Signed-off-by: Lucas De Marchi
> ---
>
> Potential problem here that needs a deeper look, the changes in
> __gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
> I removed them, but it needs to be double checked with spec and CI
> results.
I have checked the specs and your patch looks right because those
bits should be reserved for DG2.
But the main issue I see is that we were using that (wrongly?) for
DG2 so far. So it probably deserves a separate patch anyway.
With this patch only removing the comments and a separate patch
to remove that for DG2 (and standalone CI run on that patch by itself):
Reviewed-by: Rodrigo Vivi
>
> Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40
> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 20 +---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 --
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
> drivers/gpu/drm/i915/gt/intel_lrc.c | 43 -
> drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
> drivers/gpu/drm/i915/gt/intel_mocs.c | 31 --
> drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 ---
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 -
> drivers/gpu/drm/i915/i915_hwmon.c | 6 --
> drivers/gpu/drm/i915/i915_pci.c | 17
> drivers/gpu/drm/i915/i915_perf.c | 11 +--
> drivers/gpu/drm/i915/i915_reg.h | 3 +-
> drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
> drivers/gpu/drm/i915/intel_device_info.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> drivers/gpu/drm/i915/intel_step.c | 10 --
> drivers/gpu/drm/i915/intel_uncore.c | 15 +--
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -
> 24 files changed, 51 insertions(+), 380 deletions(-)
>
> diff --git a/Documentation/gpu/rfc/i915_vm_bind.h
> b/Documentation/gpu/rfc/i915_vm_bind.h
> index 8a8fcd4fceac..bc26dc126104 100644
> --- a/Documentation/gpu/rfc/i915_vm_bind.h
> +++ b/Documentation/gpu/rfc/i915_vm_bind.h
> @@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
> * Multiple VA mappings can be created to the same section of the object
> * (aliasing).
> *
> - * The @start, @offset and @length must be 4K page aligned. However the DG2
> - * and XEHPSDV has 64K page size for device local memory and has compact page
> - * table. On those platforms, for binding device local-memory objects, the
> - * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
> - * the local memory 64K page and the system memory 4K page bindings in the
> same
> - * 2M range.
> + * The @start, @offset and @length must be 4K page aligned. However the DG2
> has
> + * 64K page size for device local memory and has compact page table. On that
> + * platform, for binding device local-memory objects, the @start, @offset and
> + * @length must be 64K aligned. Also, UMDs should not mix the local memory
> 64K
> + * page and the system memory 4K page bindings in the same 2M range.
> *
> * Error code -EINVAL will be returned if @start, @offset and @length are not
> * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error
> code
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index fa46d2308b0e..1bd0e041e15c 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
> }
>
> static void
> -xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
> - struct i915_vma_resource *vma_res,
> - struct sgt_dma *iter,
> - unsigned int pat_index,
> - u32 flags)
> +xehp_ppgtt_insert_huge(struct i915_address_space *vm,
> +struct i915_vma_resource *vma_res,
> +struct sgt_dma *iter,
> +unsigned int pat_index,
> +u32 flags)
> {
> const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
> unsigned int rem = sg_dma_len(iter->sg);
> @@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space
> *vm,
> struct sgt_dma iter = sgt_dma(vma_res);
>
> if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
> -
[PATCH 2/5] drm/i915: Drop dead code for xehpsdv
PCI IDs for XEHPSDV were never added and platform always marked with
force_probe. Drop what's not used and rename some places to either be
xehp or dg2, depending on the platform/IP checks.
The registers not used anymore are also removed.
Signed-off-by: Lucas De Marchi
---
Potential problem here that needs a deeper look, the changes in
__gen12_fw_ranges. Some ranges had comments saying they were XEHPSDV so
I removed them, but it needs to be double checked with spec and CI
results.
Documentation/gpu/rfc/i915_vm_bind.h | 11 +--
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 40
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 ---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 20 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 50 --
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 21 ++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 43 -
drivers/gpu/drm/i915/gt/intel_migrate.c | 18 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 31 --
drivers/gpu/drm/i915/gt/intel_rps.c | 2 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 95 ---
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_hwmon.c | 6 --
drivers/gpu/drm/i915/i915_pci.c | 17
drivers/gpu/drm/i915/i915_perf.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/intel_clock_gating.c | 10 --
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 10 --
drivers/gpu/drm/i915/intel_uncore.c | 15 +--
drivers/gpu/drm/i915/selftests/intel_uncore.c | 1 -
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -
24 files changed, 51 insertions(+), 380 deletions(-)
diff --git a/Documentation/gpu/rfc/i915_vm_bind.h
b/Documentation/gpu/rfc/i915_vm_bind.h
index 8a8fcd4fceac..bc26dc126104 100644
--- a/Documentation/gpu/rfc/i915_vm_bind.h
+++ b/Documentation/gpu/rfc/i915_vm_bind.h
@@ -93,12 +93,11 @@ struct drm_i915_gem_timeline_fence {
* Multiple VA mappings can be created to the same section of the object
* (aliasing).
*
- * The @start, @offset and @length must be 4K page aligned. However the DG2
- * and XEHPSDV has 64K page size for device local memory and has compact page
- * table. On those platforms, for binding device local-memory objects, the
- * @start, @offset and @length must be 64K aligned. Also, UMDs should not mix
- * the local memory 64K page and the system memory 4K page bindings in the same
- * 2M range.
+ * The @start, @offset and @length must be 4K page aligned. However the DG2 has
+ * 64K page size for device local memory and has compact page table. On that
+ * platform, for binding device local-memory objects, the @start, @offset and
+ * @length must be 64K aligned. Also, UMDs should not mix the local memory 64K
+ * page and the system memory 4K page bindings in the same 2M range.
*
* Error code -EINVAL will be returned if @start, @offset and @length are not
* properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index fa46d2308b0e..1bd0e041e15c 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -500,11 +500,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
}
static void
-xehpsdv_ppgtt_insert_huge(struct i915_address_space *vm,
- struct i915_vma_resource *vma_res,
- struct sgt_dma *iter,
- unsigned int pat_index,
- u32 flags)
+xehp_ppgtt_insert_huge(struct i915_address_space *vm,
+ struct i915_vma_resource *vma_res,
+ struct sgt_dma *iter,
+ unsigned int pat_index,
+ u32 flags)
{
const gen8_pte_t pte_encode = vm->pte_encode(0, pat_index, flags);
unsigned int rem = sg_dma_len(iter->sg);
@@ -741,8 +741,8 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
struct sgt_dma iter = sgt_dma(vma_res);
if (vma_res->bi.page_sizes.sg > I915_GTT_PAGE_SIZE) {
- if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 50))
- xehpsdv_ppgtt_insert_huge(vm, vma_res, ,
pat_index, flags);
+ if (GRAPHICS_VER_FULL(vm->i915) >= IP_VER(12, 55))
+ xehp_ppgtt_insert_huge(vm, vma_res, , pat_index,
flags);
else
gen8_ppgtt_insert_huge(vm, vma_res, , pat_index,
flags);
} else {
@@ -781,11 +781,11 @@ static void gen8_ppgtt_insert_entry(struct
i915_address_space *vm,
drm_clflush_virt_range([gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
-static void __xehpsdv_ppgtt_insert_entry_lm(struct
