Re: [PATCH 4/5] drm/i915: Drop dead code for pvc
On Mon, Mar 11, 2024 at 10:35:20AM -0500, Lucas De Marchi wrote: > On Mon, Mar 11, 2024 at 11:29:31AM -0400, Rodrigo Vivi wrote: > > > @@ -2907,9 +2829,7 @@ engine_init_workarounds(struct intel_engine_cs > > > *engine, struct i915_wa_list *wal > > > if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) > > > general_render_compute_wa_init(engine, wal); > > > > > > - if (engine->class == COMPUTE_CLASS) > > > - ccs_engine_wa_init(engine, wal); > > > - else if (engine->class == RENDER_CLASS) > > > > I don't believe we need to remove this chunk since we are not deleting the > > ccs_engine_wa_init. > > If we want to keep that as a placeholder we should also keep the caller as > > well. > > right... I had removed it but brought it back since I noticed the > kernel-doc mentions and forgot to bring back the caller too. I will fix > this in next rev. thanks! with that: Reviewed-by: Rodrigo Vivi > > > thanks > Lucas De Marchi
Re: [PATCH 4/5] drm/i915: Drop dead code for pvc
On Mon, Mar 11, 2024 at 11:29:31AM -0400, Rodrigo Vivi wrote: @@ -2907,9 +2829,7 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) general_render_compute_wa_init(engine, wal); - if (engine->class == COMPUTE_CLASS) - ccs_engine_wa_init(engine, wal); - else if (engine->class == RENDER_CLASS) I don't believe we need to remove this chunk since we are not deleting the ccs_engine_wa_init. If we want to keep that as a placeholder we should also keep the caller as well. right... I had removed it but brought it back since I noticed the kernel-doc mentions and forgot to bring back the caller too. I will fix this in next rev. thanks Lucas De Marchi
Re: [PATCH 4/5] drm/i915: Drop dead code for pvc
On Wed, Mar 06, 2024 at 11:36:42AM -0800, Lucas De Marchi wrote:
> PCI IDs for PVC were never added and platform always marked with
> force_probe. Drop what's not used and rename some places as needed.
>
> The registers not used anymore are also removed.
>
> Signed-off-by: Lucas De Marchi
> ---
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 30 +---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 9 --
> drivers/gpu/drm/i915/gt/intel_mocs.c | 19 ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_sseu.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 90 +--
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
> drivers/gpu/drm/i915/i915_debugfs.c | 12 --
> drivers/gpu/drm/i915/i915_drv.h | 9 --
> drivers/gpu/drm/i915/i915_pci.c | 36 -
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> drivers/gpu/drm/i915/intel_clock_gating.c | 16 +-
> drivers/gpu/drm/i915/intel_device_info.c | 1 -
> drivers/gpu/drm/i915/intel_device_info.h | 1 -
> drivers/gpu/drm/i915/intel_step.c | 70 +
> drivers/gpu/drm/i915/intel_uncore.c | 142 --
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 -
> .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 -
> 21 files changed, 12 insertions(+), 485 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 0c5cdab278b6..d3300ae3053f 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -386,7 +386,7 @@ struct drm_i915_gem_object {
>* and kernel mode driver for caching policy control after GEN12.
>* In the meantime platform specific tables are created to translate
>* i915_cache_level into pat index, for more details check the macros
> - * defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
> + * defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
>* For backward compatibility, this field contains values exactly match
>* the entries of enum i915_cache_level for pre-GEN12 platforms (See
>* LEGACY_CACHELEVEL), so that the PTE encode functions for these
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 24d1c28201fa..2e27bcb52e0d 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct
> intel_engine_cs *engine)
> {
> i915_reg_t reg = gen12_get_aux_inv_reg(engine);
>
> - if (IS_PONTEVECCHIO(engine->i915))
> - return false;
> -
> /*
>* So far platforms supported by i915 having flat ccs do not require
>* AUX invalidation. Check also whether the engine requires it.
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 75bde8c1aa5d..396f5fe993c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct
> intel_gt *gt)
> }
> }
>
> -static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
> -{
> - struct drm_i915_private *i915 = gt->i915;
> - struct intel_gt_info *info = >info;
> - unsigned long meml3_mask;
> - unsigned long quad;
> -
> - if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
> - GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
> - return;
> -
> - meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
> - meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
> -
> - /*
> - * Link Copy engines may be fused off according to meml3_mask. Each
> - * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
> - */
> - for_each_clear_bit(quad, _mask, GEN12_MAX_MSLICES) {
> - unsigned int instance = quad * 2 + 1;
> - intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
> -_BCS(instance));
> -
> - if (mask & info->engine_mask) {
> - gt_dbg(gt, "bcs%u fused off\n", instance);
> - gt_dbg(gt, "bcs%u fused off\n", instance + 1);
> -
> - info->engine_mask &= ~mask;
> - }
> - }
> -}
> -
> /*
> * Determine which engines are fused off in our particular hardware.
> * Note that we have a catch-22 situation where we need to be able to access
> @@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct
> intel_gt *gt)
>
>
[PATCH 4/5] drm/i915: Drop dead code for pvc
PCI IDs for PVC were never added and platform always marked with
force_probe. Drop what's not used and rename some places as needed.
The registers not used anymore are also removed.
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 -
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 30 +---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 9 --
drivers/gpu/drm/i915/gt/intel_mocs.c | 19 ---
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 9 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 90 +--
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 12 --
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_pci.c | 36 -
drivers/gpu/drm/i915/i915_reg.h | 1 -
drivers/gpu/drm/i915/intel_clock_gating.c | 16 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 1 -
drivers/gpu/drm/i915/intel_step.c | 70 +
drivers/gpu/drm/i915/intel_uncore.c | 142 --
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 -
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 -
21 files changed, 12 insertions(+), 485 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0c5cdab278b6..d3300ae3053f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -386,7 +386,7 @@ struct drm_i915_gem_object {
* and kernel mode driver for caching policy control after GEN12.
* In the meantime platform specific tables are created to translate
* i915_cache_level into pat index, for more details check the macros
-* defined i915/i915_pci.c, e.g. PVC_CACHELEVEL.
+* defined i915/i915_pci.c, e.g. MTL_CACHELEVEL.
* For backward compatibility, this field contains values exactly match
* the entries of enum i915_cache_level for pre-GEN12 platforms (See
* LEGACY_CACHELEVEL), so that the PTE encode functions for these
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 24d1c28201fa..2e27bcb52e0d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -189,9 +189,6 @@ static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs
*engine)
{
i915_reg_t reg = gen12_get_aux_inv_reg(engine);
- if (IS_PONTEVECCHIO(engine->i915))
- return false;
-
/*
* So far platforms supported by i915 having flat ccs do not require
* AUX invalidation. Check also whether the engine requires it.
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 75bde8c1aa5d..396f5fe993c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -839,38 +839,6 @@ static void engine_mask_apply_compute_fuses(struct
intel_gt *gt)
}
}
-static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
-{
- struct drm_i915_private *i915 = gt->i915;
- struct intel_gt_info *info = >info;
- unsigned long meml3_mask;
- unsigned long quad;
-
- if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
- GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
- return;
-
- meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
- meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
-
- /*
-* Link Copy engines may be fused off according to meml3_mask. Each
-* bit is a quad that houses 2 Link Copy and two Sub Copy engines.
-*/
- for_each_clear_bit(quad, _mask, GEN12_MAX_MSLICES) {
- unsigned int instance = quad * 2 + 1;
- intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
- _BCS(instance));
-
- if (mask & info->engine_mask) {
- gt_dbg(gt, "bcs%u fused off\n", instance);
- gt_dbg(gt, "bcs%u fused off\n", instance + 1);
-
- info->engine_mask &= ~mask;
- }
- }
-}
-
/*
* Determine which engines are fused off in our particular hardware.
* Note that we have a catch-22 situation where we need to be able to access
@@ -889,7 +857,6 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
engine_mask_apply_media_fuses(gt);
engine_mask_apply_compute_fuses(gt);
- engine_mask_apply_copy_fuses(gt);
/*
* The only use of the GSC CS is to load and communicate with the GSC
