Quoting Shekhar Chauhan (2024-03-05 00:58:00-03:00)
>The driver currently waits 1ms for idle patterns,
>but for LNL and later platforms, it requires a
I would say "for Xe2LPD and possibly future display IPs, it requires". I
feel the requirement is not necessarily tied to the platform itself.
>1640us (rounded up to 2ms) timeout whilst waiting
>for idle patterns for MST streams.
>
>To simplify the code, the timeout is uniformly
>increased by 1ms across all platforms.
To be more precise, "platforms/display IPs"?
>
>v1: Introduced the 2ms wait timeout.
>v2: Segregated the wait timeout for platforms before & after LNL.
>v3: Fixed 2 cosmetic changes.
>v4: Revert to v2 design with commit message enhancements.
>
>BSpec: 68849
>Signed-off-by: Shekhar Chauhan
With the tweaks to the commit message above,
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>b/drivers/gpu/drm/i915/display/intel_ddi.c
>index bea441590204..05ba3642d486 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3680,7 +3680,7 @@ static void intel_ddi_set_idle_link_train(struct
>intel_dp *intel_dp,
>
> if (intel_de_wait_for_set(dev_priv,
> dp_tp_status_reg(encoder, crtc_state),
>- DP_TP_STATUS_IDLE_DONE, 1))
>+ DP_TP_STATUS_IDLE_DONE, 2))
> drm_err(&dev_priv->drm,
> "Timed out waiting for DP idle patterns\n");
> }
>--
>2.34.1
>
