RE: [RFC PATCH 1/3] drm/fourcc: define Intel Xe2 related tile4 ccs modifier

[Chery, Nanley G]

> -Original Message-
> From: Juha-Pekka Heikkila 
> Sent: Monday, May 6, 2024 2:53 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Juha-Pekka Heikkila ; Chery, Nanley G 
> ; Saarinen, Jani
> ; Graunke, Kenneth W ; 
> Souza, Jose ; Mathew, Alwin
> ; Zhang, Jianxun ; Syrjala, 
> Ville ; Nikula, Jani
> 
> Subject: [RFC PATCH 1/3] drm/fourcc: define Intel Xe2 related tile4 ccs 
> modifier
> 
> Add Tile4 type ccs modifier to indicate presence of compression on Xe2
> 
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  include/uapi/drm/drm_fourcc.h | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 84d502e42961..50db2cc89642 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -702,6 +702,18 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
> 
> +/*
> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 render 
> compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all compressible GEM objects. The main surface pitch is
> + * required to be a multiple of four Tile 4 widths.
> + */

The pitch requirement is gone on this generation, isn't it?

-Nanley

> +#define I915_FORMAT_MOD_4_TILED_XE2_CCS fourcc_mod_code(INTEL, 16)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> --
> 2.43.2

[RFC PATCH 1/3] drm/fourcc: define Intel Xe2 related tile4 ccs modifier

[Juha-Pekka Heikkila]

Add Tile4 type ccs modifier to indicate presence of compression on Xe2

Signed-off-by: Juha-Pekka Heikkila 
---
 include/uapi/drm/drm_fourcc.h | 12 
 1 file changed, 12 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 84d502e42961..50db2cc89642 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -702,6 +702,18 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
 
+/*
+ * Intel Color Control Surfaces (CCS) for graphics ver. 20 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all compressible GEM objects. The main surface pitch is
+ * required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_XE2_CCS fourcc_mod_code(INTEL, 16)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.43.2