Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-10-13 Thread Daniel Vetter 
On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote:
> On Wed, 26 Aug 2015, Chris Wilson  wrote:
> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
> >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
> >> > In order to flush the results from in-batch pipecontrol writes (used for
> >> > example in glQuery) before declaring the batch complete (and so declaring
> >> > the query results coherent), we need to set the FlushEnable bit in our
> >> > flushing pipecontrol. The FlushEnable bit "waits until all previous
> >> > writes of immediate data from post-sync circles are complete before
> >> > executing the next command".
> >> > 
> >> > Signed-off-by: Chris Wilson 
> >> > Cc: sta...@vger.kernel.org
> >> 
> >> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
> >> bugzilla or why is this cc: stable?
> >
> > I get GPU hangs on byt without flushing these writes (running ue4).
> > piglit has examples where the flush is required for correct rendering.
> 
> Daniel, does this satisfy your question? We've had an r-b from Ville for
> a long time.

Yeah, just add that bit to the commit message to justify cc: stable.
-Daniel
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Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-10-13 Thread Jani Nikula 
On Tue, 13 Oct 2015, Daniel Vetter  wrote:
> On Tue, Oct 13, 2015 at 03:45:58PM +0300, Jani Nikula wrote:
>> On Wed, 26 Aug 2015, Chris Wilson  wrote:
>> > On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
>> >> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
>> >> > In order to flush the results from in-batch pipecontrol writes (used for
>> >> > example in glQuery) before declaring the batch complete (and so 
>> >> > declaring
>> >> > the query results coherent), we need to set the FlushEnable bit in our
>> >> > flushing pipecontrol. The FlushEnable bit "waits until all previous
>> >> > writes of immediate data from post-sync circles are complete before
>> >> > executing the next command".
>> >> > 
>> >> > Signed-off-by: Chris Wilson 
>> >> > Cc: sta...@vger.kernel.org
>> >> 
>> >> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
>> >> bugzilla or why is this cc: stable?
>> >
>> > I get GPU hangs on byt without flushing these writes (running ue4).
>> > piglit has examples where the flush is required for correct rendering.
>> 
>> Daniel, does this satisfy your question? We've had an r-b from Ville for
>> a long time.
>
> Yeah, just add that bit to the commit message to justify cc: stable.

Pushed to drm-intel-fixes, thanks for the patch and review.

BR,
Jani.

> -Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

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Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-10-13 Thread Jani Nikula 
On Wed, 26 Aug 2015, Chris Wilson  wrote:
> On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
>> On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
>> > In order to flush the results from in-batch pipecontrol writes (used for
>> > example in glQuery) before declaring the batch complete (and so declaring
>> > the query results coherent), we need to set the FlushEnable bit in our
>> > flushing pipecontrol. The FlushEnable bit "waits until all previous
>> > writes of immediate data from post-sync circles are complete before
>> > executing the next command".
>> > 
>> > Signed-off-by: Chris Wilson 
>> > Cc: sta...@vger.kernel.org
>> 
>> Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
>> bugzilla or why is this cc: stable?
>
> I get GPU hangs on byt without flushing these writes (running ue4).
> piglit has examples where the flush is required for correct rendering.

Daniel, does this satisfy your question? We've had an r-b from Ville for
a long time.

BR,
Jani.


> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-08-28 Thread shuang . he 
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 7243
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
ILK  302/302  302/302
SNB  315/315  315/315
IVB  336/336  336/336
BYT  283/283  283/283
HSW  378/378  378/378
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
Note: You need to pay more attention to line start with '*'
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Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-08-26 Thread Daniel Vetter 
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
 In order to flush the results from in-batch pipecontrol writes (used for
 example in glQuery) before declaring the batch complete (and so declaring
 the query results coherent), we need to set the FlushEnable bit in our
 flushing pipecontrol. The FlushEnable bit waits until all previous
 writes of immediate data from post-sync circles are complete before
 executing the next command.
 
 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
 Cc: sta...@vger.kernel.org

Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
bugzilla or why is this cc: stable?
-Daniel

 ---
  drivers/gpu/drm/i915/intel_lrc.c| 1 +
  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
  2 files changed, 3 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
 b/drivers/gpu/drm/i915/intel_lrc.c
 index 01cf0ca21990..e0c19d75b196 100644
 --- a/drivers/gpu/drm/i915/intel_lrc.c
 +++ b/drivers/gpu/drm/i915/intel_lrc.c
 @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct 
 drm_i915_gem_request *request,
   if (flush_domains) {
   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 + flags |= PIPE_CONTROL_FLUSH_ENABLE;
   }
  
   if (invalidate_domains) {
 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
 b/drivers/gpu/drm/i915/intel_ringbuffer.c
 index c2392f6c4204..551af7399ca1 100644
 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
 +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
 @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
   if (flush_domains) {
   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 + flags |= PIPE_CONTROL_FLUSH_ENABLE;
   }
   if (invalidate_domains) {
   flags |= PIPE_CONTROL_TLB_INVALIDATE;
 @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
   if (flush_domains) {
   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 + flags |= PIPE_CONTROL_FLUSH_ENABLE;
   }
   if (invalidate_domains) {
   flags |= PIPE_CONTROL_TLB_INVALIDATE;
 -- 
 2.5.0
 
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Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-08-26 Thread Chris Wilson 
On Wed, Aug 26, 2015 at 11:16:34AM +0200, Daniel Vetter wrote:
 On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
  In order to flush the results from in-batch pipecontrol writes (used for
  example in glQuery) before declaring the batch complete (and so declaring
  the query results coherent), we need to set the FlushEnable bit in our
  flushing pipecontrol. The FlushEnable bit waits until all previous
  writes of immediate data from post-sync circles are complete before
  executing the next command.
  
  Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
  Cc: sta...@vger.kernel.org
 
 Do we have an igt/piglit failing somewhere (igt kinda preferred) or a
 bugzilla or why is this cc: stable?

I get GPU hangs on byt without flushing these writes (running ue4).
piglit has examples where the flush is required for correct rendering.
-Chris

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Re: [Intel-gfx] [PATCH] drm/i915: Flush pipecontrol post-sync writes

2015-08-21 Thread Ville Syrjälä 
On Fri, Aug 21, 2015 at 04:08:41PM +0100, Chris Wilson wrote:
 In order to flush the results from in-batch pipecontrol writes (used for
 example in glQuery) before declaring the batch complete (and so declaring
 the query results coherent), we need to set the FlushEnable bit in our
 flushing pipecontrol. The FlushEnable bit waits until all previous
 writes of immediate data from post-sync circles are complete before
 executing the next command.
 
 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
 Cc: sta...@vger.kernel.org

Yeah makes as much sense as anything about pipecontrols.
Reviewed-by: Ville Syrjälä ville.syrj...@linux.intel.com

Though the spec makes me thing it would be even more appropriate if
we did the seqno write using a post-sync operation and followed it
with such a pipecontrol flush. But I've not actually played around
with this stuff, so can't say for sure.

Oh and we're also lacking DC flushes everywhere, in case someone
cares.

 ---
  drivers/gpu/drm/i915/intel_lrc.c| 1 +
  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
  2 files changed, 3 insertions(+)
 
 diff --git a/drivers/gpu/drm/i915/intel_lrc.c 
 b/drivers/gpu/drm/i915/intel_lrc.c
 index 01cf0ca21990..e0c19d75b196 100644
 --- a/drivers/gpu/drm/i915/intel_lrc.c
 +++ b/drivers/gpu/drm/i915/intel_lrc.c
 @@ -1771,6 +1771,7 @@ static int gen8_emit_flush_render(struct 
 drm_i915_gem_request *request,
   if (flush_domains) {
   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 + flags |= PIPE_CONTROL_FLUSH_ENABLE;
   }
  
   if (invalidate_domains) {
 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
 b/drivers/gpu/drm/i915/intel_ringbuffer.c
 index c2392f6c4204..551af7399ca1 100644
 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
 +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
 @@ -330,6 +330,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
   if (flush_domains) {
   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 + flags |= PIPE_CONTROL_FLUSH_ENABLE;
   }
   if (invalidate_domains) {
   flags |= PIPE_CONTROL_TLB_INVALIDATE;
 @@ -401,6 +402,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
   if (flush_domains) {
   flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
   flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 + flags |= PIPE_CONTROL_FLUSH_ENABLE;
   }
   if (invalidate_domains) {
   flags |= PIPE_CONTROL_TLB_INVALIDATE;
 -- 
 2.5.0
 
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