Re: [Intel-gfx] [PATCH 07/15] drm/i915: there's no DSPADDR register on Haswell

2013-03-20 Thread Paulo Zanoni 
Hi

2013/3/17 Daniel Vetter dan...@ffwll.ch:
 On Fri, Mar 15, 2013 at 12:10:02PM -0700, Ben Widawsky wrote:
 On Wed, Mar 06, 2013 at 08:03:14PM -0300, Paulo Zanoni wrote:
  From: Paulo Zanoni paulo.r.zan...@intel.com
 
  So don't read it when we hang the GPU. This solves unclaimed
  register messages.
 
  Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
 It would be nice if you could make this a bit more future proof, but
 looks correct to me:

 Done.

Done for intel_display_capture_error_state but not for
intel_display_print_error_state. Do you want to fix this or do you
want me to send a patch on top of dinq?

Thanks for the reviews!
Paulo


 Reviewed-by: Ben Widawsky b...@bwidawsk.net
 Queued for -next, thanks for the patch.
 -Daniel
 --
 Daniel Vetter
 Software Engineer, Intel Corporation
 +41 (0) 79 365 57 48 - http://blog.ffwll.ch



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Re: [Intel-gfx] [PATCH 07/15] drm/i915: there's no DSPADDR register on Haswell

2013-03-20 Thread Daniel Vetter 
On Wed, Mar 20, 2013 at 03:01:34PM -0300, Paulo Zanoni wrote:
 Hi
 
 2013/3/17 Daniel Vetter dan...@ffwll.ch:
  On Fri, Mar 15, 2013 at 12:10:02PM -0700, Ben Widawsky wrote:
  On Wed, Mar 06, 2013 at 08:03:14PM -0300, Paulo Zanoni wrote:
   From: Paulo Zanoni paulo.r.zan...@intel.com
  
   So don't read it when we hang the GPU. This solves unclaimed
   register messages.
  
   Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
  It would be nice if you could make this a bit more future proof, but
  looks correct to me:
 
  Done.
 
 Done for intel_display_capture_error_state but not for
 intel_display_print_error_state. Do you want to fix this or do you
 want me to send a patch on top of dinq?

Oh, I've failed again ;-) Yes, please submit a patch since due to the
backmerge it'll be a mess to rebase this one out.

Thanks, Daniel
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Re: [Intel-gfx] [PATCH 07/15] drm/i915: there's no DSPADDR register on Haswell

2013-03-17 Thread Daniel Vetter 
On Fri, Mar 15, 2013 at 12:10:02PM -0700, Ben Widawsky wrote:
 On Wed, Mar 06, 2013 at 08:03:14PM -0300, Paulo Zanoni wrote:
  From: Paulo Zanoni paulo.r.zan...@intel.com
  
  So don't read it when we hang the GPU. This solves unclaimed
  register messages.
  
  Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
 It would be nice if you could make this a bit more future proof, but
 looks correct to me:

Done.

 Reviewed-by: Ben Widawsky b...@bwidawsk.net
Queued for -next, thanks for the patch.
-Daniel
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Software Engineer, Intel Corporation
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Re: [Intel-gfx] [PATCH 07/15] drm/i915: there's no DSPADDR register on Haswell

2013-03-15 Thread Ben Widawsky 
On Wed, Mar 06, 2013 at 08:03:14PM -0300, Paulo Zanoni wrote:
 From: Paulo Zanoni paulo.r.zan...@intel.com
 
 So don't read it when we hang the GPU. This solves unclaimed
 register messages.
 
 Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
It would be nice if you could make this a bit more future proof, but
looks correct to me:
Reviewed-by: Ben Widawsky b...@bwidawsk.net
 ---
  drivers/gpu/drm/i915/intel_display.c |6 --
  1 file changed, 4 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/intel_display.c 
 b/drivers/gpu/drm/i915/intel_display.c
 index 56cca6e..0451056 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -9351,7 +9351,8 @@ intel_display_capture_error_state(struct drm_device 
 *dev)
   if (INTEL_INFO(dev)-gen = 3)
   error-plane[i].size = I915_READ(DSPSIZE(i));
   error-plane[i].pos = I915_READ(DSPPOS(i));
 - error-plane[i].addr = I915_READ(DSPADDR(i));
 + if (!IS_HASWELL(dev))
 + error-plane[i].addr = I915_READ(DSPADDR(i));
   if (INTEL_INFO(dev)-gen = 4) {
   error-plane[i].surface = I915_READ(DSPSURF(i));
   error-plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
 @@ -9396,7 +9397,8 @@ intel_display_print_error_state(struct seq_file *m,
   if (INTEL_INFO(dev)-gen = 3)
   seq_printf(m,   SIZE: %08x\n, error-plane[i].size);
   seq_printf(m,   POS: %08x\n, error-plane[i].pos);
 - seq_printf(m,   ADDR: %08x\n, error-plane[i].addr);
 + if (!IS_HASWELL(dev))
 + seq_printf(m,   ADDR: %08x\n, error-plane[i].addr);
   if (INTEL_INFO(dev)-gen = 4) {
   seq_printf(m,   SURF: %08x\n, 
 error-plane[i].surface);
   seq_printf(m,   TILEOFF: %08x\n, 
 error-plane[i].tile_offset);
 -- 
 1.7.10.4
 
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