Re: [Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec
On Fri, 2021-04-23 at 12:25 +0200, Maarten Lankhorst wrote: > Op 22-04-2021 om 13:00 schreef Mun, Gwan-gyeong: > > The changed name looks more accurate to the edp 1.4b spec. > > Looks good to me. > > > > Reviewed-by: Gwan-gyeong Mun > > > > On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote: > > > DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture > > > Indication" in eDP spec has a ambiguous name, so renaming to better > > > match specification. > > > > > > While at it, replacing bit shit by BIT() macro and adding the version > > > some registers were added to eDP specification. > > > > > > Cc: > > > Cc: Rodrigo Vivi > > > Cc: Jani Nikula > > > Cc: Gwan-gyeong Mun > > > Signed-off-by: José Roberto de Souza > > > --- > > > include/drm/drm_dp_helper.h | 16 > > > 1 file changed, 8 insertions(+), 8 deletions(-) > > > > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > > index 1e85c2021f2f..d6f6a084a190 100644 > > > --- a/include/drm/drm_dp_helper.h > > > +++ b/include/drm/drm_dp_helper.h > > > @@ -687,14 +687,14 @@ struct drm_device; > > > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ > > > # define DP_DECOMPRESSION_EN (1 << 0) > > > > > > -#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > > > -# define DP_PSR_ENABLE (1 << 0) > > > -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) > > > -# define DP_PSR_CRC_VERIFICATION (1 << 2) > > > -# define DP_PSR_FRAME_CAPTURE (1 << 3) > > > -# define DP_PSR_SELECTIVE_UPDATE (1 << 4) > > > -# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) > > > -# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ > > > +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > > > +# define DP_PSR_ENABLE BIT(0) > > > +# define DP_PSR_MAIN_LINK_ACTIVE BIT(1) > > > +# define DP_PSR_CRC_VERIFICATION BIT(2) > > > +# define DP_PSR_FRAME_CAPTURE BIT(3) > > > +# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ > > > +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORSBIT(5) /* eDP > > > 1.4a */ > > > +# define DP_PSR_ENABLE_PSR2BIT(6) /* eDP 1.4a */ > > > > > > #define DP_ADAPTER_CTRL 0x1a0 > > > # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > This should probably go throuh drm-misc-next, I don't see the next patch > depending on this? The patch depending on this change will be sent right after this one is merged. > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec
Op 22-04-2021 om 13:00 schreef Mun, Gwan-gyeong: > The changed name looks more accurate to the edp 1.4b spec. > Looks good to me. > > Reviewed-by: Gwan-gyeong Mun > > On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote: >> DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture >> Indication" in eDP spec has a ambiguous name, so renaming to better >> match specification. >> >> While at it, replacing bit shit by BIT() macro and adding the version >> some registers were added to eDP specification. >> >> Cc: >> Cc: Rodrigo Vivi >> Cc: Jani Nikula >> Cc: Gwan-gyeong Mun >> Signed-off-by: José Roberto de Souza >> --- >> include/drm/drm_dp_helper.h | 16 >> 1 file changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index 1e85c2021f2f..d6f6a084a190 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -687,14 +687,14 @@ struct drm_device; >> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ >> # define DP_DECOMPRESSION_EN (1 << 0) >> >> -#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ >> -# define DP_PSR_ENABLE (1 << 0) >> -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) >> -# define DP_PSR_CRC_VERIFICATION (1 << 2) >> -# define DP_PSR_FRAME_CAPTURE (1 << 3) >> -# define DP_PSR_SELECTIVE_UPDATE (1 << 4) >> -# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) >> -# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ >> +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ >> +# define DP_PSR_ENABLE BIT(0) >> +# define DP_PSR_MAIN_LINK_ACTIVE BIT(1) >> +# define DP_PSR_CRC_VERIFICATION BIT(2) >> +# define DP_PSR_FRAME_CAPTURE BIT(3) >> +# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ >> +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORSBIT(5) /* eDP >> 1.4a */ >> +# define DP_PSR_ENABLE_PSR2BIT(6) /* eDP 1.4a */ >> >> #define DP_ADAPTER_CTRL 0x1a0 >> # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx This should probably go throuh drm-misc-next, I don't see the next patch depending on this? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec
The changed name looks more accurate to the edp 1.4b spec. Looks good to me. Reviewed-by: Gwan-gyeong Mun On Wed, 2021-04-21 at 15:02 -0700, José Roberto de Souza wrote: > DP_PSR_EN_CFG bit 5 aka "Selective Update Region Scan Line Capture > Indication" in eDP spec has a ambiguous name, so renaming to better > match specification. > > While at it, replacing bit shit by BIT() macro and adding the version > some registers were added to eDP specification. > > Cc: > Cc: Rodrigo Vivi > Cc: Jani Nikula > Cc: Gwan-gyeong Mun > Signed-off-by: José Roberto de Souza > --- > include/drm/drm_dp_helper.h | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 1e85c2021f2f..d6f6a084a190 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -687,14 +687,14 @@ struct drm_device; > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ > # define DP_DECOMPRESSION_EN (1 << 0) > > -#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > -# define DP_PSR_ENABLE (1 << 0) > -# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) > -# define DP_PSR_CRC_VERIFICATION (1 << 2) > -# define DP_PSR_FRAME_CAPTURE (1 << 3) > -# define DP_PSR_SELECTIVE_UPDATE (1 << 4) > -# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) > -# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ > +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > +# define DP_PSR_ENABLE BIT(0) > +# define DP_PSR_MAIN_LINK_ACTIVE BIT(1) > +# define DP_PSR_CRC_VERIFICATION BIT(2) > +# define DP_PSR_FRAME_CAPTURE BIT(3) > +# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ > +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORSBIT(5) /* eDP > 1.4a */ > +# define DP_PSR_ENABLE_PSR2BIT(6) /* eDP 1.4a */ > > #define DP_ADAPTER_CTRL 0x1a0 > # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
