On Thursday 27 March 2014 01:54 PM, Chris Wilson wrote:
The speculation is that we can conserve more power by masking off the
interrupts at source (PMINTRMSK) rather than filtering them by the
up/down thresholds (RPINTLIM).
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Cc: Deepak S deepa...@intel.com
Cc: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3ad590924062..0a76e9baeca2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3006,6 +3006,25 @@ static void gen6_set_rps_thresholds(struct
drm_i915_private *dev_priv, u8 val)
dev_priv-rps.last_adj = 0;
}
+static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
+{
+ u32 mask;
+
+ mask = GEN6_PM_RP_DOWN_TIMEOUT;
+ if (val dev_priv-rps.min_freq_softlimit)
+ mask |= GEN6_PM_RP_DOWN_THRESHOLD;
+ if (val dev_priv-rps.max_freq_softlimit)
+ mask |= GEN6_PM_RP_UP_THRESHOLD;
+
+ /* IVB and SNB hard hangs on looping batchbuffer
+* if GEN6_PM_UP_EI_EXPIRED is masked.
+*/
+ if (INTEL_INFO(dev_priv-dev)-gen = 7 !IS_HASWELL(dev_priv-dev))
+ mask |= GEN6_PM_RP_UP_EI_EXPIRED;
+
+ return ~mask;
+}
+
/* gen6_set_rps is called to update the frequency request, but should also be
* called when the range (min_delay and max_delay) is modified so that we can
* update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
@@ -3037,6 +3056,7 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
* until we hit the minimum or maximum frequencies.
*/
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
+ I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
POSTING_READ(GEN6_RPNSWREQ);
@@ -3220,24 +3240,12 @@ int intel_enable_rc6(const struct drm_device *dev)
static void gen6_enable_rps_interrupts(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
- u32 enabled_intrs;
spin_lock_irq(dev_priv-irq_lock);
WARN_ON(dev_priv-rps.pm_iir);
snb_enable_pm_irq(dev_priv, dev_priv-pm_rps_events);
I915_WRITE(GEN6_PMIIR, dev_priv-pm_rps_events);
spin_unlock_irq(dev_priv-irq_lock);
-
- /* only unmask PM interrupts we need. Mask all others. */
- enabled_intrs = dev_priv-pm_rps_events;
-
- /* IVB and SNB hard hangs on looping batchbuffer
-* if GEN6_PM_UP_EI_EXPIRED is masked.
-*/
- if (INTEL_INFO(dev)-gen = 7 !IS_HASWELL(dev))
- enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
-
- I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
}
static void gen8_enable_rps(struct drm_device *dev)
On VLV, gen6_enable_rps_interrupts is used to enable turbo
interrutpts. I think we need to extend gen6_rps_pm_maskto valleyview also?
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