Re: [Intel-gfx] [PATCH 6/7] drm/i915: implement async flush w/a

2012-04-10 Thread Paul Menzel 
Am Samstag, den 31.03.2012, 11:52 +0100 schrieb Chris Wilson:
 On Sat, 31 Mar 2012 11:22:02 +0200, Daniel Vetter daniel.vet...@ffwll.ch 
 wrote:
  Note that async flush also means things like VT-d IOTLB invalidation.
  
  See Bspec vol1c.4 Render Engine Command Streamer, Section ECOSKPD -
  Eco Scratch Pad.
  
  It doesn't seem to help in for any of our VT-d related bugs thoug.

While we are at it: thoug*h*.

  Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
  ---
   drivers/gpu/drm/i915/i915_reg.h  |1 +
   drivers/gpu/drm/i915/intel_display.c |3 +++
   2 files changed, 4 insertions(+), 0 deletions(-)

[…]


Thanks,

Paul


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Re: [Intel-gfx] [PATCH 6/7] drm/i915: implement async flush w/a

2012-04-10 Thread Ben Widawsky 
On Sat, Mar 31, 2012 at 11:22:02AM +0200, Daniel Vetter wrote:
 Note that async flush also means things like VT-d IOTLB invalidation.
 
 See Bspec vol1c.4 Render Engine Command Streamer, Section ECOSKPD -
 Eco Scratch Pad.
 
 It doesn't seem to help in for any of our VT-d related bugs thoug.
 
 Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch

I think we don't want this one from what the bspec says, though I am a
bit unclear.

So I intend to not r-b this one unless I manage to learn how to work our
internal bug database better.

Ben
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Re: [Intel-gfx] [PATCH 6/7] drm/i915: implement async flush w/a

2012-03-31 Thread Chris Wilson 
On Sat, 31 Mar 2012 11:22:02 +0200, Daniel Vetter daniel.vet...@ffwll.ch 
wrote:
 Note that async flush also means things like VT-d IOTLB invalidation.
 
 See Bspec vol1c.4 Render Engine Command Streamer, Section ECOSKPD -
 Eco Scratch Pad.
 
 It doesn't seem to help in for any of our VT-d related bugs thoug.
 
 Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
 ---
  drivers/gpu/drm/i915/i915_reg.h  |1 +
  drivers/gpu/drm/i915/intel_display.c |3 +++
  2 files changed, 4 insertions(+), 0 deletions(-)
 
 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
 index a7ef74a..5b23d5c 100644
 --- a/drivers/gpu/drm/i915/i915_reg.h
 +++ b/drivers/gpu/drm/i915/i915_reg.h
 @@ -583,6 +583,7 @@
  #define BB_ADDR  0x02140 /* 8 bytes */
  #define GFX_FLSH_CNTL0x02170 /* 915+ only */
  #define ECOSKPD  0x021d0
 +#define   ECO_ASYNC_FLUSH_FIX_REVERT (17)
  #define   ECO_GATING_CX_ONLY (13)
  #define   ECO_FLIP_DONE  (10)
  
 diff --git a/drivers/gpu/drm/i915/intel_display.c 
 b/drivers/gpu/drm/i915/intel_display.c
 index dab2381..dce64d8 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -8510,6 +8510,9 @@ static void gen6_init_clock_gating(struct drm_device 
 *dev)
   I915_WRITE(WM2_LP_ILK, 0);
   I915_WRITE(WM1_LP_ILK, 0);
  
 + I915_WRITE(ECOSKPD, (ECO_ASYNC_FLUSH_FIX_REVERT  16) |
 + ECO_ASYNC_FLUSH_FIX_REVERT);
Just a request for a standardised means of setting masked bits:

#define MASKED_ENABLE(x) ((x)  16) | (x))
#define MASKED_DISABLE(x) ((x)  16) | 0)

see MI_MODE, GFX_MODE.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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