Re: [Intel-gfx] [PATCH 8/8] drm/i915: Follow the forcewake domains type on hw accessors

2014-12-09 Thread shuang . he 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
-Summary-
Platform  Delta  drm-intel-nightly  Series Applied
PNV  364/364  364/364
ILK  +1-3  364/366  362/366
SNB -19  448/450  429/450
IVB  497/498  497/498
BYT  289/289  289/289
HSW -83  563/564  480/564
BDW -4  417/417  413/417
-Detailed-
Platform  Testdrm-intel-nightly  Series 
Applied
 ILK  igt_kms_flip_blocking-absolute-wf_vblank-interruptible  DMESG_WARN(1, 
M26)PASS(3, M26)  DMESG_WARN(1, M26)
*ILK  igt_kms_flip_busy-flip-interruptible  PASS(4, M26)  DMESG_WARN(1, 
M26)
*ILK  igt_kms_flip_flip-vs-panning  PASS(3, M26)  DMESG_WARN(1, M26)
 ILK  igt_kms_flip_wf_vblank-ts-check  DMESG_WARN(1, M26)PASS(10, M26M37)   
   PASS(1, M26)
*SNB  igt_pm_rpm_cursor  PASS(2, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_cursor-dpms  PASS(2, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_debugfs-forcewake-user  PASS(1, M35)  DMESG_WARN(1, 
M22)
*SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp  PASS(1, M35)  DMESG_WARN(1, 
M22)
*SNB  igt_pm_rpm_dpms-non-lpsp  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_drm-resources-equal  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_fences  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_fences-dpms  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_gem-execbuf  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_gem-idle  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_gem-mmap-cpu  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_gem-mmap-gtt  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_gem-pread  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_i2c  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_modeset-non-lpsp  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait  PASS(1, M35)  
DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_pci-d3-state  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_reg-read-ioctl  PASS(1, M35)  DMESG_WARN(1, M22)
*SNB  igt_pm_rpm_rte  PASS(1, M35)  DMESG_WARN(1, M22)
*HSW  igt_gem_concurrent_blit_cpu-bcs-overwrite-source-forked  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_flip_vblank-vs-dpms-rpm  PASS(2, M40)  DMESG_WARN(1, M40)
*HSW  igt_kms_pipe_crc_basic_read-crc-pipe-A  PASS(2, M40)  
DMESG_WARN(1, M40)
*HSW  igt_kms_pipe_crc_basic_read-crc-pipe-A-frame-sequence  PASS(2, M40)   
   DMESG_WARN(1, M40)
*HSW  igt_kms_pipe_crc_basic_read-crc-pipe-B  PASS(2, M40)  
DMESG_WARN(1, M40)
*HSW  igt_kms_pipe_crc_basic_read-crc-pipe-B-frame-sequence  PASS(2, M40)   
   DMESG_WARN(1, M40)
*HSW  igt_kms_pipe_crc_basic_read-crc-pipe-C  PASS(2, M40)  
DMESG_WARN(1, M40)
*HSW  igt_kms_pipe_crc_basic_read-crc-pipe-C-frame-sequence  PASS(2, M40)   
   DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-bottom-right-pipe-A-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-bottom-right-pipe-B-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-A-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-A-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-B-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-B-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-C-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-C-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-position-covered-pipe-A-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-position-covered-pipe-A-plane-2  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-position-covered-pipe-B-plane-1  PASS(2, M40) 
 DMESG_WARN(1, M40)
*HSW  igt_kms_plane_plane-position-covered-pipe-C-plane-1

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Follow the forcewake domains type on hw accessors

2014-12-11 Thread Deepak S 


On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote:

Forcewake domain code uses unsigned int as a type for 'domains mask'.
Bring the hw accessors inline with this.

Suggested-by: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
  drivers/gpu/drm/i915/intel_uncore.c | 8 
  2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2a8536..917614e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -535,9 +535,9 @@ struct drm_i915_display_funcs {
  
  struct intel_uncore_funcs {

void (*force_wake_get)(struct drm_i915_private *dev_priv,
-   int fw_engine);
+   unsigned fw_domains);
void (*force_wake_put)(struct drm_i915_private *dev_priv,
-   int fw_engine);
+   unsigned fw_domains);
  
  	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, 
bool trace);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 509b9c9..be02aab 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -122,7 +122,7 @@ fw_domain_posting_read(const struct 
intel_uncore_forcewake_domain *d)
  }
  
  static void

-fw_domains_get(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_get(struct drm_i915_private *dev_priv, unsigned fw_domains)
  {
struct intel_uncore_forcewake_domain *d;
int id;
@@ -136,7 +136,7 @@ fw_domains_get(struct drm_i915_private *dev_priv, int 
fw_domains)
  }
  
  static void

-fw_domains_put(struct drm_i915_private *dev_priv, int fw_domains)
+fw_domains_put(struct drm_i915_private *dev_priv, unsigned fw_domains)
  {
struct intel_uncore_forcewake_domain *d;
int id;
@@ -181,7 +181,7 @@ static void __gen6_gt_wait_for_thread_c0(struct 
drm_i915_private *dev_priv)
  }
  
  static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,

- int fw_domains)
+ unsigned fw_domains)
  {
fw_domains_get(dev_priv, fw_domains);
  
@@ -199,7 +199,7 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)

  }
  
  static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,

-int fw_domains)
+unsigned fw_domains)
  {
fw_domains_put(dev_priv, fw_domains);
gen6_gt_check_fifodbg(dev_priv);


Looks fine

Reviewed-by: Deepak S

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