Re: [Intel-gfx] [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Conselvan De Oliveira, Ander]

On Tue, 2016-04-19 at 13:37 -0700, Jim Bride wrote:
> On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:
> > The logic for setting signal levels is used for both HDMI and DP with
> > small variations. But it is similar enough to put behind a function
> > called from the encoders.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira <
> > ander.conselvan.de.olive...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h   |  4 
> >  drivers/gpu/drm/i915/intel_dp.c   | 43 
> > ---
> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +
> >  drivers/gpu/drm/i915/intel_hdmi.c | 14 
> >  4 files changed, 49 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 85c0610..f2481a2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder
> > *encoder);
> >  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> >  void chv_phy_post_disable(struct intel_encoder *encoder);
> >  
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > + u32 demph_reg_value, u32 preemph_reg_value,
> > + u32 uniqtranscale_reg_value, u32 tx3_demph);
> > +
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> >  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index cdacd8b..3e42355 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp,
> > uint8_t voltage_swing)
> >  
> >  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  {
> > -   struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -   struct drm_i915_private *dev_priv = dev->dev_private;
> > -   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > -   struct intel_crtc *intel_crtc =
> > -   to_intel_crtc(dport->base.base.crtc);
> > +   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> > unsigned long demph_reg_value, preemph_reg_value,
> > uniqtranscale_reg_value;
> > uint8_t train_set = intel_dp->train_set[0];
> > -   enum dpio_channel port = vlv_dport_to_channel(dport);
> > -   int pipe = intel_crtc->pipe;
> >  
> > switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> > case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp
> > *intel_dp)
> > return 0;
> > }
> >  
> > -   mutex_lock(_priv->sb_lock);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > -uniqtranscale_reg_value);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x0003);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port),
> > preemph_reg_value);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x8000);
> > -   mutex_unlock(_priv->sb_lock);
> > +   vlv_set_phy_signal_level(encoder, demph_reg_value,
> > preemph_reg_value,
> > +uniqtranscale_reg_value, 0);
> >  
> > return 0;
> >  }
> > @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector
> > *intel_connector)
> > intel_dp->compliance_test_type = 0;
> > intel_dp->compliance_test_data = 0;
> >  
> > -   /*
> > -* If we were in MST mode, and device is not there,
> > -* get out of MST mode
> > -*/
> > -   if (intel_dp->is_mst) {
> > -   DRM_DEBUG_KMS("MST device may have disappeared %d
> > vs %d\n",
> > - intel_dp->is_mst, intel_dp
> > ->mst_mgr.mst_state);
> > -   intel_dp->is_mst = false;
> > -   drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
> > -   intel_dp->is_mst);
> > -   }
> > goto out;
> > }
> >  
> > @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector
> > *intel_connector)
> >  out:
> > if (status != connector_status_connected) {
> > intel_dp_unset_edid(intel_dp);
> > +
> > +   /*
> > +* If we were in MST mode, and device is not there,
> > +* get out of MST mode
> > +*/
> > +   if (intel_dp->is_mst) {
> > +   DRM_DEBUG_KMS("MST device may have disappeared %d
> > vs %d\n",
> > + intel_dp->is_mst, intel_dp
> > ->mst_mgr.mst_state);
> > +   

Re: [Intel-gfx] [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Jim Bride]

On Tue, Apr 19, 2016 at 01:37:26PM -0700, Jim Bride wrote:
> On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:

Same typo in this patch's subject ('Undiplicate') as the previous one.

Jim


> > The logic for setting signal levels is used for both HDMI and DP with
> > small variations. But it is similar enough to put behind a function
> > called from the encoders.
> > 
> > Signed-off-by: Ander Conselvan de Oliveira 
> > 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h   |  4 
> >  drivers/gpu/drm/i915/intel_dp.c   | 43 
> > ---
> >  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +
> >  drivers/gpu/drm/i915/intel_hdmi.c | 14 
> >  4 files changed, 49 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 85c0610..f2481a2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder 
> > *encoder);
> >  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
> >  void chv_phy_post_disable(struct intel_encoder *encoder);
> >  
> > +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> > + u32 demph_reg_value, u32 preemph_reg_value,
> > + u32 uniqtranscale_reg_value, u32 tx3_demph);
> > +
> >  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> >  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index cdacd8b..3e42355 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp 
> > *intel_dp, uint8_t voltage_swing)
> >  
> >  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
> >  {
> > -   struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > -   struct drm_i915_private *dev_priv = dev->dev_private;
> > -   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> > -   struct intel_crtc *intel_crtc =
> > -   to_intel_crtc(dport->base.base.crtc);
> > +   struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> > unsigned long demph_reg_value, preemph_reg_value,
> > uniqtranscale_reg_value;
> > uint8_t train_set = intel_dp->train_set[0];
> > -   enum dpio_channel port = vlv_dport_to_channel(dport);
> > -   int pipe = intel_crtc->pipe;
> >  
> > switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> > case DP_TRAIN_PRE_EMPH_LEVEL_0:
> > @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp 
> > *intel_dp)
> > return 0;
> > }
> >  
> > -   mutex_lock(_priv->sb_lock);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> > -uniqtranscale_reg_value);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x0003);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> > -   vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x8000);
> > -   mutex_unlock(_priv->sb_lock);
> > +   vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> > +uniqtranscale_reg_value, 0);
> >  
> > return 0;
> >  }
> > @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector 
> > *intel_connector)
> > intel_dp->compliance_test_type = 0;
> > intel_dp->compliance_test_data = 0;
> >  
> > -   /*
> > -* If we were in MST mode, and device is not there,
> > -* get out of MST mode
> > -*/
> > -   if (intel_dp->is_mst) {
> > -   DRM_DEBUG_KMS("MST device may have disappeared %d vs 
> > %d\n",
> > - intel_dp->is_mst, 
> > intel_dp->mst_mgr.mst_state);
> > -   intel_dp->is_mst = false;
> > -   drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
> > -   intel_dp->is_mst);
> > -   }
> > goto out;
> > }
> >  
> > @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector 
> > *intel_connector)
> >  out:
> > if (status != connector_status_connected) {
> > intel_dp_unset_edid(intel_dp);
> > +
> > +   /*
> > +* If we were in MST mode, and device is not there,
> > +* get out of MST mode
> > +*/
> > +   if (intel_dp->is_mst) {
> > +   DRM_DEBUG_KMS("MST device may have disappeared %d vs 
> > %d\n",
> > +   

Re: [Intel-gfx] [PATCH v2 07/10] drm/i915: Undiplicate VLV signal level code

[Jim Bride]

On Wed, Apr 13, 2016 at 08:47:50PM +0300, Ander Conselvan de Oliveira wrote:
> The logic for setting signal levels is used for both HDMI and DP with
> small variations. But it is similar enough to put behind a function
> called from the encoders.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  4 
>  drivers/gpu/drm/i915/intel_dp.c   | 43 
> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 26 +
>  drivers/gpu/drm/i915/intel_hdmi.c | 14 
>  4 files changed, 49 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85c0610..f2481a2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3565,6 +3565,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder 
> *encoder);
>  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
>  void chv_phy_post_disable(struct intel_encoder *encoder);
>  
> +void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> +   u32 demph_reg_value, u32 preemph_reg_value,
> +   u32 uniqtranscale_reg_value, u32 tx3_demph);
> +
>  int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
>  int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cdacd8b..3e42355 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3009,16 +3009,10 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, 
> uint8_t voltage_swing)
>  
>  static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
>  {
> - struct drm_device *dev = intel_dp_to_dev(intel_dp);
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> - struct intel_crtc *intel_crtc =
> - to_intel_crtc(dport->base.base.crtc);
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
>   unsigned long demph_reg_value, preemph_reg_value,
>   uniqtranscale_reg_value;
>   uint8_t train_set = intel_dp->train_set[0];
> - enum dpio_channel port = vlv_dport_to_channel(dport);
> - int pipe = intel_crtc->pipe;
>  
>   switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
>   case DP_TRAIN_PRE_EMPH_LEVEL_0:
> @@ -3093,16 +3087,8 @@ static uint32_t vlv_signal_levels(struct intel_dp 
> *intel_dp)
>   return 0;
>   }
>  
> - mutex_lock(_priv->sb_lock);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> -  uniqtranscale_reg_value);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x0003);
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> - vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x8000);
> - mutex_unlock(_priv->sb_lock);
> + vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
> +  uniqtranscale_reg_value, 0);
>  
>   return 0;
>  }
> @@ -4285,17 +4271,6 @@ intel_dp_long_pulse(struct intel_connector 
> *intel_connector)
>   intel_dp->compliance_test_type = 0;
>   intel_dp->compliance_test_data = 0;
>  
> - /*
> -  * If we were in MST mode, and device is not there,
> -  * get out of MST mode
> -  */
> - if (intel_dp->is_mst) {
> - DRM_DEBUG_KMS("MST device may have disappeared %d vs 
> %d\n",
> -   intel_dp->is_mst, 
> intel_dp->mst_mgr.mst_state);
> - intel_dp->is_mst = false;
> - drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
> - intel_dp->is_mst);
> - }
>   goto out;
>   }
>  
> @@ -4355,6 +4330,18 @@ intel_dp_long_pulse(struct intel_connector 
> *intel_connector)
>  out:
>   if (status != connector_status_connected) {
>   intel_dp_unset_edid(intel_dp);
> +
> + /*
> +  * If we were in MST mode, and device is not there,
> +  * get out of MST mode
> +  */
> + if (intel_dp->is_mst) {
> + DRM_DEBUG_KMS("MST device may have disappeared %d vs 
> %d\n",
> +   intel_dp->is_mst, 
> intel_dp->mst_mgr.mst_state);
> + intel_dp->is_mst = false;
> + drm_dp_mst_topology_mgr_set_mst(_dp->mst_mgr,
> +