Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

2016-09-26 Thread Ben Widawsky 

On 16-09-15 17:30:10, Mika Kuoppala wrote:

Imre Deak  writes:


From: Ben Widawsky 

v2: (Imre)
- Access only subslices that are known to exist.
- Reset explictly the MCR selector to slice/sub-slice ID 0 after the
  readout.
- Use the subslice INSTDONE bits for the hangcheck/subunits-stuck
  detection too.
- Take the uncore lock for the MCR-select/subslice-readout sequence.

Signed-off-by: Ben Widawsky 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 14 --
 drivers/gpu/drm/i915/i915_gpu_error.c   | 76 ++---
 drivers/gpu/drm/i915/i915_irq.c | 25 ---
 drivers/gpu/drm/i915/i915_reg.h |  5 +++
 drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +-
 5 files changed, 125 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 45244f9..0f84165 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1281,6 +1281,9 @@ static void i915_instdone_info(struct drm_i915_private 
*dev_priv,
   struct seq_file *m,
   struct intel_instdone *instdone)
 {
+   int slice;
+   int subslice;
+
seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
   instdone->instdone);

@@ -1293,10 +1296,13 @@ static void i915_instdone_info(struct drm_i915_private 
*dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;

-   seq_printf(m, "\t\tSAMPLER_INSTDONE: 0x%08x\n",
-  instdone->sampler);
-   seq_printf(m, "\t\tROW_INSTDONE: 0x%08x\n",
-  instdone->row);
+   for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+   seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
+  slice, subslice, instdone->sampler[slice][subslice]);
+
+   for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+   seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
+  slice, subslice, instdone->row[slice][subslice]);
 }

 static int i915_hangcheck_info(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 80fe101..06d4309 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -231,6 +231,9 @@ static const char *hangcheck_action_to_str(enum 
intel_engine_hangcheck_action a)
 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 struct drm_i915_error_engine *ee)
 {
+   int slice;
+   int subslice;
+
err_printf(m, "  INSTDONE: 0x%08x\n",
   ee->instdone.instdone);

@@ -243,10 +246,15 @@ static void error_print_instdone(struct 
drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;

-   err_printf(m, "  SAMPLER_INSTDONE: 0x%08x\n",
-  ee->instdone.sampler);
-   err_printf(m, "  ROW_INSTDONE: 0x%08x\n",
-  ee->instdone.row);
+   for_each_instdone_slice_subslice(m->i915, slice, subslice)
+   err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
+  slice, subslice,
+  ee->instdone.sampler[slice][subslice]);
+
+   for_each_instdone_slice_subslice(m->i915, slice, subslice)
+   err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
+  slice, subslice,
+  ee->instdone.row[slice][subslice]);
 }

 static void error_print_engine(struct drm_i915_error_state_buf *m,
@@ -1534,12 +1542,52 @@ const char *i915_cache_level_str(struct 
drm_i915_private *i915, int type)
}
 }

+static inline uint32_t
+read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
+ int subslice, i915_reg_t reg)
+{
+   uint32_t mcr;
+   uint32_t ret;
+   enum forcewake_domains fw_domains;
+
+   fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
+   FW_REG_READ);
+   fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+GEN8_MCR_SELECTOR,
+FW_REG_READ | 
FW_REG_WRITE);
+
+   spin_lock_irq(_priv->uncore.lock);
+   intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+
+   mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
+   /*
+* The HW expects the slice and sublice selectors to be reset to 0
+* after reading out the registers.
+*/
+   WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
+   mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+   mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+   I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

2016-09-20 Thread Mika Kuoppala 
Imre Deak  writes:

> From: Ben Widawsky 
>
> v2: (Imre)
> - Access only subslices that are known to exist.
> - Reset explictly the MCR selector to slice/sub-slice ID 0 after the
>   readout.
> - Use the subslice INSTDONE bits for the hangcheck/subunits-stuck
>   detection too.
> - Take the uncore lock for the MCR-select/subslice-readout sequence.
>
> Signed-off-by: Ben Widawsky 
> Signed-off-by: Imre Deak 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 14 --
>  drivers/gpu/drm/i915/i915_gpu_error.c   | 76 
> ++---
>  drivers/gpu/drm/i915/i915_irq.c | 25 ---
>  drivers/gpu/drm/i915/i915_reg.h |  5 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +-
>  5 files changed, 125 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 45244f9..0f84165 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1281,6 +1281,9 @@ static void i915_instdone_info(struct drm_i915_private 
> *dev_priv,
>  struct seq_file *m,
>  struct intel_instdone *instdone)
>  {
> + int slice;
> + int subslice;
> +
>   seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
>  instdone->instdone);
>  
> @@ -1293,10 +1296,13 @@ static void i915_instdone_info(struct 
> drm_i915_private *dev_priv,
>   if (INTEL_GEN(dev_priv) <= 6)
>   return;
>  
> - seq_printf(m, "\t\tSAMPLER_INSTDONE: 0x%08x\n",
> -instdone->sampler);
> - seq_printf(m, "\t\tROW_INSTDONE: 0x%08x\n",
> -instdone->row);
> + for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> + seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice, instdone->sampler[slice][subslice]);
> +
> + for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> + seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice, instdone->row[slice][subslice]);
>  }
>  
>  static int i915_hangcheck_info(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 80fe101..06d4309 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -231,6 +231,9 @@ static const char *hangcheck_action_to_str(enum 
> intel_engine_hangcheck_action a)
>  static void error_print_instdone(struct drm_i915_error_state_buf *m,
>struct drm_i915_error_engine *ee)
>  {
> + int slice;
> + int subslice;
> +
>   err_printf(m, "  INSTDONE: 0x%08x\n",
>  ee->instdone.instdone);
>  
> @@ -243,10 +246,15 @@ static void error_print_instdone(struct 
> drm_i915_error_state_buf *m,
>   if (INTEL_GEN(m->i915) <= 6)
>   return;
>  
> - err_printf(m, "  SAMPLER_INSTDONE: 0x%08x\n",
> -ee->instdone.sampler);
> - err_printf(m, "  ROW_INSTDONE: 0x%08x\n",
> -ee->instdone.row);
> + for_each_instdone_slice_subslice(m->i915, slice, subslice)
> + err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice,
> +ee->instdone.sampler[slice][subslice]);
> +
> + for_each_instdone_slice_subslice(m->i915, slice, subslice)
> + err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice,
> +ee->instdone.row[slice][subslice]);
>  }
>  
>  static void error_print_engine(struct drm_i915_error_state_buf *m,
> @@ -1534,12 +1542,52 @@ const char *i915_cache_level_str(struct 
> drm_i915_private *i915, int type)
>   }
>  }
>  
> +static inline uint32_t
> +read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> +   int subslice, i915_reg_t reg)
> +{
> + uint32_t mcr;
> + uint32_t ret;
> + enum forcewake_domains fw_domains;
> +
> + fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
> + FW_REG_READ);
> + fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> +  GEN8_MCR_SELECTOR,
> +  FW_REG_READ | 
> FW_REG_WRITE);
> +
> + spin_lock_irq(_priv->uncore.lock);
> + intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> +
> + mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> + /*
> +  * The HW expects the slice and sublice selectors to be reset to 0
> +  * after reading out the registers.
> +  */
> + WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
> + mcr &=

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

2016-09-15 Thread Imre Deak 
On Thu, 2016-09-15 at 17:30 +0300, Mika Kuoppala wrote:
> Imre Deak  writes:
> 
> > From: Ben Widawsky 
> > 
> > v2: (Imre)
> > - Access only subslices that are known to exist.
> > - Reset explictly the MCR selector to slice/sub-slice ID 0 after the
> >   readout.
> > - Use the subslice INSTDONE bits for the hangcheck/subunits-stuck
> >   detection too.
> > - Take the uncore lock for the MCR-select/subslice-readout sequence.
> > 
> > Signed-off-by: Ben Widawsky 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 14 --
> >  drivers/gpu/drm/i915/i915_gpu_error.c   | 76 
> > ++---
> >  drivers/gpu/drm/i915/i915_irq.c | 25 ---
> >  drivers/gpu/drm/i915/i915_reg.h |  5 +++
> >  drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +-
> >  5 files changed, 125 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> > b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 45244f9..0f84165 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1281,6 +1281,9 @@ static void i915_instdone_info(struct 
> > drm_i915_private *dev_priv,
> >        struct seq_file *m,
> >        struct intel_instdone *instdone)
> >  {
> > +   int slice;
> > +   int subslice;
> > +
> >     seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
> >        instdone->instdone);
> >  
> > @@ -1293,10 +1296,13 @@ static void i915_instdone_info(struct 
> > drm_i915_private *dev_priv,
> >     if (INTEL_GEN(dev_priv) <= 6)
> >     return;
> >  
> > -   seq_printf(m, "\t\tSAMPLER_INSTDONE: 0x%08x\n",
> > -      instdone->sampler);
> > -   seq_printf(m, "\t\tROW_INSTDONE: 0x%08x\n",
> > -      instdone->row);
> > +   for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> > +   seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> > +      slice, subslice, instdone->sampler[slice][subslice]);
> > +
> > +   for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> > +   seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
> > +      slice, subslice, instdone->row[slice][subslice]);
> >  }
> >  
> >  static int i915_hangcheck_info(struct seq_file *m, void *unused)
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index 80fe101..06d4309 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -231,6 +231,9 @@ static const char *hangcheck_action_to_str(enum 
> > intel_engine_hangcheck_action a)
> >  static void error_print_instdone(struct drm_i915_error_state_buf *m,
> >      struct drm_i915_error_engine *ee)
> >  {
> > +   int slice;
> > +   int subslice;
> > +
> >     err_printf(m, "  INSTDONE: 0x%08x\n",
> >        ee->instdone.instdone);
> >  
> > @@ -243,10 +246,15 @@ static void error_print_instdone(struct 
> > drm_i915_error_state_buf *m,
> >     if (INTEL_GEN(m->i915) <= 6)
> >     return;
> >  
> > -   err_printf(m, "  SAMPLER_INSTDONE: 0x%08x\n",
> > -      ee->instdone.sampler);
> > -   err_printf(m, "  ROW_INSTDONE: 0x%08x\n",
> > -      ee->instdone.row);
> > +   for_each_instdone_slice_subslice(m->i915, slice, subslice)
> > +   err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> > +      slice, subslice,
> > +      ee->instdone.sampler[slice][subslice]);
> > +
> > +   for_each_instdone_slice_subslice(m->i915, slice, subslice)
> > +   err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
> > +      slice, subslice,
> > +      ee->instdone.row[slice][subslice]);
> >  }
> >  
> >  static void error_print_engine(struct drm_i915_error_state_buf *m,
> > @@ -1534,12 +1542,52 @@ const char *i915_cache_level_str(struct 
> > drm_i915_private *i915, int type)
> >     }
> >  }
> >  
> > +static inline uint32_t
> > +read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> > +     int subslice, i915_reg_t reg)
> > +{
> > +   uint32_t mcr;
> > +   uint32_t ret;
> > +   enum forcewake_domains fw_domains;
> > +
> > +   fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
> > +   FW_REG_READ);
> > +   fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> > +    GEN8_MCR_SELECTOR,
> > +    FW_REG_READ | 
> > FW_REG_WRITE);
> > +
> > +   spin_lock_irq(_priv->uncore.lock);
> > +   intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> > +
> > +   mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> > +   /*
> > +    * The HW expects the slice and sublice selectors to be reset to 0
> > +    * after

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Try to print INSTDONE bits for all slice/subslice

2016-09-15 Thread Mika Kuoppala 
Imre Deak  writes:

> From: Ben Widawsky 
>
> v2: (Imre)
> - Access only subslices that are known to exist.
> - Reset explictly the MCR selector to slice/sub-slice ID 0 after the
>   readout.
> - Use the subslice INSTDONE bits for the hangcheck/subunits-stuck
>   detection too.
> - Take the uncore lock for the MCR-select/subslice-readout sequence.
>
> Signed-off-by: Ben Widawsky 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 14 --
>  drivers/gpu/drm/i915/i915_gpu_error.c   | 76 
> ++---
>  drivers/gpu/drm/i915/i915_irq.c | 25 ---
>  drivers/gpu/drm/i915/i915_reg.h |  5 +++
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 23 +-
>  5 files changed, 125 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 45244f9..0f84165 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1281,6 +1281,9 @@ static void i915_instdone_info(struct drm_i915_private 
> *dev_priv,
>  struct seq_file *m,
>  struct intel_instdone *instdone)
>  {
> + int slice;
> + int subslice;
> +
>   seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
>  instdone->instdone);
>  
> @@ -1293,10 +1296,13 @@ static void i915_instdone_info(struct 
> drm_i915_private *dev_priv,
>   if (INTEL_GEN(dev_priv) <= 6)
>   return;
>  
> - seq_printf(m, "\t\tSAMPLER_INSTDONE: 0x%08x\n",
> -instdone->sampler);
> - seq_printf(m, "\t\tROW_INSTDONE: 0x%08x\n",
> -instdone->row);
> + for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> + seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice, instdone->sampler[slice][subslice]);
> +
> + for_each_instdone_slice_subslice(dev_priv, slice, subslice)
> + seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice, instdone->row[slice][subslice]);
>  }
>  
>  static int i915_hangcheck_info(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 80fe101..06d4309 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -231,6 +231,9 @@ static const char *hangcheck_action_to_str(enum 
> intel_engine_hangcheck_action a)
>  static void error_print_instdone(struct drm_i915_error_state_buf *m,
>struct drm_i915_error_engine *ee)
>  {
> + int slice;
> + int subslice;
> +
>   err_printf(m, "  INSTDONE: 0x%08x\n",
>  ee->instdone.instdone);
>  
> @@ -243,10 +246,15 @@ static void error_print_instdone(struct 
> drm_i915_error_state_buf *m,
>   if (INTEL_GEN(m->i915) <= 6)
>   return;
>  
> - err_printf(m, "  SAMPLER_INSTDONE: 0x%08x\n",
> -ee->instdone.sampler);
> - err_printf(m, "  ROW_INSTDONE: 0x%08x\n",
> -ee->instdone.row);
> + for_each_instdone_slice_subslice(m->i915, slice, subslice)
> + err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice,
> +ee->instdone.sampler[slice][subslice]);
> +
> + for_each_instdone_slice_subslice(m->i915, slice, subslice)
> + err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
> +slice, subslice,
> +ee->instdone.row[slice][subslice]);
>  }
>  
>  static void error_print_engine(struct drm_i915_error_state_buf *m,
> @@ -1534,12 +1542,52 @@ const char *i915_cache_level_str(struct 
> drm_i915_private *i915, int type)
>   }
>  }
>  
> +static inline uint32_t
> +read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
> +   int subslice, i915_reg_t reg)
> +{
> + uint32_t mcr;
> + uint32_t ret;
> + enum forcewake_domains fw_domains;
> +
> + fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
> + FW_REG_READ);
> + fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> +  GEN8_MCR_SELECTOR,
> +  FW_REG_READ | 
> FW_REG_WRITE);
> +
> + spin_lock_irq(_priv->uncore.lock);
> + intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
> +
> + mcr = I915_READ_FW(GEN8_MCR_SELECTOR);
> + /*
> +  * The HW expects the slice and sublice selectors to be reset to 0
> +  * after reading out the registers.
> +  */
> + WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
> + mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
> + mcr |=