Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter
On Fri, Mar 06, 2020 at 12:22:09AM +, Souza, Jose wrote: > On Wed, 2020-02-19 at 20:52 +0200, Ville Syrjälä wrote: > > On Wed, Feb 19, 2020 at 06:37:27PM +, Souza, Jose wrote: > > > On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote: > > > > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza > > > > wrote: > > > > > Most of the kms_frontbuffer_tracking tests disables the feature > > > > > being > > > > > tested, draw, get the CRC then enable the feature, draw again, > > > > > get > > > > > the > > > > > CRC and check if it matches. > > > > > Some times it is able to do that with a fastset, so > > > > > intel_pre_plane_update() is executed but > > > > > intel_fbc_can_flip_nuke() > > > > > was > > > > > not checking if FBC is now enabled in this CRTC leaving FBC > > > > > active > > > > > and > > > > > causing the warning bellow in __intel_fbc_disable() > > > > > > > > > > [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri- > > > > > indfb- > > > > > multidraw > > > > > Setting dangerous option enable_fbc - tainting kernel > > > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting > > > > > PSR > > > > > debug to f > > > > > i915 :00:02.0: [drm:intel_psr_debug_set [i915]] Invalid > > > > > debug > > > > > mask f > > > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting > > > > > PSR > > > > > debug to 1 > > > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] > > > > > [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of > > > > > EDID > > > > > bpp 24, requested bpp 36, max platform bpp 36 > > > > > [drm:intel_dp_compute_config [i915]] DP link computation with > > > > > max > > > > > lane count 2 max rate 27 max bpp 24 pixel clock 138120KHz > > > > > [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > > > > > [drm:intel_dp_compute_config [i915]] DP lane count 2 clock > > > > > 27 > > > > > bpp 24 > > > > > [drm:intel_dp_compute_config [i915]] DP link rate required > > > > > 414360 > > > > > available 54 > > > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: > > > > > 24, > > > > > pipe bpp: 24, dithering: 0 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > [CRTC:91:pipe A] enable: yes [fastset] > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] active: > > > > > yes, > > > > > output_types: EDP (0x100), output format: RGB > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: > > > > > lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, > > > > > link_n: > > > > > 524288, tu: 64 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] audio: > > > > > 0, > > > > > infoframes: 0, infoframes enabled: 0x0 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > requested > > > > > mode: > > > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > > > > > 138120 > > > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted > > > > > mode: > > > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > > > > > 138120 > > > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > > > [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 > > > > > 1968 > > > > > 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] port > > > > > clock: > > > > > 27, pipe src size: 1920x1080, pixel rate 138120 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > linetime: > > > > > 119, ips linetime: 0 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > num_scalers: > > > > > 2, scaler_users: 0x0, scaler_id: -1 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] pch > > > > > pfit: > > > > > pos: 0x, size: 0x, disabled, force thru: no > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, > > > > > double wide: 0 > > > > > [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: > > > > > 0x1c001a5, > > > > > cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: > > > > > 0x0, > > > > > mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, > > > > > mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, > > > > > mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > csc_mode: > > > > > 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] MST > > > > > master > > > > > transcoder: > > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > > [PLANE:31:plane 1A] fb: [FB:262] 1920x1080 format = XR24 > > > > > little- > > > > > endian (0x34325258), visible: yes > > > > > i915 :00:02.0: [drm:intel_dump_p
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter
On Wed, 2020-02-19 at 20:52 +0200, Ville Syrjälä wrote: > On Wed, Feb 19, 2020 at 06:37:27PM +, Souza, Jose wrote: > > On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote: > > > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza > > > wrote: > > > > Most of the kms_frontbuffer_tracking tests disables the feature > > > > being > > > > tested, draw, get the CRC then enable the feature, draw again, > > > > get > > > > the > > > > CRC and check if it matches. > > > > Some times it is able to do that with a fastset, so > > > > intel_pre_plane_update() is executed but > > > > intel_fbc_can_flip_nuke() > > > > was > > > > not checking if FBC is now enabled in this CRTC leaving FBC > > > > active > > > > and > > > > causing the warning bellow in __intel_fbc_disable() > > > > > > > > [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri- > > > > indfb- > > > > multidraw > > > > Setting dangerous option enable_fbc - tainting kernel > > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting > > > > PSR > > > > debug to f > > > > i915 :00:02.0: [drm:intel_psr_debug_set [i915]] Invalid > > > > debug > > > > mask f > > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting > > > > PSR > > > > debug to 1 > > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] > > > > [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of > > > > EDID > > > > bpp 24, requested bpp 36, max platform bpp 36 > > > > [drm:intel_dp_compute_config [i915]] DP link computation with > > > > max > > > > lane count 2 max rate 27 max bpp 24 pixel clock 138120KHz > > > > [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > > > > [drm:intel_dp_compute_config [i915]] DP lane count 2 clock > > > > 27 > > > > bpp 24 > > > > [drm:intel_dp_compute_config [i915]] DP link rate required > > > > 414360 > > > > available 54 > > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: > > > > 24, > > > > pipe bpp: 24, dithering: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > [CRTC:91:pipe A] enable: yes [fastset] > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] active: > > > > yes, > > > > output_types: EDP (0x100), output format: RGB > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: > > > > lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, > > > > link_n: > > > > 524288, tu: 64 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] audio: > > > > 0, > > > > infoframes: 0, infoframes enabled: 0x0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > requested > > > > mode: > > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > > > > 138120 > > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted > > > > mode: > > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > > > > 138120 > > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > > [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 > > > > 1968 > > > > 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] port > > > > clock: > > > > 27, pipe src size: 1920x1080, pixel rate 138120 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > linetime: > > > > 119, ips linetime: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > num_scalers: > > > > 2, scaler_users: 0x0, scaler_id: -1 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] pch > > > > pfit: > > > > pos: 0x, size: 0x, disabled, force thru: no > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, > > > > double wide: 0 > > > > [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: > > > > 0x1c001a5, > > > > cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: > > > > 0x0, > > > > mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, > > > > mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, > > > > mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > csc_mode: > > > > 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] MST > > > > master > > > > transcoder: > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > > [PLANE:31:plane 1A] fb: [FB:262] 1920x1080 format = XR24 > > > > little- > > > > endian (0x34325258), visible: yes > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] rotatio > > > > n: 0x1, scaler: -1 > > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] src: > > > > 1920.00x1080.00+0.00+0.00 dst: 1920x1080+0+0 > > > > i915 :00:02.0: [drm:intel_psr_disable_locked [i915]] > > > > Disabling > > >
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter
On Wed, Feb 19, 2020 at 06:37:27PM +, Souza, Jose wrote: > On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote: > > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza > > wrote: > > > Most of the kms_frontbuffer_tracking tests disables the feature > > > being > > > tested, draw, get the CRC then enable the feature, draw again, get > > > the > > > CRC and check if it matches. > > > Some times it is able to do that with a fastset, so > > > intel_pre_plane_update() is executed but intel_fbc_can_flip_nuke() > > > was > > > not checking if FBC is now enabled in this CRTC leaving FBC active > > > and > > > causing the warning bellow in __intel_fbc_disable() > > > > > > [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri-indfb- > > > multidraw > > > Setting dangerous option enable_fbc - tainting kernel > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR > > > debug to f > > > i915 :00:02.0: [drm:intel_psr_debug_set [i915]] Invalid debug > > > mask f > > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR > > > debug to 1 > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] > > > [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID > > > bpp 24, requested bpp 36, max platform bpp 36 > > > [drm:intel_dp_compute_config [i915]] DP link computation with max > > > lane count 2 max rate 27 max bpp 24 pixel clock 138120KHz > > > [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > > > [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 27 > > > bpp 24 > > > [drm:intel_dp_compute_config [i915]] DP link rate required 414360 > > > available 54 > > > i915 :00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, > > > pipe bpp: 24, dithering: 0 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > [CRTC:91:pipe A] enable: yes [fastset] > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, > > > output_types: EDP (0x100), output format: RGB > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: > > > lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: > > > 524288, tu: 64 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, > > > infoframes: 0, infoframes enabled: 0x0 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] requested > > > mode: > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted > > > mode: > > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 > > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > > [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 > > > 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: > > > 27, pipe src size: 1920x1080, pixel rate 138120 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: > > > 119, ips linetime: 0 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: > > > 2, scaler_users: 0x0, scaler_id: -1 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: > > > pos: 0x, size: 0x, disabled, force thru: no > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, > > > double wide: 0 > > > [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, > > > cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, > > > mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, > > > mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, > > > mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: > > > 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] MST master > > > transcoder: > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > > [PLANE:31:plane 1A] fb: [FB:262] 1920x1080 format = XR24 little- > > > endian (0x34325258), visible: yes > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]]rotatio > > > n: 0x1, scaler: -1 > > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]]src: > > > 1920.00x1080.00+0.00+0.00 dst: 1920x1080+0+0 > > > i915 :00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling > > > PSR1 > > > i915 :00:02.0: [drm:intel_ddi_update_pipe [i915]] Panel doesn't > > > support DRRS > > > [ cut here ] > > > i915 :00:02.0: drm_WARN_ON(fbc->active) > > > WARNING: CPU: 4 PID: 1175 at > > > drivers/gpu/drm/i915/display/intel_fbc.c:973 > > > __intel_fbc_disable+0xa5/0x130 [i915] > > > Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek > > > snd_hda_codec_generic i915 mei_hdcp x86_pkg_temp_thermal core
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter
On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote: > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza > wrote: > > Most of the kms_frontbuffer_tracking tests disables the feature > > being > > tested, draw, get the CRC then enable the feature, draw again, get > > the > > CRC and check if it matches. > > Some times it is able to do that with a fastset, so > > intel_pre_plane_update() is executed but intel_fbc_can_flip_nuke() > > was > > not checking if FBC is now enabled in this CRTC leaving FBC active > > and > > causing the warning bellow in __intel_fbc_disable() > > > > [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri-indfb- > > multidraw > > Setting dangerous option enable_fbc - tainting kernel > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR > > debug to f > > i915 :00:02.0: [drm:intel_psr_debug_set [i915]] Invalid debug > > mask f > > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR > > debug to 1 > > i915 :00:02.0: [drm:intel_atomic_check [i915]] > > [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID > > bpp 24, requested bpp 36, max platform bpp 36 > > [drm:intel_dp_compute_config [i915]] DP link computation with max > > lane count 2 max rate 27 max bpp 24 pixel clock 138120KHz > > [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > > [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 27 > > bpp 24 > > [drm:intel_dp_compute_config [i915]] DP link rate required 414360 > > available 54 > > i915 :00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, > > pipe bpp: 24, dithering: 0 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > [CRTC:91:pipe A] enable: yes [fastset] > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, > > output_types: EDP (0x100), output format: RGB > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: > > lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: > > 524288, tu: 64 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, > > infoframes: 0, infoframes enabled: 0x0 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] requested > > mode: > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted > > mode: > > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 > > 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa > > [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 > > 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: > > 27, pipe src size: 1920x1080, pixel rate 138120 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: > > 119, ips linetime: 0 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: > > 2, scaler_users: 0x0, scaler_id: -1 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: > > pos: 0x, size: 0x, disabled, force thru: no > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, > > double wide: 0 > > [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, > > cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, > > mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, > > mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, > > mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: > > 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] MST master > > transcoder: > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] > > [PLANE:31:plane 1A] fb: [FB:262] 1920x1080 format = XR24 little- > > endian (0x34325258), visible: yes > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] rotatio > > n: 0x1, scaler: -1 > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] src: > > 1920.00x1080.00+0.00+0.00 dst: 1920x1080+0+0 > > i915 :00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling > > PSR1 > > i915 :00:02.0: [drm:intel_ddi_update_pipe [i915]] Panel doesn't > > support DRRS > > [ cut here ] > > i915 :00:02.0: drm_WARN_ON(fbc->active) > > WARNING: CPU: 4 PID: 1175 at > > drivers/gpu/drm/i915/display/intel_fbc.c:973 > > __intel_fbc_disable+0xa5/0x130 [i915] > > Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek > > snd_hda_codec_generic i915 mei_hdcp x86_pkg_temp_thermal coretemp > > crct10dif_pclmul snd_hda_intel crc32_pclmul snd_intel_dspcfg > > snd_hda_codec ghash_clmulni_intel snd_hwdep snd_hda_core cdc_ether > > e1000e usbnet mii snd_pcm ptp mei_me pps_core mei thunderbolt > > intel_lpss_pci prime_numbers > > C
Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Deactive FBC in fastsets when disabled by parameter
On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza wrote: > Most of the kms_frontbuffer_tracking tests disables the feature being > tested, draw, get the CRC then enable the feature, draw again, get the > CRC and check if it matches. > Some times it is able to do that with a fastset, so > intel_pre_plane_update() is executed but intel_fbc_can_flip_nuke() was > not checking if FBC is now enabled in this CRTC leaving FBC active and > causing the warning bellow in __intel_fbc_disable() > > [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri-indfb-multidraw > Setting dangerous option enable_fbc - tainting kernel > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR debug to f > i915 :00:02.0: [drm:intel_psr_debug_set [i915]] Invalid debug mask f > i915 :00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR debug to 1 > i915 :00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] > Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max > platform bpp 36 > [drm:intel_dp_compute_config [i915]] DP link computation with max lane count > 2 max rate 27 max bpp 24 pixel clock 138120KHz > [drm:intel_dp_compute_config [i915]] Force DSC en = 0 > [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 27 bpp 24 > [drm:intel_dp_compute_config [i915]] DP link rate required 414360 available > 54 > i915 :00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: > 24, dithering: 0 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:91:pipe A] > enable: yes [fastset] > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, > output_types: EDP (0x100), output format: RGB > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, > pipe bpp: 24, dithering: 0 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; > gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: > 0, infoframes enabled: 0x0 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode: > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 1920 1968 > 2018 2052 1080 1084 1086 1122 0x48 0xa > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode: > [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 1920 1968 > 2018 2052 1080 1084 1086 1122 0x48 0xa > [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 > 1080 1084 1086 1122, type: 0x48 flags: 0xa > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 27, > pipe src size: 1920x1080, pixel rate 138120 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 119, ips > linetime: 0 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, > scaler_users: 0x0, scaler_id: -1 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: > 0x, size: 0x, disabled, force thru: no > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 > [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: > 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: > 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: > 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 > gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: > > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] > fb: [FB:262] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]]rotation: 0x1, > scaler: -1 > i915 :00:02.0: [drm:intel_dump_pipe_config [i915]]src: > 1920.00x1080.00+0.00+0.00 dst: 1920x1080+0+0 > i915 :00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR1 > i915 :00:02.0: [drm:intel_ddi_update_pipe [i915]] Panel doesn't support > DRRS > [ cut here ] > i915 :00:02.0: drm_WARN_ON(fbc->active) > WARNING: CPU: 4 PID: 1175 at drivers/gpu/drm/i915/display/intel_fbc.c:973 > __intel_fbc_disable+0xa5/0x130 [i915] > Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek > snd_hda_codec_generic i915 mei_hdcp x86_pkg_temp_thermal coretemp > crct10dif_pclmul snd_hda_intel crc32_pclmul snd_intel_dspcfg snd_hda_codec > ghash_clmulni_intel snd_hwdep snd_hda_core cdc_ether e1000e usbnet mii > snd_pcm ptp mei_me pps_core mei thunderbolt intel_lpss_pci prime_numbers > CPU: 4 PID: 1175 Comm: kms_frontbuffer Tainted: G U > 5.5.0-CI-Trybot_5651+ #1 > Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 > SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3234.A01.1906141750 06/14/2019 > RIP: 0010:__in
