Re: [Intel-gfx] [PATCH v4] drm/i915: Show IPEIR and IPEHR in the engine dump

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-18 12:58:51)
> 
> On 18/12/2017 12:39, Chris Wilson wrote:
> > A useful bit of information for inspecting GPU stalls from
> > intel_engine_dump() are the error registers, IPEIR and IPEHR.
> > 
> > v2: Fixup gen changes in register offsets (Tvrtko)
> > v3: Old FADDR location as well
> > v4: Use I915_READ64_2x32
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > Cc: Joonas Lahtinen 
> > Cc: Tvrtko Ursulin 
> > ---
> >   drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++
> >   1 file changed, 18 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index 510e0bc3a377..b4807497e92d 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs 
> > *engine,
> >   addr = intel_engine_get_last_batch_head(engine);
> >   drm_printf(m, "BBADDR: 0x%08x_%08x\n",
> >  upper_32_bits(addr), lower_32_bits(addr));
> > + if (INTEL_GEN(dev_priv) >= 8)
> > + addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
> > + RING_DMA_FADD_UDW(engine->mmio_base));
> > + else if (INTEL_GEN(dev_priv) >= 4)
> > + addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
> > + else
> > + addr = I915_READ(DMA_FADD_I8XX);
> > + drm_printf(m, "DMA_FADDR: 0x%08x_%08x\n",
> > +upper_32_bits(addr), lower_32_bits(addr));
> > + if (INTEL_GEN(dev_priv) >= 4) {
> > + drm_printf(m, "IPEIR: 0x%08x\n",
> > +I915_READ(RING_IPEIR(engine->mmio_base)));
> > + drm_printf(m, "IPEHR: 0x%08x\n",
> > +I915_READ(RING_IPEHR(engine->mmio_base)));
> > + } else {
> > + drm_printf(m, "IPEIR: 0x%08x\n", I915_READ(IPEIR));
> > + drm_printf(m, "IPEHR: 0x%08x\n", I915_READ(IPEHR));
> > + }
> >   
> >   if (HAS_EXECLISTS(dev_priv)) {
> >   const u32 *hws = 
> > >status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> > 
> 
> Reviewed-by: Tvrtko Ursulin 

Thanks for the review, lots of fixes in such a small patch.
Pushed, so just the selftest for per-engine resets remaining, which I
hope Michel will pick up later.
-Chris
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Re: [Intel-gfx] [PATCH v4] drm/i915: Show IPEIR and IPEHR in the engine dump

[Tvrtko Ursulin]

On 18/12/2017 12:39, Chris Wilson wrote:

A useful bit of information for inspecting GPU stalls from
intel_engine_dump() are the error registers, IPEIR and IPEHR.

v2: Fixup gen changes in register offsets (Tvrtko)
v3: Old FADDR location as well
v4: Use I915_READ64_2x32

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
  drivers/gpu/drm/i915/intel_engine_cs.c | 18 ++
  1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 510e0bc3a377..b4807497e92d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1757,6 +1757,24 @@ void intel_engine_dump(struct intel_engine_cs *engine,
addr = intel_engine_get_last_batch_head(engine);
drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
   upper_32_bits(addr), lower_32_bits(addr));
+   if (INTEL_GEN(dev_priv) >= 8)
+   addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
+   RING_DMA_FADD_UDW(engine->mmio_base));
+   else if (INTEL_GEN(dev_priv) >= 4)
+   addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
+   else
+   addr = I915_READ(DMA_FADD_I8XX);
+   drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
+  upper_32_bits(addr), lower_32_bits(addr));
+   if (INTEL_GEN(dev_priv) >= 4) {
+   drm_printf(m, "\tIPEIR: 0x%08x\n",
+  I915_READ(RING_IPEIR(engine->mmio_base)));
+   drm_printf(m, "\tIPEHR: 0x%08x\n",
+  I915_READ(RING_IPEHR(engine->mmio_base)));
+   } else {
+   drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(IPEIR));
+   drm_printf(m, "\tIPEHR: 0x%08x\n", I915_READ(IPEHR));
+   }
  
  	if (HAS_EXECLISTS(dev_priv)) {

const u32 *hws = 
>status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];



Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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