Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
On Wed, Jun 05, 2019 at 04:01:05PM +0200, Maarten Lankhorst wrote: > Op 31-05-2019 om 15:05 schreef Ville Syrjälä: > > On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote: > >> == Series Details == > >> > >> Series: series starting with [01/10] drm/i915: Add windowing for primary > >> planes on gen2/3 and chv > >> URL : https://patchwork.freedesktop.org/series/61345/ > >> State : failure > >> > >> == Summary == > >> > >> CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full > >> > >> > >> Summary > >> --- > >> > >> **FAILURE** > >> > >> Serious unknown changes coming with Patchwork_13133_full absolutely need > >> to be > >> verified manually. > >> > >> If you think the reported changes have nothing to do with the changes > >> introduced in Patchwork_13133_full, please notify your bug team to allow > >> them > >> to document this new failure mode, which will reduce false positives in > >> CI. > >> > >> > >> > >> Possible new issues > >> --- > >> > >> Here are the unknown changes that may have been introduced in > >> Patchwork_13133_full: > >> > >> ### IGT changes ### > >> > >> Possible regressions > >> > >> * igt@kms_plane@pixel-format-pipe-a-planes: > >> - shard-glk: [PASS][1] -> [FAIL][2] > >>[1]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html > >>[2]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html > > <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": > > 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 > > ... > > <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to > > 79200 kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage > > level 4 > > ... > > <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported > > pixel clock with scaling exceeded > > > > Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are > > exceeding. We'd need some way to bump the cdclk for this case, but > > the kernel will only do that for modesets, and it won't account for > > that 8/9 factor. Not sure there is a great way to handle these sorts > > of cases. > > > >> * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: > >> - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues > >>[3]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > >>[4]: > >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > > <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling > > of plane > > <7> [1749.831620] [drm:drm_rect_debug_print] src: > > 8.00x8.00+0.00+0.00 > > <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0 > > > > Not quite sure what's going on here. Unfortunately the debugs don't have > > enough information to see what's going on. > > For first 6 patches > > Reviewed-by: Maarten Lankhorst Thanks. > > What happens on < gen9 btw with half float support? > > Enabling patches look sane, but worried about hw coverage. > > So if you are sure it works on add my r-b on those too. But I would like to have no regressions so have to > get gen9 fixed first before pushing. :) We do have some missing checks for the cdclk vs. fp16 case on pre-gen9, as well as missing similar cdclk vs. scaling checks. I think I have some kind of plan to remedy that. And I can probably tweak that into bumping the cdclk for fp16 as well (assuming a modeset is allowed for the commit in question of course). -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
On Fri, May 31, 2019 at 04:05:51PM +0300, Ville Syrjälä wrote: > On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [01/10] drm/i915: Add windowing for primary > > planes on gen2/3 and chv > > URL : https://patchwork.freedesktop.org/series/61345/ > > State : failure > > > > == Summary == > > > > CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full > > > > > > Summary > > --- > > > > **FAILURE** > > > > Serious unknown changes coming with Patchwork_13133_full absolutely need > > to be > > verified manually. > > > > If you think the reported changes have nothing to do with the changes > > introduced in Patchwork_13133_full, please notify your bug team to allow > > them > > to document this new failure mode, which will reduce false positives in > > CI. > > > > > > > > Possible new issues > > --- > > > > Here are the unknown changes that may have been introduced in > > Patchwork_13133_full: > > > > ### IGT changes ### > > > > Possible regressions > > > > * igt@kms_plane@pixel-format-pipe-a-planes: > > - shard-glk: [PASS][1] -> [FAIL][2] > >[1]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html > >[2]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html > > <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 > 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5 > ... > <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200 > kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage > level 4 > ... > <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported > pixel clock with scaling exceeded > > Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are > exceeding. We'd need some way to bump the cdclk for this case, but > the kernel will only do that for modesets, and it won't account for > that 8/9 factor. Not sure there is a great way to handle these sorts > of cases. > > > > > * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format: > > - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues > >[3]: > > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > >[4]: > > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html > > <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling > of plane > <7> [1749.831620] [drm:drm_rect_debug_print] src: > 8.00x8.00+0.00+0.00 > <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0 > > Not quite sure what's going on here. Unfortunately the debugs don't have > enough information to see what's going on. Doh. That's obviously the "no scaling with fp16" hardware limitation kicking in. I'll need to adjust the test somehow to make it skip fp16 on these platforms. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
Op 31-05-2019 om 15:05 schreef Ville Syrjälä:
> On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote:
>> == Series Details ==
>>
>> Series: series starting with [01/10] drm/i915: Add windowing for primary
>> planes on gen2/3 and chv
>> URL : https://patchwork.freedesktop.org/series/61345/
>> State : failure
>>
>> == Summary ==
>>
>> CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full
>>
>>
>> Summary
>> ---
>>
>> **FAILURE**
>>
>> Serious unknown changes coming with Patchwork_13133_full absolutely need
>> to be
>> verified manually.
>>
>> If you think the reported changes have nothing to do with the changes
>> introduced in Patchwork_13133_full, please notify your bug team to allow
>> them
>> to document this new failure mode, which will reduce false positives in CI.
>>
>>
>>
>> Possible new issues
>> ---
>>
>> Here are the unknown changes that may have been introduced in
>> Patchwork_13133_full:
>>
>> ### IGT changes ###
>>
>> Possible regressions
>>
>> * igt@kms_plane@pixel-format-pipe-a-planes:
>> - shard-glk: [PASS][1] -> [FAIL][2]
>>[1]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html
>>[2]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html
> <7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60
> 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
> ...
> <7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200
> kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage
> level 4
> ...
> <7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported
> pixel clock with scaling exceeded
>
> Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are
> exceeding. We'd need some way to bump the cdclk for this case, but
> the kernel will only do that for modesets, and it won't account for
> that 8/9 factor. Not sure there is a great way to handle these sorts
> of cases.
>
>> * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
>> - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues
>>[3]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html
>>[4]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html
> <7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling
> of plane
> <7> [1749.831620] [drm:drm_rect_debug_print] src:
> 8.00x8.00+0.00+0.00
> <7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0
>
> Not quite sure what's going on here. Unfortunately the debugs don't have
> enough information to see what's going on.
For first 6 patches
Reviewed-by: Maarten Lankhorst
What happens on < gen9 btw with half float support?
Enabling patches look sane, but worried about hw coverage.
So if you are sure it works on >
>> Suppressed
>>
>> The following results come from untrusted machines, tests, or statuses.
>> They do not affect the overall result.
>>
>> * igt@gem_workarounds@suspend-resume-context:
>> - {shard-iclb}: [PASS][5] -> [FAIL][6] +1 similar issue
>>[5]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-iclb3/igt@gem_workarou...@suspend-resume-context.html
>>[6]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-iclb2/igt@gem_workarou...@suspend-resume-context.html
>>
>>
>> Known issues
>>
>>
>> Here are the changes found in Patchwork_13133_full that come from known
>> issues:
>>
>> ### IGT changes ###
>>
>> Issues hit
>>
>> * igt@gem_ctx_switch@basic-all-heavy:
>> - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540])
>>[7]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-hsw5/igt@gem_ctx_swi...@basic-all-heavy.html
>>[8]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-hsw1/igt@gem_ctx_swi...@basic-all-heavy.html
>>
>> * igt@i915_pm_rc6_residency@rc6-accuracy:
>> - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271])
>>[9]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-kbl3/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>>[10]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>> - shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271])
>>[11]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-snb7/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>>[12]:
>> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-snb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>>
>> * igt@i915_suspend@fence-restore-untiled:
>> - shard-apl:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/10] drm/i915: Add windowing for primary planes on gen2/3 and chv
On Thu, May 30, 2019 at 05:43:00AM -, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [01/10] drm/i915: Add windowing for primary
> planes on gen2/3 and chv
> URL : https://patchwork.freedesktop.org/series/61345/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6165_full -> Patchwork_13133_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_13133_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_13133_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_13133_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@kms_plane@pixel-format-pipe-a-planes:
> - shard-glk: [PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-glk3/igt@kms_pl...@pixel-format-pipe-a-planes.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-glk8/igt@kms_pl...@pixel-format-pipe-a-planes.html
<7> [125.370679] [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60
148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
...
<7> [125.542650] [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 79200
kHz, VCO 633600 kHz, ref 19200 kHz, bypass 19200 kHz, voltage
level 4
...
<7> [133.682144] [drm:skl_check_pipe_max_pixel_rate [i915]] Max supported pixel
clock with scaling exceeded
Max pixel rate for 64bpp is 79.2*2 * 8/9 = 140.8 Mhz, which we are
exceeding. We'd need some way to bump the cdclk for this case, but
the kernel will only do that for modesets, and it won't account for
that 8/9 factor. Not sure there is a great way to handle these sorts
of cases.
>
> * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
> - shard-apl: [PASS][3] -> [FAIL][4] +4 similar issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl5/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl7/igt@kms_plane_scal...@pipe-c-scaler-with-pixel-format.html
<7> [1749.831610] [drm:drm_atomic_helper_check_plane_state] Invalid scaling of
plane
<7> [1749.831620] [drm:drm_rect_debug_print] src:
8.00x8.00+0.00+0.00
<7> [1749.831625] [drm:drm_rect_debug_print] dst: 1920x1080+0+0
Not quite sure what's going on here. Unfortunately the debugs don't have
enough information to see what's going on.
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_workarounds@suspend-resume-context:
> - {shard-iclb}: [PASS][5] -> [FAIL][6] +1 similar issue
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-iclb3/igt@gem_workarou...@suspend-resume-context.html
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-iclb2/igt@gem_workarou...@suspend-resume-context.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_13133_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@gem_ctx_switch@basic-all-heavy:
> - shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-hsw5/igt@gem_ctx_swi...@basic-all-heavy.html
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-hsw1/igt@gem_ctx_swi...@basic-all-heavy.html
>
> * igt@i915_pm_rc6_residency@rc6-accuracy:
> - shard-kbl: [PASS][9] -> [SKIP][10] ([fdo#109271])
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-kbl3/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-kbl2/igt@i915_pm_rc6_reside...@rc6-accuracy.html
> - shard-snb: [PASS][11] -> [SKIP][12] ([fdo#109271])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-snb7/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-snb6/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>
> * igt@i915_suspend@fence-restore-untiled:
> - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2
> similar issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6165/shard-apl8/igt@i915_susp...@fence-restore-untiled.html
>[14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13133/shard-apl4/igt@i915_susp...@fence-restore-untiled.html
>
> *
