On Fri, Apr 26, 2024 at 01:51:36PM +0300, Jani Nikula wrote:
> Clean up i915_reg.h.
>
> v2: Drop chicken regs and comments (Ville)
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> drivers/gpu/drm/i915/display/intel_fbc_regs.h | 120 +
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 123 --
> drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 6 files changed, 125 insertions(+), 123 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_fbc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 7c4d2b2bf20b..151dcd0c45b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -54,6 +54,7 @@
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
> +#include "intel_fbc_regs.h"
> #include "intel_frontbuffer.h"
>
> #define for_each_fbc_id(__dev_priv, __fbc_id) \
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> new file mode 100644
> index ..ae0699c3c2fe
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -0,0 +1,120 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2024 Intel Corporation */
> +
> +#ifndef __INTEL_FBC_REGS__
> +#define __INTEL_FBC_REGS__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
> +#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
> +#define FBC_CONTROL _MMIO(0x3208)
> +#define FBC_CTL_EN REG_BIT(31)
> +#define FBC_CTL_PERIODIC REG_BIT(30)
> +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
> +#define FBC_CTL_INTERVAL(x)
> REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
> +#define FBC_CTL_STOP_ON_MODREG_BIT(15)
> +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
> +#define FBC_CTL_C3_IDLEREG_BIT(13) /* i945gm only */
> +#define FBC_CTL_STRIDE_MASKREG_GENMASK(12, 5)
> +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
> +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
> +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK,
> (x))
> +#define FBC_COMMAND _MMIO(0x320c)
> +#define FBC_CMD_COMPRESS REG_BIT(0)
> +#define FBC_STATUS _MMIO(0x3210)
> +#define FBC_STAT_COMPRESSING REG_BIT(31)
> +#define FBC_STAT_COMPRESSEDREG_BIT(30)
> +#define FBC_STAT_MODIFIED REG_BIT(29)
> +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
> +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
> +#define FBC_CTL_FENCE_DBL REG_BIT(4)
> +#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
> +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
> +#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
> +#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
> +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
> +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
> +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
> +#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK,
> (i9xx_plane))
> +#define FBC_FENCE_OFF_MMIO(0x3218) /* i965gm only, BSpec
> typo has 321Bh */
> +#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
> +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
> +#define FBC_MOD_NUM_VALID REG_BIT(0)
> +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
> +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags
> per register */
> +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
> +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
> +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
> +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
> +
> +#define FBC_LL_SIZE (1536)
> +
> +#define DPFC_CB_BASE _MMIO(0x3200)
> +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
> +#define DPFC_CONTROL _MMIO(0x3208)
> +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
> +#define DPFC_CTL_ENREG_BIT(31)
> +#define DPFC_CTL_PLANE_MASK_G4XREG_BIT(30) /* g4x-snb */
> +#define DPFC_CTL_PLANE_G4X(i9xx_plane)
> REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
> +#define DPFC_CTL_FENCE_EN_G4X
