Re: [Intel-gfx] [RFCv2 16/19] drm/i915: Sanity check all registers for matching fw domains
On 20 December 2016 at 13:08, Chris Wilson wrote:
> Add a late selftest that walks over all forcewake registers (those below
> 0x4) and checks intel_uncore_forcewake_for_reg() that the look
I don't see where we use intel_uncore_forcewake_for_reg() ?
look ?
> exists and we having the matching powerwells.
s/having/have/
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/selftests/intel_uncore.c | 47
> +++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> index c18fddb12d00..c9f90514500f 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
> @@ -107,6 +107,49 @@ int intel_uncore_mock_selftests(void)
> return 0;
> }
>
> +static int intel_uncore_check_forcewake_domains(struct drm_i915_private
> *dev_priv)
> +{
> +#define FW_RANGE 0x4
> + unsigned long *valid;
> + u32 offset;
> + int err;
> +
> + valid = kzalloc(BITS_TO_LONGS(FW_RANGE) * sizeof(*valid),
> + GFP_TEMPORARY);
> + if (!valid)
> + return -ENOMEM;
> +
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + check_for_unclaimed_mmio(dev_priv);
> + for (offset = 0; offset < FW_RANGE; offset += 4) {
> + i915_reg_t reg = { offset };
> +
> + (void)I915_READ_FW(reg);
> + if (!check_for_unclaimed_mmio(dev_priv))
> + set_bit(offset, valid);
> + }
> +
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +
> + for_each_set_bit(offset, valid, FW_RANGE) {
> + i915_reg_t reg = { offset };
> +
> + intel_uncore_forcewake_reset(dev_priv, false);
> + check_for_unclaimed_mmio(dev_priv);
> +
> + (void)I915_READ(reg);
> + if (check_for_unclaimed_mmio(dev_priv)) {
> + pr_err("Unclaimed mmio read to register 0x%04x\n",
> + offset);
> + err = -EINVAL;
> + }
> + }
> +
> + kfree(valid);
> + return err;
#undef FW_RANGE
Reviewed-by: Matthew Auld
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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/guc: Make sure vma containing firmware is GuC mappable
== Series Details == Series: drm/i915/guc: Make sure vma containing firmware is GuC mappable URL : https://patchwork.freedesktop.org/series/17836/ State : warning == Summary == Series 17836v1 drm/i915/guc: Make sure vma containing firmware is GuC mappable https://patchwork.freedesktop.org/api/1.0/series/17836/revisions/1/mbox/ Test kms_force_connector_basic: Subgroup force-edid: pass -> DMESG-WARN (fi-snb-2520m) fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:246 pass:214 dwarn:1 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 b69fc4c941bef6d10750ce3f07daedfffc7017d1 drm-tip: 2017y-01m-11d-17h-30m-02s UTC integration manifest e43f2d8 drm/i915/guc: Make sure vma containing firmware is GuC mappable == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3486/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: warning for 4.10-rc2 oops in DRM connector code (rev2)
== Series Details == Series: 4.10-rc2 oops in DRM connector code (rev2) URL : https://patchwork.freedesktop.org/series/17563/ State : warning == Summary == Series 17563v2 4.10-rc2 oops in DRM connector code https://patchwork.freedesktop.org/api/1.0/series/17563/revisions/2/mbox/ Test kms_force_connector_basic: Subgroup force-edid: pass -> DMESG-WARN (fi-snb-2520m) fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:246 pass:214 dwarn:1 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 b69fc4c941bef6d10750ce3f07daedfffc7017d1 drm-tip: 2017y-01m-11d-17h-30m-02s UTC integration manifest 736c891 4.10-rc2 oops in DRM connector code == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3487/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/2] drm: link status property and DP link training failure handling
On Tue, Dec 20, 2016 at 10:30:17AM +0100, Daniel Vetter wrote: > On Mon, Dec 19, 2016 at 11:15:40PM +, Pandiyan, Dhinakaran wrote: > > On Sun, 2016-12-18 at 14:43 +0100, Daniel Vetter wrote: > > > On Sat, Dec 17, 2016 at 05:47:56AM +, Pandiyan, Dhinakaran wrote: > > > > On Fri, 2016-12-16 at 16:47 +0200, Jani Nikula wrote: > > > > > On Fri, 16 Dec 2016, Daniel Vetter wrote: > > > > > > On Fri, Dec 16, 2016 at 12:29:05PM +0200, Jani Nikula wrote: > > > > > >> The two remaining patches from [1], rebased. > > > > > >> > > > > > >> BR, > > > > > >> Jani. > > > > > >> > > > > > >> > > > > > >> [1] > > > > > >> 1480984058-552-1-git-send-email-manasi.d.navare@intel.com">http://mid.mail-archive.com/1480984058-552-1-git-send-email-manasi.d.navare@intel.com > > > > > > > > > > > > Just for the record, I think the only thing missing here is the Xorg > > > > > > review on the -modesetting patch. As soon as we have that I can > > > > > > vacuum > > > > > > this up (probably best through drm-misc, but not sure). > > > > > > > > > > Yeah I rebased this (and provided a debug hack privately) so Martin > > > > > can > > > > > test the modesetting changes. > > > > > > > > > > BR, > > > > > Jani. > > > > > > > > > > > > > > > > > > I tested the -modesetting patch, which Martin had provided to Manasi, > > > > with a compliance testing device (DPR-120) that can simulate link > > > > training failure. The link rate correctly lowered after the link_status > > > > property was set to BAD by the kernel and the userspace responded with a > > > > modeset. > > > > > > > > One thing that was not straight forward to figure out was I had to boot > > > > with i915.nuclear_pageflip=1. Is it documented somewhere that the > > > > property needs DRIVER_ATOMIC to be set, or is it implicit? > > > > > > It should work without DRIVER_ATOMIC. At least the property should be > > > exposed ... If this does only work with DRIVER_ATOMIC set then we have a > > > bug somewhere. Can you pls try to figure out why it doesn't work? > > > > > > > The property is exposed even without DRIVER_ATOMIC set, but the value is > > always GOOD (0). > > We set connector->state->link_status to BAD when link training fails but > > the getconnector() ioctl ends up reading obj->properties->values[i] if > > DRIVER_ATOMIC is NOT set. But with DRIVER_ATOMIC set, getconnector() > > calls into drm_atomic_connector_get_property() and retrieves the value > > stored in connector->state->link_status. > > That sounds like a bug in the getconnector code. This needs the same > treatment as other places, see e.g. > > commit d3a46183db97536a53df5de6b556bd61197842b2 > Author: Daniel Vetter > Date: Wed Jun 8 14:19:15 2016 +0200 > > drm: Replace fb_helper->atomic with mode_config->atomic_commit > > I think it'd be good to extract this check into a > drm_drv_uses_atomic_modeset to better self-document the code, roll it out > to all existing places that check for atomic_commit and then also roll it > out to the getproperty functions (for connectors, planes and crtcs). > > > > > The other thing I had trouble with -modesetting was, there was no > > > > modeset following a long pulse from the sink at the begging of the test. > > > > I had to force a modeset by changing the resolution so that the link > > > > training path is executed. However, the link training failure induced a > > > > modeset without any intervention. This seems little strange because in case of SNA driver, it does respond with a full reprobe and a modeset following a long pulse from the sink at the beginning of the test and no forcing through xrandr was required. I think the modesetting driver should also behave the same and should not need any forcing of the modeset, but should be able to respond to the hotplug/long pulse at the beginning of each test which is trying to simulate the connect/disconnect of the DP cable. My guess is that the modesetting driver was probably not built with hotplug support which would cause it to not respond to the long pulse at the beginning of the test. Chris/Martin/Daniel , any thoughts? Manasi > > > > > > Sounds roughly like how it's supposed to work. For real mode configuration > > > changes the desktop environment is supposed to set the mode it wants, by > > > listening to the xrandr hotplug event. That's not the same as the udev > > > hotplug event. You can listen for the xrandr hotplug event using > > > > > > $ xev -event randr > > > > > > > Got it, -modesetting does indeed send out the hotplug events upon > > hotplug. > > Excellent, so at least that's all working well. > -Daniel > > > > > -DK > > > > > > > Cheers, Daniel > > > > > > > > > > > -DK > > > > > > > > > > > > > > -Daniel > > > > > > > > > > > >> > > > > > >> > > > > > >> Manasi Navare (2): > > > > > >> drm: Add a new connector atomic property for link status > > > > > >> drm/i915: Implement Link Rate fallback on Link training failure > > > > > >> > > > > > >> dri
[Intel-gfx] [PATCH i-g-t rfc 07/29] tests/kms_crtc_background_color: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_crtc_background_color.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_crtc_background_color.c b/tests/kms_crtc_background_color.c index 537d4ce6..d6dd8d90 100644 --- a/tests/kms_crtc_background_color.c +++ b/tests/kms_crtc_background_color.c @@ -136,7 +136,7 @@ static void test_crtc_background(data_t *data) igt_output_set_pipe(output, pipe); - plane = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + plane = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_require(plane->pipe->background_property); prepare_crtc(data, output, pipe, plane, 1, PURPLE, BLACK64); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 15/29] tests/kms_mmio_vs_cs_flip: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_mmio_vs_cs_flip.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/kms_mmio_vs_cs_flip.c b/tests/kms_mmio_vs_cs_flip.c
index 25854020..e24299e5 100644
--- a/tests/kms_mmio_vs_cs_flip.c
+++ b/tests/kms_mmio_vs_cs_flip.c
@@ -191,7 +191,7 @@ static void make_gpu_busy(data_t *data, uint32_t
flip_handle)
* supposed to be.
*/
static bool
-test_plane(data_t *data, igt_output_t *output, enum pipe pipe, enum igt_plane
plane)
+test_plane(data_t *data, igt_output_t *output, enum pipe pipe, int plane)
{
struct igt_fb red_fb, green_fb, blue_fb;
drmModeModeInfo *mode;
@@ -208,7 +208,7 @@ test_plane(data_t *data, igt_output_t *output, enum pipe
pipe, enum igt_plane pl
return false;
}
- primary = igt_output_get_plane(output, 0);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
sprite = igt_output_get_plane(output, plane);
mode = igt_output_get_mode(output);
@@ -473,7 +473,7 @@ static void
run_plane_test(data_t *data)
{
igt_output_t *output;
- enum igt_plane plane = 1; /* testing with one sprite is enough */
+ int plane = 1; /* testing with one sprite is enough */
int valid_tests = 0;
enum pipe pipe;
--
2.11.0
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[Intel-gfx] [PATCH i-g-t rfc 13/29] tests/kms_legacy_colorkey: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_legacy_colorkey.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/kms_legacy_colorkey.c b/tests/kms_legacy_colorkey.c
index 25f98aad..150520ce 100644
--- a/tests/kms_legacy_colorkey.c
+++ b/tests/kms_legacy_colorkey.c
@@ -55,8 +55,10 @@ igt_simple_main
for_each_pipe(&display, p) {
for_each_plane_on_pipe(&display, p, plane) {
+ bool is_valid = (plane->type == DRM_PLANE_TYPE_PRIMARY
||
+plane->type == DRM_PLANE_TYPE_CURSOR);
test_plane(plane->drm_plane->plane_id,
- (plane->is_cursor || plane->is_primary) ?
-ENOENT : 0);
+ is_valid ? -ENOENT : 0);
max_id = max(max_id, plane->drm_plane->plane_id);
}
--
2.11.0
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[Intel-gfx] [PATCH i-g-t rfc 02/29] lib/igt_kms: Fixed typo
Signed-off-by: Robert Foss
---
lib/igt_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 5312f8d8..0b8851f2 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -308,7 +308,7 @@ const unsigned char* igt_kms_get_alt_edid(void)
* kmstest_pipe_name:
* @pipe: display pipe
*
- * Returns: String represnting @pipe, e.g. "A".
+ * Returns: String reprsenting @pipe, e.g. "A".
*/
const char *kmstest_pipe_name(enum pipe pipe)
{
--
2.11.0
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[Intel-gfx] [PATCH i-g-t rfc 05/29] tests/kms_busy: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_busy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_busy.c b/tests/kms_busy.c index 1ae5d7fb..e6276927 100644 --- a/tests/kms_busy.c +++ b/tests/kms_busy.c @@ -53,7 +53,7 @@ set_fb_on_crtc(igt_display_t *dpy, int pipe, struct igt_fb *fb) LOCAL_I915_FORMAT_MOD_X_TILED, fb); - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, fb); return output; -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 06/29] tests/kms_chv_cursor_fail: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_chv_cursor_fail.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/kms_chv_cursor_fail.c b/tests/kms_chv_cursor_fail.c index 8f878cbf..a5c648af 100644 --- a/tests/kms_chv_cursor_fail.c +++ b/tests/kms_chv_cursor_fail.c @@ -65,7 +65,7 @@ static void cursor_disable(data_t *data) igt_output_t *output = data->output; igt_plane_t *cursor; - cursor = igt_output_get_plane(output, IGT_PLANE_CURSOR); + cursor = igt_output_get_plane_type(output, DRM_PLANE_TYPE_CURSOR); igt_plane_set_fb(cursor, NULL); } @@ -249,7 +249,7 @@ static bool prepare_crtc(data_t *data) LOCAL_DRM_FORMAT_MOD_NONE, &data->primary_fb); - primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, &data->primary_fb); igt_display_commit(display); @@ -286,7 +286,7 @@ static void cleanup_crtc(data_t *data) igt_remove_fb(data->drm_fd, &data->primary_fb); - primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, NULL); igt_output_set_pipe(data->output, PIPE_ANY); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 04/29] tests/kms_atomic_transition: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_atomic_transition.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index 851ffc95..5fdb6175 100644
--- a/tests/kms_atomic_transition.c
+++ b/tests/kms_atomic_transition.c
@@ -120,7 +120,8 @@ static void set_sprite_wh(igt_display_t *display, enum pipe
pipe,
for_each_plane_on_pipe(display, pipe, plane) {
int i = plane->index;
- if (plane->is_primary || plane->is_cursor)
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY ||
+ plane->type == DRM_PLANE_TYPE_CURSOR)
continue;
parms[i].width = w;
@@ -156,20 +157,16 @@ static void setup_parms(igt_display_t *display, enum pipe
pipe,
for_each_plane_on_pipe(display, pipe, plane) {
int i = plane->index;
- if (plane->is_primary)
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
parms[i].fb = plane->fb;
- else if (plane->is_cursor)
- parms[i].fb = argb_fb;
- else
- parms[i].fb = sprite_fb;
-
- if (plane->is_primary) {
parms[i].width = mode->hdisplay;
parms[i].height = mode->vdisplay;
- } else if (plane->is_cursor) {
+ } else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ parms[i].fb = argb_fb;
parms[i].width = cursor_width;
parms[i].height = cursor_height;
- }
+ } else
+ parms[i].fb = sprite_fb;
}
igt_create_fb(display->drm_fd, cursor_width, cursor_height,
@@ -273,7 +270,7 @@ run_transition_test(igt_display_t *display, enum pipe pipe,
igt_output_t *output
drmModeModeInfo *mode, override_mode;
igt_plane_t *plane;
uint32_t iter_max = 1 << display->pipes[pipe].n_planes, i;
- struct plane_parms parms[IGT_MAX_PLANES];
+ struct plane_parms parms[display->pipes[pipe].n_planes];
bool skip_test = false;
unsigned flags = DRM_MODE_PAGE_FLIP_EVENT;
@@ -421,7 +418,8 @@ static unsigned set_combinations(igt_display_t *display,
unsigned mask, struct i
igt_output_set_pipe(output, PIPE_NONE);
for_each_pipe(display, pipe) {
- igt_plane_t *plane =
&display->pipes[pipe].planes[IGT_PLANE_PRIMARY];
+ igt_plane_t *plane =
igt_pipe_get_plane_type(&display->pipes[pipe],
+ DRM_PLANE_TYPE_PRIMARY);
drmModeModeInfo *mode = NULL;
if (!(mask & (1 << pipe))) {
@@ -462,7 +460,7 @@ static void refresh_primaries(igt_display_t *display)
for_each_pipe(display, pipe)
for_each_plane_on_pipe(display, pipe, plane)
- if (plane->is_primary && plane->fb)
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY && plane->fb)
plane->fb_changed = true;
}
@@ -506,7 +504,8 @@ static void run_modeset_tests(igt_display_t *display, int
howmany, bool nonblock
DRM_FORMAT_XRGB, 0, .5, .5, .5,
&fbs[1]);
for_each_pipe(display, i) {
- igt_plane_t *plane =
&display->pipes[i].planes[IGT_PLANE_PRIMARY];
+ igt_pipe_t *pipe = &display->pipes[i];
+ igt_plane_t *plane = igt_pipe_get_plane_type(pipe,
DRM_PLANE_TYPE_PRIMARY);
drmModeModeInfo *mode = NULL;
if (is_i915_device(display->drm_fd))
--
2.11.0
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[Intel-gfx] [PATCH i-g-t rfc 12/29] tests/kms_flip_event_leak: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_flip_event_leak.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_flip_event_leak.c b/tests/kms_flip_event_leak.c index a1389b4c..636a706e 100644 --- a/tests/kms_flip_event_leak.c +++ b/tests/kms_flip_event_leak.c @@ -57,7 +57,7 @@ static bool test(data_t *data, enum pipe pipe, igt_output_t *output) return false; } - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); mode = igt_output_get_mode(output); igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay, -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 03/29] lib/igt_kms: Implement dynamic plane count support
In upcoming drm-misc-next changes, the number of planes per pipe has
been increased as more than one primary plane can be associated with
a pipe.
The simple fix for this would be to simply bump hardcoded value for
number of frames per pipe.
But a better solution would be to add support for dynamic number of
planes per pipe to i-g-t.
Signed-off-by: Robert Foss
---
lib/igt_kms.c | 157 +++---
lib/igt_kms.h | 32
2 files changed, 115 insertions(+), 74 deletions(-)
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 0b8851f2..294a8113 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -329,24 +329,17 @@ const char *kmstest_pipe_name(enum pipe pipe)
*
* Returns: String represnting @pipe, e.g. "plane1".
*/
-const char *kmstest_plane_name(enum igt_plane plane)
+const char *kmstest_plane_type_name(int plane_type)
{
static const char *names[] = {
- [IGT_PLANE_1] = "plane1",
- [IGT_PLANE_2] = "plane2",
- [IGT_PLANE_3] = "plane3",
- [IGT_PLANE_4] = "plane4",
- [IGT_PLANE_5] = "plane5",
- [IGT_PLANE_6] = "plane6",
- [IGT_PLANE_7] = "plane7",
- [IGT_PLANE_8] = "plane8",
- [IGT_PLANE_9] = "plane9",
- [IGT_PLANE_CURSOR] = "cursor",
+ [DRM_PLANE_TYPE_OVERLAY] = "overlay",
+ [DRM_PLANE_TYPE_PRIMARY] = "primary",
+ [DRM_PLANE_TYPE_CURSOR] = "cursor",
};
- igt_assert(plane < ARRAY_SIZE(names) && names[plane]);
+ igt_assert(plane_type < ARRAY_SIZE(names) && names[plane_type]);
- return names[plane];
+ return names[plane_type];
}
static const char *mode_stereo_name(const drmModeModeInfo *mode)
@@ -1355,14 +1348,17 @@ void igt_display_init(igt_display_t *display, int
drm_fd)
for (i = 0; i < display->n_pipes; i++) {
igt_pipe_t *pipe = &display->pipes[i];
igt_plane_t *plane;
- int p = IGT_PLANE_2;
+ int p = 1;
int j, type;
- uint8_t n_planes = 0;
+ uint8_t last_plane = 0, n_planes = 0;
uint64_t prop_value;
pipe->crtc_id = resources->crtcs[i];
pipe->display = display;
pipe->pipe = i;
+ pipe->plane_cursor = -1;
+ pipe->plane_primary = -1;
+ pipe->planes = NULL;
get_crtc_property(display->drm_fd, pipe->crtc_id,
"background_color",
@@ -1388,6 +1384,27 @@ void igt_display_init(igt_display_t *display, int drm_fd)
igt_atomic_fill_pipe_props(display, pipe, IGT_NUM_CRTC_PROPS,
igt_crtc_prop_names);
+ /* count number of valid planes */
+ for (j = 0; j < plane_resources->count_planes; j++) {
+ drmModePlane *drm_plane;
+
+ drm_plane = drmModeGetPlane(display->drm_fd,
+ plane_resources->planes[j]);
+ igt_assert(drm_plane);
+
+ if (!(drm_plane->possible_crtcs & (1 << i))) {
+ drmModeFreePlane(drm_plane);
+ continue;
+}
+
+ n_planes++;
+ }
+
+ igt_assert_lte(0, n_planes);
+ pipe->planes = calloc(sizeof(igt_plane_t), n_planes);
+ igt_assert_f(pipe->planes != NULL, "Failed to allocate memory
for %d planes\n", n_planes);
+ last_plane = n_planes - 1;
+
/* add the planes that can be used with that pipe */
for (j = 0; j < plane_resources->count_planes; j++) {
drmModePlane *drm_plane;
@@ -1405,21 +1422,24 @@ void igt_display_init(igt_display_t *display, int
drm_fd)
plane_resources->planes[j]);
switch (type) {
case DRM_PLANE_TYPE_PRIMARY:
- plane = &pipe->planes[IGT_PLANE_PRIMARY];
- plane->is_primary = 1;
- plane->index = IGT_PLANE_PRIMARY;
+ if (pipe->plane_primary == -1) {
+ plane = &pipe->planes[0];
+ plane->index = 0;
+ pipe->plane_primary = 0;
+ } else {
+ plane = &pipe->planes[p];
+ plane->index = p++;
+ }
break;
case DRM_PLANE_TYPE_CURSOR:
- /*
-* Cursor should be the highest index in our
-
[Intel-gfx] [PATCH i-g-t rfc 10/29] tests/kms_fbc_crc: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_fbc_crc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/kms_fbc_crc.c b/tests/kms_fbc_crc.c
index 2a2c93f7..f2fd88a6 100644
--- a/tests/kms_fbc_crc.c
+++ b/tests/kms_fbc_crc.c
@@ -383,7 +383,7 @@ static bool prepare_test(data_t *data, enum test_mode
test_mode)
igt_output_t *output = data->output;
igt_pipe_crc_t *pipe_crc;
- data->primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY);
+ data->primary = igt_output_get_plane_type(data->output,
DRM_PLANE_TYPE_PRIMARY);
create_fbs(data, true, data->fb);
@@ -471,7 +471,7 @@ static void reset_display(data_t *data)
for_each_connected_output(display, data->output) {
if (data->output->valid > 0) {
- data->primary = igt_output_get_plane(data->output,
IGT_PLANE_PRIMARY);
+ data->primary =
igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(data->primary, NULL);
}
igt_output_set_pipe(data->output, PIPE_ANY);
--
2.11.0
___
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[Intel-gfx] [PATCH i-g-t rfc 08/29] tests/kms_cursor_crc: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_cursor_crc.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/kms_cursor_crc.c b/tests/kms_cursor_crc.c index 926579d6..a6ba6dc4 100644 --- a/tests/kms_cursor_crc.c +++ b/tests/kms_cursor_crc.c @@ -92,7 +92,7 @@ static void cursor_enable(data_t *data) igt_output_t *output = data->output; igt_plane_t *cursor; - cursor = igt_output_get_plane(output, IGT_PLANE_CURSOR); + cursor = igt_output_get_plane_type(output, DRM_PLANE_TYPE_CURSOR); igt_plane_set_fb(cursor, &data->fb); igt_plane_set_size(cursor, data->curw, data->curh); } @@ -102,7 +102,7 @@ static void cursor_disable(data_t *data) igt_output_t *output = data->output; igt_plane_t *cursor; - cursor = igt_output_get_plane(output, IGT_PLANE_CURSOR); + cursor = igt_output_get_plane_type(output, DRM_PLANE_TYPE_CURSOR); igt_plane_set_fb(cursor, NULL); } @@ -120,7 +120,7 @@ static void do_single_test(data_t *data, int x, int y) /* Hardware test */ igt_paint_test_pattern(cr, data->screenw, data->screenh); cursor_enable(data); - cursor = igt_output_get_plane(data->output, IGT_PLANE_CURSOR); + cursor = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_CURSOR); igt_plane_set_position(cursor, x, y); igt_display_commit(display); igt_wait_for_vblank(data->drm_fd, data->pipe); @@ -174,7 +174,7 @@ static void do_fail_test(data_t *data, int x, int y, int expect) /* Hardware test */ igt_paint_test_pattern(cr, data->screenw, data->screenh); cursor_enable(data); - cursor = igt_output_get_plane(data->output, IGT_PLANE_CURSOR); + cursor = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_CURSOR); igt_plane_set_position(cursor, x, y); ret = igt_display_try_commit2(display, COMMIT_LEGACY); @@ -308,7 +308,7 @@ static bool prepare_crtc(data_t *data, igt_output_t *output, 0.0, 0.0, 0.0, &data->primary_fb); - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, &data->primary_fb); igt_display_commit(display); @@ -351,7 +351,7 @@ static void cleanup_crtc(data_t *data, igt_output_t *output) igt_remove_fb(data->drm_fd, &data->primary_fb); - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, NULL); igt_output_set_pipe(output, PIPE_ANY); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 09/29] tests/kms_cursor_legacy: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_cursor_legacy.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/tests/kms_cursor_legacy.c b/tests/kms_cursor_legacy.c
index 40220970..dcec9834 100644
--- a/tests/kms_cursor_legacy.c
+++ b/tests/kms_cursor_legacy.c
@@ -166,7 +166,7 @@ static igt_output_t *set_fb_on_crtc(igt_display_t *display,
int pipe, struct igt
mode->hdisplay, mode->vdisplay,
DRM_FORMAT_XRGB, I915_TILING_NONE, fb_info);
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, fb_info);
return output;
@@ -180,7 +180,7 @@ static void set_cursor_on_pipe(igt_display_t *display, enum
pipe pipe, struct ig
igt_plane_t *plane, *cursor = NULL;
for_each_plane_on_pipe(display, pipe, plane) {
- if (!plane->is_cursor)
+ if (plane->type != DRM_PLANE_TYPE_CURSOR)
continue;
cursor = plane;
@@ -250,13 +250,14 @@ static enum pipe find_connected_pipe(igt_display_t
*display, bool second)
return pipe;
}
-static void flip_nonblocking(igt_display_t *display, enum pipe pipe, bool
atomic, struct igt_fb *fb)
+static void flip_nonblocking(igt_display_t *display, enum pipe pipe_id, bool
atomic, struct igt_fb *fb)
{
- igt_plane_t *primary = &display->pipes[pipe].planes[IGT_PLANE_PRIMARY];
+ igt_pipe_t *pipe = &display->pipes[pipe_id];
+ igt_plane_t *primary = igt_pipe_get_plane_type(pipe,
DRM_PLANE_TYPE_PRIMARY);
if (!atomic) {
/* Schedule a nonblocking flip for the next vblank */
- do_or_die(drmModePageFlip(display->drm_fd,
display->pipes[pipe].crtc_id, fb->fb_id,
+ do_or_die(drmModePageFlip(display->drm_fd, pipe->crtc_id,
fb->fb_id,
DRM_MODE_PAGE_FLIP_EVENT, fb));
} else {
igt_plane_set_fb(primary, fb);
@@ -283,12 +284,13 @@ static bool cursor_slowpath(enum flip_test mode)
return true;
}
-static void transition_nonblocking(igt_display_t *display, enum pipe pipe,
+static void transition_nonblocking(igt_display_t *display, enum pipe pipe_id,
struct igt_fb *prim_fb, struct igt_fb
*argb_fb,
bool hide_sprite)
{
- igt_plane_t *primary = &display->pipes[pipe].planes[IGT_PLANE_PRIMARY];
- igt_plane_t *sprite = &display->pipes[pipe].planes[IGT_PLANE_2];
+ igt_pipe_t *pipe = &display->pipes[pipe_id];
+ igt_plane_t *primary = igt_pipe_get_plane_type(pipe,
DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_t *sprite = igt_pipe_get_plane_type(pipe,
DRM_PLANE_TYPE_OVERLAY);
if (hide_sprite) {
igt_plane_set_fb(primary, prim_fb);
@@ -345,7 +347,7 @@ static void prepare_flip_test(igt_display_t *display,
if (mode == flip_test_atomic_transitions ||
mode == flip_test_atomic_transitions_varying_size) {
igt_require(display->pipes[flip_pipe].n_planes > 1 &&
-
!display->pipes[flip_pipe].planes[IGT_PLANE_2].is_cursor);
+ display->pipes[flip_pipe].planes[1].type !=
DRM_PLANE_TYPE_CURSOR);
igt_create_color_pattern_fb(display->drm_fd, prim_fb->width,
prim_fb->height,
DRM_FORMAT_ARGB, 0, .1, .1, .1,
argb_fb);
@@ -794,7 +796,7 @@ static void nonblocking_modeset_vs_cursor(igt_display_t
*display, int loops)
arg[0].flags |= DRM_MODE_CURSOR_BO;
for_each_plane_on_pipe(display, pipe, plane) {
- if (!plane->is_cursor)
+ if (plane->type != DRM_PLANE_TYPE_CURSOR)
continue;
cursor = plane;
@@ -1240,6 +1242,8 @@ static void flip_vs_cursor_busy_crc(igt_display_t
*display, bool atomic)
unsigned vblank_start;
enum pipe pipe = find_connected_pipe(display, false);
igt_pipe_crc_t *pipe_crc;
+ igt_pipe_t *pipe_connected = &display->pipes[pipe];
+ igt_plane_t *plane_primary = igt_pipe_get_plane_type(pipe_connected,
DRM_PLANE_TYPE_PRIMARY);
igt_crc_t crcs[3];
if (atomic)
@@ -1271,10 +1275,10 @@ static void flip_vs_cursor_busy_crc(igt_display_t
*display, bool atomic)
* setting the correct cache level, else we get a stall in the
* page flip handler.
*/
- igt_plane_set_fb(&display->pipes[pipe].planes[IGT_PLANE_PRIMARY],
&fb_info[1]);
+ igt_plane_set_fb(plane_primary, &fb_info[1]);
igt_display_commit2(display, COMMIT_UNIVERSAL);
- igt_plane_set_fb(&display->pipes[pipe].planes[IGT_PLANE_PRIMARY],
&fb
[Intel-gfx] [PATCH i-g-t rfc 23/29] tests/kms_pwrite_crc: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_pwrite_crc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_pwrite_crc.c b/tests/kms_pwrite_crc.c index 86292bda..587d0561 100644 --- a/tests/kms_pwrite_crc.c +++ b/tests/kms_pwrite_crc.c @@ -123,7 +123,7 @@ static bool prepare_crtc(data_t *data) DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE, 1.0, 1.0, 1.0, &data->fb[0]); - data->primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + data->primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(data->primary, &data->fb[0]); igt_display_commit(display); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 18/29] tests/kms_plane: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_plane.c | 94 ++-
1 file changed, 52 insertions(+), 42 deletions(-)
diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index ce5e3101..4817ec4e 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -150,7 +150,7 @@ enum {
static void
test_plane_position_with_output(data_t *data,
enum pipe pipe,
- enum igt_plane plane,
+ int plane,
igt_output_t *output,
unsigned int flags)
{
@@ -170,7 +170,7 @@ test_plane_position_with_output(data_t *data,
igt_output_set_pipe(output, pipe);
mode = igt_output_get_mode(output);
- primary = igt_output_get_plane(output, 0);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
sprite = igt_output_get_plane(output, plane);
create_fb_for_mode__position(data, mode, 100, 100, 64, 64,
@@ -222,7 +222,7 @@ test_plane_position_with_output(data_t *data,
}
static void
-test_plane_position(data_t *data, enum pipe pipe, enum igt_plane plane,
+test_plane_position(data_t *data, enum pipe pipe, int plane,
unsigned int flags)
{
igt_output_t *output;
@@ -294,7 +294,7 @@ enum {
static void
test_plane_panning_with_output(data_t *data,
enum pipe pipe,
- enum igt_plane plane,
+ int plane,
igt_output_t *output,
unsigned int flags)
{
@@ -348,7 +348,7 @@ test_plane_panning_with_output(data_t *data,
}
static void
-test_plane_panning(data_t *data, enum pipe pipe, enum igt_plane plane,
+test_plane_panning(data_t *data, enum pipe pipe, int plane,
unsigned int flags)
{
igt_output_t *output;
@@ -367,47 +367,57 @@ test_plane_panning(data_t *data, enum pipe pipe, enum
igt_plane plane,
}
static void
-run_tests_for_pipe_plane(data_t *data, enum pipe pipe, enum igt_plane plane)
+run_tests_for_pipe_plane(data_t *data, enum pipe pipe)
{
- igt_subtest_f("plane-position-covered-pipe-%s-plane-%d",
- kmstest_pipe_name(pipe), plane)
- test_plane_position(data, pipe, plane,
- TEST_POSITION_FULLY_COVERED);
-
- igt_subtest_f("plane-position-hole-pipe-%s-plane-%d",
- kmstest_pipe_name(pipe), plane)
- test_plane_position(data, pipe, plane, 0);
-
- igt_subtest_f("plane-position-hole-dpms-pipe-%s-plane-%d",
- kmstest_pipe_name(pipe), plane)
- test_plane_position(data, pipe, plane,
- TEST_DPMS);
-
- igt_subtest_f("plane-panning-top-left-pipe-%s-plane-%d",
- kmstest_pipe_name(pipe), plane)
- test_plane_panning(data, pipe, plane, TEST_PANNING_TOP_LEFT);
-
- igt_subtest_f("plane-panning-bottom-right-pipe-%s-plane-%d",
- kmstest_pipe_name(pipe), plane)
- test_plane_panning(data, pipe, plane,
- TEST_PANNING_BOTTOM_RIGHT);
-
- igt_subtest_f("plane-panning-bottom-right-suspend-pipe-%s-plane-%d",
- kmstest_pipe_name(pipe), plane)
- test_plane_panning(data, pipe, plane,
- TEST_PANNING_BOTTOM_RIGHT |
- TEST_SUSPEND_RESUME);
-}
+ igt_subtest_f("plane-position-covered-pipe-%s-planes",
+ kmstest_pipe_name(pipe)) {
+ int n_planes = data->display.pipes[pipe].n_planes;
+ for (int plane = 1; plane < n_planes; plane++)
+ test_plane_position(data, pipe, plane,
+ TEST_POSITION_FULLY_COVERED);
+ }
-static void
-run_tests_for_pipe(data_t *data, enum pipe pipe)
-{
- int plane;
+ igt_subtest_f("plane-position-hole-pipe-%s-planes",
+ kmstest_pipe_name(pipe)) {
+ int n_planes = data->display.pipes[pipe].n_planes;
+ for (int plane = 1; plane < n_planes; plane++)
+ test_plane_position(data, pipe, plane, 0);
+ }
+
+ igt_subtest_f("plane-position-hole-dpms-pipe-%s-planes",
+ kmstest_pipe_name(pipe)) {
+ int n_planes = data->display.pipes[pipe].n_planes;
+ for (int plane = 1; plane < n_planes; plane++)
+ test_plane_position(data, pipe, plane,
+ TEST_DPMS);
+ }
+
+ igt_subtest_f("plane-panning-top-left-pipe-%s-planes",
+ kmstest_pipe_name(pipe)) {
+ int n_planes = data->display.
[Intel-gfx] [PATCH i-g-t rfc 11/29] tests/kms_fence_pin_leak: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_fence_pin_leak.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_fence_pin_leak.c b/tests/kms_fence_pin_leak.c index 7d4ffbcd..98963bbb 100644 --- a/tests/kms_fence_pin_leak.c +++ b/tests/kms_fence_pin_leak.c @@ -122,7 +122,7 @@ static bool run_single_test(data_t *data, enum pipe pipe, igt_output_t *output) } mode = igt_output_get_mode(output); - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay, DRM_FORMAT_XRGB, -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 17/29] tests/kms_pipe_color: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_pipe_color.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_pipe_color.c b/tests/kms_pipe_color.c index 98dc4038..31755690 100644 --- a/tests/kms_pipe_color.c +++ b/tests/kms_pipe_color.c @@ -856,10 +856,10 @@ run_tests_for_pipe(data_t *data, enum pipe p) return; pipe = &data->display.pipes[p]; - if (pipe->n_planes < IGT_PLANE_PRIMARY) + if (pipe->n_planes < 0) return; - primary = &pipe->planes[IGT_PLANE_PRIMARY]; + primary = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY); data->pipe_crc = igt_pipe_crc_new(primary->pipe->pipe, INTEL_PIPE_CRC_SOURCE_AUTO); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 22/29] tests/kms_psr_sink_crc: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_psr_sink_crc.c | 52 +---
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 926b8578..8f6bdc0d 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -34,12 +34,6 @@ bool running_with_psr_disabled;
#define CRC_BLACK ""
-enum planes {
- PRIMARY,
- SPRITE,
- CURSOR,
-};
-
enum operations {
PAGE_FLIP,
MMAP_GTT,
@@ -69,7 +63,7 @@ static const char *op_str(enum operations op)
typedef struct {
int drm_fd;
- enum planes test_plane;
+ int test_plane;
enum operations op;
uint32_t devid;
uint32_t crtc_id;
@@ -313,9 +307,9 @@ static void run_test(data_t *data)
/* Setting a secondary fb/plane */
switch (data->test_plane) {
- case PRIMARY: default: test_plane = data->primary; break;
- case SPRITE: test_plane = data->sprite; break;
- case CURSOR: test_plane = data->cursor; break;
+ case DRM_PLANE_TYPE_PRIMARY: default: test_plane = data->primary; break;
+ case DRM_PLANE_TYPE_OVERLAY: test_plane = data->sprite; break;
+ case DRM_PLANE_TYPE_CURSOR: test_plane = data->cursor; break;
}
igt_plane_set_fb(test_plane, &data->fb_white);
igt_display_commit(&data->display);
@@ -323,7 +317,7 @@ static void run_test(data_t *data)
/* Confirm it is not Green anymore */
igt_assert(wait_psr_entry(data));
get_sink_crc(data, ref_crc);
- if (data->test_plane == PRIMARY)
+ if (data->test_plane == DRM_PLANE_TYPE_PRIMARY)
assert_or_manual(!is_green(ref_crc), "screen WHITE");
else
assert_or_manual(!is_green(ref_crc), "GREEN background with
WHITE box");
@@ -355,7 +349,7 @@ static void run_test(data_t *data)
/* Printing white on white so the screen shouldn't change */
memset(ptr, 0xff, data->mod_size);
get_sink_crc(data, crc);
- if (data->test_plane == PRIMARY)
+ if (data->test_plane == DRM_PLANE_TYPE_PRIMARY)
assert_or_manual(strcmp(ref_crc, crc) == 0, "screen
WHITE");
else
assert_or_manual(strcmp(ref_crc, crc) == 0,
@@ -406,9 +400,9 @@ static void run_test(data_t *data)
static void test_cleanup(data_t *data) {
igt_plane_set_fb(data->primary, NULL);
- if (data->test_plane == SPRITE)
+ if (data->test_plane == DRM_PLANE_TYPE_OVERLAY)
igt_plane_set_fb(data->sprite, NULL);
- if (data->test_plane == CURSOR)
+ if (data->test_plane == DRM_PLANE_TYPE_CURSOR)
igt_plane_set_fb(data->cursor, NULL);
igt_display_commit(&data->display);
@@ -428,7 +422,7 @@ static void setup_test_plane(data_t *data)
0.0, 1.0, 0.0,
&data->fb_green);
- data->primary = igt_output_get_plane(data->output, IGT_PLANE_PRIMARY);
+ data->primary = igt_output_get_plane_type(data->output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(data->primary, NULL);
white_h = data->mode->hdisplay;
@@ -439,16 +433,16 @@ static void setup_test_plane(data_t *data)
data->mod_stride = white_h * 4;
switch (data->test_plane) {
- case SPRITE:
- data->sprite = igt_output_get_plane(data->output,
- IGT_PLANE_2);
+ case DRM_PLANE_TYPE_OVERLAY:
+ data->sprite = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_OVERLAY);
igt_plane_set_fb(data->sprite, NULL);
/* To make it different for human eyes let's make
* sprite visible in only one quarter of the primary
*/
white_h = white_h/2;
white_v = white_v/2;
- case PRIMARY:
+ case DRM_PLANE_TYPE_PRIMARY:
igt_create_color_fb(data->drm_fd,
white_h, white_v,
DRM_FORMAT_XRGB,
@@ -456,9 +450,9 @@ static void setup_test_plane(data_t *data)
1.0, 1.0, 1.0,
&data->fb_white);
break;
- case CURSOR:
- data->cursor = igt_output_get_plane(data->output,
- IGT_PLANE_CURSOR);
+ case DRM_PLANE_TYPE_CURSOR:
+ data->cursor = igt_output_get_plane_type(data->output,
+ DRM_PLANE_TYPE_CURSOR);
igt_plane_set_fb(data->cursor, NULL);
create_cursor_fb(data);
igt_plane_
[Intel-gfx] [PATCH i-g-t rfc 00/29] lib/igt_kms: Implement dynamic plane count support
Coverletter: This series implements dynamic plane count support in lib/igt_kms and modifies all of the tests that rely on a static plane count. Currently it has only been tested on vc4, but testing reveals no new failures. This series can be found here: https://git.collabora.com/cgit/user/robertfoss/intel-gpu-tools.git/ Robert Foss (29): lib/igt_debugfs: Prevent buffer overflow lib/igt_kms: Fixed typo lib/igt_kms: Implement dynamic plane count support tests/kms_atomic_transition: Add support for dynamic number of planes tests/kms_busy: Add support for dynamic number of planes tests/kms_chv_cursor_fail: Add support for dynamic number of planes tests/kms_crtc_background_color: Add support for dynamic number of planes tests/kms_cursor_crc: Add support for dynamic number of planes tests/kms_cursor_legacy: Add support for dynamic number of planes tests/kms_fbc_crc: Add support for dynamic number of planes tests/kms_fence_pin_leak: Add support for dynamic number of planes tests/kms_flip_event_leak: Add support for dynamic number of planes tests/kms_legacy_colorkey: Add support for dynamic number of planes tests/kms_mmap_write_crc: Add support for dynamic number of planes tests/kms_mmio_vs_cs_flip: Add support for dynamic number of planes tests/kms_panel_fitting: Add support for dynamic number of planes tests/kms_pipe_color: Add support for dynamic number of planes tests/kms_plane: Add support for dynamic number of planes tests/kms_plane_multiple: Add support for dynamic number of planes tests/kms_plane_scaling: Add support for dynamic number of planes tests/kms_properties: Add support for dynamic number of planes tests/kms_psr_sink_crc: Add support for dynamic number of planes tests/kms_pwrite_crc: Add support for dynamic number of planes tests/kms_rmfb: Add support for dynamic number of planes tests/kms_rotation_crc: Add support for dynamic number of planes tests/kms_sink_crc_basic: Add support for dynamic number of planes tests/kms_universal_plane: Add support for dynamic number of planes tests/kms_vblank: Add support for dynamic number of planes tests/prime_mmap_kms: Add support for dynamic number of planes lib/igt_debugfs.c | 8 +- lib/igt_kms.c | 159 +++-- lib/igt_kms.h | 32 ++ tests/kms_atomic_transition.c | 27 +++-- tests/kms_busy.c | 2 +- tests/kms_chv_cursor_fail.c | 6 +- tests/kms_crtc_background_color.c | 2 +- tests/kms_cursor_crc.c| 12 +-- tests/kms_cursor_legacy.c | 30 +++--- tests/kms_fbc_crc.c | 4 +- tests/kms_fence_pin_leak.c| 2 +- tests/kms_flip_event_leak.c | 2 +- tests/kms_legacy_colorkey.c | 4 +- tests/kms_mmap_write_crc.c| 2 +- tests/kms_mmio_vs_cs_flip.c | 6 +- tests/kms_panel_fitting.c | 16 +-- tests/kms_pipe_color.c| 4 +- tests/kms_plane.c | 94 ++ tests/kms_plane_multiple.c| 203 +++--- tests/kms_plane_scaling.c | 14 +-- tests/kms_properties.c| 6 +- tests/kms_psr_sink_crc.c | 52 +- tests/kms_pwrite_crc.c| 2 +- tests/kms_rmfb.c | 2 +- tests/kms_rotation_crc.c | 63 ++-- tests/kms_sink_crc_basic.c| 2 +- tests/kms_universal_plane.c | 18 ++-- tests/kms_vblank.c| 4 +- tests/prime_mmap_kms.c| 2 +- 29 files changed, 440 insertions(+), 340 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 01/29] lib/igt_debugfs: Prevent buffer overflow
buf array may overflow with when writing '\0' if
MAX_LINE_LEN bytes are read during read().
Signed-off-by: Robert Foss
---
lib/igt_debugfs.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index d828687a..8b8a627a 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -594,13 +594,15 @@ static int read_crc(igt_pipe_crc_t *pipe_crc, igt_crc_t
*out)
read_len = MAX_LINE_LEN;
igt_set_timeout(5, "CRC reading");
- bytes_read = read(pipe_crc->crc_fd, &buf, read_len);
+ bytes_read = read(pipe_crc->crc_fd, &buf, read_len - 1);
igt_reset_timeout();
- if (bytes_read < 0 && errno == EAGAIN) {
+ if (bytes_read < 0 && errno == EAGAIN)
igt_assert(pipe_crc->flags & O_NONBLOCK);
+
+ if (bytes_read < 0)
bytes_read = 0;
- }
+
buf[bytes_read] = '\0';
if (bytes_read && !pipe_crc_init_from_string(pipe_crc, out, buf))
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 19/29] tests/kms_plane_multiple: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_plane_multiple.c | 203 -
1 file changed, 125 insertions(+), 78 deletions(-)
diff --git a/tests/kms_plane_multiple.c b/tests/kms_plane_multiple.c
index 5e12be45..dec5488d 100644
--- a/tests/kms_plane_multiple.c
+++ b/tests/kms_plane_multiple.c
@@ -47,8 +47,8 @@ typedef struct {
int drm_fd;
igt_display_t display;
igt_pipe_crc_t *pipe_crc;
- igt_plane_t *plane[IGT_MAX_PLANES];
- struct igt_fb fb[IGT_MAX_PLANES];
+ igt_plane_t **plane;
+ struct igt_fb *fb;
} data_t;
typedef struct {
@@ -92,20 +92,32 @@ static unsigned int get_vblank(int fd, int pipe, unsigned
int flags)
/*
* Common code across all tests, acting on data_t
*/
-static void test_init(data_t *data, enum pipe pipe)
+static void test_init(data_t *data, enum pipe pipe, int max_planes)
{
data->pipe_crc = igt_pipe_crc_new(pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+
+ data->plane = malloc(max_planes * sizeof(data->plane));
+ igt_assert_f(data->plane != NULL, "Failed to allocate memory for
planes\n");
+
+ data->fb = malloc(max_planes * sizeof(struct igt_fb));
+ igt_assert_f(data->fb != NULL, "Failed to allocate memory for FBs\n");
}
static void test_fini(data_t *data, igt_output_t *output, int max_planes)
{
- for (int i = IGT_PLANE_PRIMARY; i <= max_planes; i++)
- igt_plane_set_fb(data->plane[i], NULL);
+ for (int i = 0; i <= max_planes; i++) {
+ igt_plane_t *plane = data->plane[i];
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+ continue;
+ igt_plane_set_fb(plane, NULL);
+ }
/* reset the constraint on the pipe */
igt_output_set_pipe(output, PIPE_ANY);
igt_pipe_crc_free(data->pipe_crc);
+ free(data->plane);
+ free(data->fb);
}
static void
@@ -113,11 +125,13 @@ test_grab_crc(data_t *data, igt_output_t *output, enum
pipe pipe, bool atomic,
color_t *color, uint64_t tiling, igt_crc_t *crc /* out */)
{
drmModeModeInfo *mode;
+ igt_plane_t *primary;
int ret, n;
igt_output_set_pipe(output, pipe);
- data->plane[IGT_PLANE_PRIMARY] = igt_output_get_plane(output,
IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+ data->plane[primary->index] = primary;
mode = igt_output_get_mode(output);
@@ -125,9 +139,9 @@ test_grab_crc(data_t *data, igt_output_t *output, enum pipe
pipe, bool atomic,
DRM_FORMAT_XRGB,
LOCAL_DRM_FORMAT_MOD_NONE,
color->red, color->green, color->blue,
- &data->fb[IGT_PLANE_PRIMARY]);
+ &data->fb[primary->index]);
- igt_plane_set_fb(data->plane[IGT_PLANE_PRIMARY],
&data->fb[IGT_PLANE_PRIMARY]);
+ igt_plane_set_fb(data->plane[primary->index],
&data->fb[primary->index]);
ret = igt_display_try_commit2(&data->display,
atomic ? COMMIT_ATOMIC : COMMIT_LEGACY);
@@ -150,29 +164,35 @@ test_grab_crc(data_t *data, igt_output_t *output, enum
pipe pipe, bool atomic,
*/
static void
-create_fb_for_mode_position(data_t *data, drmModeModeInfo *mode,
+create_fb_for_mode_position(data_t *data, igt_output_t *output,
drmModeModeInfo *mode,
color_t *color, int *rect_x, int *rect_y,
int *rect_w, int *rect_h, uint64_t tiling,
int max_planes)
{
unsigned int fb_id;
cairo_t *cr;
+ igt_plane_t *primary;
+
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
fb_id = igt_create_fb(data->drm_fd,
mode->hdisplay, mode->vdisplay,
DRM_FORMAT_XRGB,
tiling,
- &data->fb[IGT_PLANE_PRIMARY]);
+ &data->fb[primary->index]);
igt_assert(fb_id);
- cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[IGT_PLANE_PRIMARY]);
+ cr = igt_get_cairo_ctx(data->drm_fd, &data->fb[primary->index]);
igt_paint_color(cr, rect_x[0], rect_y[0],
mode->hdisplay, mode->vdisplay,
color->red, color->green, color->blue);
- for (int i = IGT_PLANE_2; i <= max_planes; i++)
+ for (int i = 0; i <= max_planes; i++) {
+ if (data->plane[i]->type == DRM_PLANE_TYPE_PRIMARY)
+ continue;
igt_paint_color(cr, rect_x[i], rect_y[i],
rect_w[i], rect_h[i], 0.0, 0.0, 0.0);
+ }
igt_assert(cairo_status(cr) == 0);
cairo_destroy(cr);
@@ -180,
[Intel-gfx] [PATCH i-g-t rfc 14/29] tests/kms_mmap_write_crc: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_mmap_write_crc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_mmap_write_crc.c b/tests/kms_mmap_write_crc.c index fce0471d..fcfba154 100644 --- a/tests/kms_mmap_write_crc.c +++ b/tests/kms_mmap_write_crc.c @@ -184,7 +184,7 @@ static bool prepare_crtc(data_t *data) DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE, 1.0, 1.0, 1.0, &data->fb[0]); - data->primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + data->primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(data->primary, &data->fb[0]); igt_display_commit(display); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 25/29] tests/kms_rotation_crc: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_rotation_crc.c | 63
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 796b4486..5e87d4f4 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -97,16 +97,17 @@ static void commit_crtc(data_t *data, igt_output_t *output,
igt_plane_t *plane)
* we create an fb covering the crtc and call commit
*/
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, &data->fb_modeset);
igt_display_commit(display);
igt_plane_set_fb(plane, &data->fb);
- if (!plane->is_cursor)
+ if (plane->type != DRM_PLANE_TYPE_CURSOR)
igt_plane_set_position(plane, data->pos_x, data->pos_y);
- if (plane->is_primary || plane->is_cursor)
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY ||
+ plane->type == DRM_PLANE_TYPE_CURSOR)
commit = COMMIT_UNIVERSAL;
if (data->display.is_atomic)
@@ -153,7 +154,7 @@ static void prepare_crtc(data_t *data, igt_output_t
*output, enum pipe pipe,
tiling = data->override_tiling ?
data->override_tiling : LOCAL_I915_FORMAT_MOD_Y_TILED;
w = h = mode->vdisplay;
- } else if (plane->is_cursor) {
+ } else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
pixel_format = data->override_fmt ?
data->override_fmt : DRM_FORMAT_ARGB;
w = h = 128;
@@ -205,10 +206,10 @@ static void cleanup_crtc(data_t *data, igt_output_t
*output, igt_plane_t *plane)
igt_remove_fb(data->gfx_fd, &data->fb_flip);
/* XXX: see the note in prepare_crtc() */
- if (!plane->is_primary) {
+ if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
igt_plane_t *primary;
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
}
@@ -235,7 +236,7 @@ static void wait_for_pageflip(int fd)
igt_assert(drmHandleEvent(fd, &evctx) == 0);
}
-static void test_plane_rotation(data_t *data, enum igt_plane plane_type)
+static void test_plane_rotation(data_t *data, int plane_type)
{
igt_display_t *display = &data->display;
igt_output_t *output;
@@ -246,10 +247,10 @@ static void test_plane_rotation(data_t *data, enum
igt_plane plane_type)
unsigned int flip_count;
int ret;
- if (plane_type == IGT_PLANE_PRIMARY || plane_type == IGT_PLANE_CURSOR)
+ if (plane_type == DRM_PLANE_TYPE_PRIMARY || plane_type ==
DRM_PLANE_TYPE_CURSOR)
commit = COMMIT_UNIVERSAL;
- if (plane_type == IGT_PLANE_CURSOR)
+ if (plane_type == DRM_PLANE_TYPE_CURSOR)
igt_require(display->has_cursor_plane);
if (data->display.is_atomic)
@@ -261,7 +262,7 @@ static void test_plane_rotation(data_t *data, enum
igt_plane plane_type)
igt_output_set_pipe(output, pipe);
- plane = igt_output_get_plane(output, plane_type);
+ plane = igt_output_get_plane_type(output, plane_type);
igt_require(igt_plane_supports_rotation(plane));
prepare_crtc(data, output, pipe, plane);
@@ -320,7 +321,7 @@ static void test_plane_rotation(data_t *data, enum
igt_plane plane_type)
igt_require_f(valid_tests, "no valid crtc/connector combinations
found\n");
}
-static void test_plane_rotation_ytiled_obj(data_t *data, enum igt_plane
plane_type)
+static void test_plane_rotation_ytiled_obj(data_t *data, int plane_type)
{
igt_display_t *display = &data->display;
uint64_t tiling = LOCAL_I915_FORMAT_MOD_Y_TILED;
@@ -337,13 +338,13 @@ static void test_plane_rotation_ytiled_obj(data_t *data,
enum igt_plane plane_ty
igt_require(output != NULL && output->valid == true);
- plane = igt_output_get_plane(output, plane_type);
+ plane = igt_output_get_plane_type(output, plane_type);
igt_require(igt_plane_supports_rotation(plane));
- if (plane_type == IGT_PLANE_PRIMARY || plane_type == IGT_PLANE_CURSOR)
+ if (plane_type == DRM_PLANE_TYPE_PRIMARY || plane_type ==
DRM_PLANE_TYPE_CURSOR)
commit = COMMIT_UNIVERSAL;
- if (plane_type == IGT_PLANE_CURSOR)
+ if (plane_type == DRM_PLANE_TYPE_CURSOR)
igt_require(display->has_cursor_plane);
if (data->display.is_atomic)
@@ -386,7 +387,7 @@ static void test_plane_rotation_ytiled_obj(data_t *data,
enum igt_plane plane_ty
igt_assert
[Intel-gfx] [PATCH i-g-t rfc 29/29] tests/prime_mmap_kms: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/prime_mmap_kms.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/prime_mmap_kms.c b/tests/prime_mmap_kms.c index 15e310fc..5ef882c3 100644 --- a/tests/prime_mmap_kms.c +++ b/tests/prime_mmap_kms.c @@ -175,7 +175,7 @@ static bool prepare_crtc(gpu_process_t *gpu) DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE, 1.0, 1.0, 1.0, &gpu->fb); - gpu->primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + gpu->primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(gpu->primary, &gpu->fb); igt_display_commit(display); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 26/29] tests/kms_sink_crc_basic: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_sink_crc_basic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kms_sink_crc_basic.c b/tests/kms_sink_crc_basic.c index c332eb1e..953ead10 100644 --- a/tests/kms_sink_crc_basic.c +++ b/tests/kms_sink_crc_basic.c @@ -138,7 +138,7 @@ static void run_test(data_t *data) 1.0, 0.0, 0.0, &data->fb_red); - data->primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + data->primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); basic_sink_crc_check(data); return; -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 28/29] tests/kms_vblank: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe. Signed-off-by: Robert Foss --- tests/kms_vblank.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c index 9bc49296..73b3b2ad 100644 --- a/tests/kms_vblank.c +++ b/tests/kms_vblank.c @@ -83,7 +83,7 @@ static bool prepare_crtc(data_t *data, int fd, igt_output_t *output) 0.0, 0.0, 0.0, &data->primary_fb); - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, &data->primary_fb); igt_display_commit(display); @@ -100,7 +100,7 @@ static void cleanup_crtc(data_t *data, int fd, igt_output_t *output) igt_remove_fb(fd, &data->primary_fb); - primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY); + primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY); igt_plane_set_fb(primary, NULL); igt_output_set_pipe(output, PIPE_ANY); -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH i-g-t rfc 27/29] tests/kms_universal_plane: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_universal_plane.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tests/kms_universal_plane.c b/tests/kms_universal_plane.c
index b9e0651b..360211c1 100644
--- a/tests/kms_universal_plane.c
+++ b/tests/kms_universal_plane.c
@@ -148,16 +148,16 @@ functional_test_pipe(data_t *data, enum pipe pipe,
igt_output_t *output)
* boolean and show up in userspace as the wrong type.
*/
for (i = 0; i < display->pipes[pipe].n_planes; i++)
- if (display->pipes[pipe].planes[i].is_primary)
+ if (display->pipes[pipe].planes[i].type ==
DRM_PLANE_TYPE_PRIMARY)
num_primary++;
- else if (display->pipes[pipe].planes[i].is_cursor)
+ else if (display->pipes[pipe].planes[i].type ==
DRM_PLANE_TYPE_CURSOR)
num_cursor++;
igt_assert_eq(num_primary, 1);
igt_assert_lte(num_cursor, 1);
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
- sprite = igt_output_get_plane(output, IGT_PLANE_2);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+ sprite = igt_output_get_plane_type(output, DRM_PLANE_TYPE_OVERLAY);
if (!sprite) {
functional_test_fini(&test, output);
igt_skip("No sprite plane available\n");
@@ -369,7 +369,7 @@ sanity_test_pipe(data_t *data, enum pipe pipe, igt_output_t
*output)
sanity_test_init(&test, output, pipe);
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
/* Use legacy API to set a mode with a blue FB */
igt_plane_set_fb(primary, &test.blue_fb);
@@ -480,7 +480,7 @@ pageflip_test_pipe(data_t *data, enum pipe pipe,
igt_output_t *output)
pageflip_test_init(&test, output, pipe);
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
/* Use legacy API to set a mode with a blue FB */
igt_plane_set_fb(primary, &test.blue_fb);
@@ -602,8 +602,8 @@ cursor_leak_test_pipe(data_t *data, enum pipe pipe,
igt_output_t *output)
&cursor_fb[i]);
}
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
- cursor = igt_output_get_plane(output, IGT_PLANE_CURSOR);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+ cursor = igt_output_get_plane_type(output, DRM_PLANE_TYPE_CURSOR);
if (!primary || !cursor) {
cursor_leak_test_fini(data, output, &background_fb, cursor_fb);
igt_skip("Primary and/or cursor are unavailable\n");
@@ -706,7 +706,7 @@ gen9_test_pipe(data_t *data, enum pipe pipe, igt_output_t
*output)
gen9_test_init(&test, output, pipe);
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
/* Start with a full-screen primary plane */
igt_plane_set_fb(primary, &test.biggreen_fb);
--
2.11.0
___
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[Intel-gfx] [PATCH i-g-t rfc 16/29] tests/kms_panel_fitting: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_panel_fitting.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index 1b350762..e145a2df 100644
--- a/tests/kms_panel_fitting.c
+++ b/tests/kms_panel_fitting.c
@@ -76,10 +76,10 @@ static void prepare_crtc(data_t *data, igt_output_t
*output, enum pipe pipe,
* there's no way (that works) to light up a pipe with only a sprite
* plane enabled at the moment.
*/
- if (!plane->is_primary) {
+ if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
igt_plane_t *primary;
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, &data->fb1);
}
@@ -116,10 +116,10 @@ static void cleanup_crtc(data_t *data, igt_output_t
*output, igt_plane_t *plane)
data->fb_id3 = 0;
}
- if (!plane->is_primary) {
+ if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
igt_plane_t *primary;
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
}
@@ -174,7 +174,7 @@ static void test_panel_fitting(data_t *d)
/* Set up display to enable panel fitting */
mode->hdisplay = 640;
mode->vdisplay = 480;
- d->plane1 = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ d->plane1 = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
prepare_crtc(d, output, pipe, d->plane1, mode, COMMIT_LEGACY);
/* disable panel fitting */
@@ -189,7 +189,7 @@ static void test_panel_fitting(data_t *d)
prepare_crtc(d, output, pipe, d->plane1, &native_mode,
COMMIT_LEGACY);
/* Set up fb2->plane2 mapping. */
- d->plane2 = igt_output_get_plane(output, IGT_PLANE_2);
+ d->plane2 = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_OVERLAY);
igt_plane_set_fb(d->plane2, &d->fb2);
/* enable sprite plane */
@@ -226,8 +226,8 @@ test_panel_fitting_fastset(igt_display_t *display, const
enum pipe pipe, igt_out
igt_output_override_mode(output, &mode);
igt_output_set_pipe(output, pipe);
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
- sprite = igt_output_get_plane(output, IGT_PLANE_2);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+ sprite = igt_output_get_plane_type(output, DRM_PLANE_TYPE_OVERLAY);
igt_create_color_fb(display->drm_fd, mode.hdisplay, mode.vdisplay,
DRM_FORMAT_XRGB, LOCAL_DRM_FORMAT_MOD_NONE,
--
2.11.0
___
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[Intel-gfx] [PATCH i-g-t rfc 21/29] tests/kms_properties: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_properties.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/kms_properties.c b/tests/kms_properties.c
index 2650672d..a86371c0 100644
--- a/tests/kms_properties.c
+++ b/tests/kms_properties.c
@@ -38,7 +38,7 @@ static void prepare_pipe(igt_display_t *display, enum pipe
pipe, igt_output_t *o
igt_output_set_pipe(output, pipe);
- igt_plane_set_fb(igt_output_get_plane(output, IGT_PLANE_PRIMARY), fb);
+ igt_plane_set_fb(igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY), fb);
igt_display_commit2(display, display->is_atomic ? COMMIT_ATOMIC :
COMMIT_LEGACY);
}
@@ -163,8 +163,8 @@ static void run_plane_property_tests(igt_display_t
*display, enum pipe pipe, igt
prepare_pipe(display, pipe, output, &fb);
for_each_plane_on_pipe(display, pipe, plane) {
- igt_info("Testing plane properties on %s.%s (output: %s)\n",
-kmstest_pipe_name(pipe),
kmstest_plane_name(plane->index), output->name);
+ igt_info("Testing plane properties on %s.#%d-%s (output: %s)\n",
+kmstest_pipe_name(pipe), plane->index,
kmstest_plane_type_name(plane->type), output->name);
test_properties(display->drm_fd, DRM_MODE_OBJECT_PLANE,
plane->drm_plane->plane_id, atomic);
}
--
2.11.0
___
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[Intel-gfx] [PATCH i-g-t rfc 24/29] tests/kms_rmfb: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_rmfb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/kms_rmfb.c b/tests/kms_rmfb.c
index 17a3065a..5753d74c 100644
--- a/tests/kms_rmfb.c
+++ b/tests/kms_rmfb.c
@@ -83,7 +83,7 @@ test_rmfb(struct rmfb_data *data, igt_output_t *output, enum
pipe pipe, bool reo
* later on.
*/
for_each_plane_on_pipe(&data->display, pipe, plane) {
- if (plane->is_cursor) {
+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
igt_plane_set_fb(plane, &argb_fb);
igt_fb_set_size(&argb_fb, plane, cursor_width,
cursor_height);
igt_plane_set_size(plane, cursor_width, cursor_height);
--
2.11.0
___
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[Intel-gfx] [PATCH i-g-t rfc 20/29] tests/kms_plane_scaling: Add support for dynamic number of planes
Add changes reflecting the new support for dynamic number of planes per pipe.
Signed-off-by: Robert Foss
---
tests/kms_plane_scaling.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tests/kms_plane_scaling.c b/tests/kms_plane_scaling.c
index 368da09f..18ba86c9 100644
--- a/tests/kms_plane_scaling.c
+++ b/tests/kms_plane_scaling.c
@@ -85,10 +85,10 @@ static void prepare_crtc(data_t *data, igt_output_t
*output, enum pipe pipe,
* there's no way (that works) to light up a pipe with only a sprite
* plane enabled at the moment.
*/
- if (!plane->is_primary) {
+ if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
igt_plane_t *primary;
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, &data->fb1);
}
@@ -128,10 +128,10 @@ static void cleanup_crtc(data_t *data, igt_output_t
*output, igt_plane_t *plane)
data->fb_id3 = 0;
}
- if (!plane->is_primary) {
+ if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
igt_plane_t *primary;
- primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ primary = igt_output_get_plane_type(output,
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
}
@@ -207,7 +207,7 @@ static void test_plane_scaling(data_t *d)
igt_assert(d->fb_id3);
/* Set up display with plane 1 */
- d->plane1 = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+ d->plane1 = igt_output_get_plane(output, 1);
prepare_crtc(d, output, pipe, d->plane1, mode,
COMMIT_UNIVERSAL);
if (primary_plane_scaling) {
@@ -227,7 +227,7 @@ static void test_plane_scaling(data_t *d)
}
/* Set up fb2->plane2 mapping. */
- d->plane2 = igt_output_get_plane(output, IGT_PLANE_2);
+ d->plane2 = igt_output_get_plane(output, 2);
igt_plane_set_fb(d->plane2, &d->fb2);
/* 2nd plane windowed */
@@ -263,7 +263,7 @@ static void test_plane_scaling(data_t *d)
}
/* Set up fb3->plane3 mapping. */
- d->plane3 = igt_output_get_plane(output, IGT_PLANE_3);
+ d->plane3 = igt_output_get_plane(output, 3);
igt_plane_set_fb(d->plane3, &d->fb3);
/* 3rd plane windowed - no scaling */
--
2.11.0
___
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[Intel-gfx] [PATCH] dim: Update docs
- Remove branch overview, instead link to drm-intel and drm-misc pages. - Move quickstart to the top, to make it easier to find. - Make quickstart generic, we use dim for other stuff than drm-intel now. - s/drm-intel-rerere/drm-rerere/ - Remove the section about resolving conflicts, that's now explained in detail in the process pages. v2: Also eradicate dinq (Laurent). Signed-off-by: Daniel Vetter --- dim.rst | 138 1 file changed, 51 insertions(+), 87 deletions(-) diff --git a/dim.rst b/dim.rst index b9cb41a2ba5b..97b375e34e90 100644 --- a/dim.rst +++ b/dim.rst @@ -23,40 +23,66 @@ DESCRIPTION drm-intel maintainer script. -Branch Model - +Used to maintain drm-intel_ and drm-misc_ git repositories. -The dim flow has 3 main development branches: +.. _drm-intel: drm-intel.html +.. _drm-misc: drm-misc.html -- drm-intel-next-queued for feature work. This branch gets regularly pushed to - drm-intel-next and tagged and then sent on to the upstream drm-next branch - using *update-next*. The cut-off for the last pull request to drm-next is - around -rc5. After that point patches in drm-intel-next-queued already aim at - the next but one and not the next merge window. +QUICKSTART +== -- drm-intel-next-fixes is to collect fixes for the current merge window after - the -rc5 feature cut-off in drm-next. +For getting started grab the latest drm (drm-intel-maintainer) script from:: -- drm-intel-fixes is for fixes for the current -rc1 kernel. This is separate - from drm-intel-next-fixes since the merge window feature cutoff at -rc5 is a - few weeks ahead of the final release of the previous kernel. +http://cgit.freedesktop.org/drm-intel/tree/dim?h=maintainer-tools - There's separate tracking branches for inclusion into linux-next to make sure - that the feature work in drm-intel-next-queued aimed for the next but one - merge window doesn't cause unecassary conflicts in linux-next - in that case - only drm-intel-next-fixes is included in linux-next. The switchover happens - when drm-intel-fixes has caught up (in git terms: drm-intel-next-fixes is - direct ancestor of drm-intel-fixes). Therefore only roll drm-intel-fixes - forward once -rc1 is released +There's also a sample config file for ~/.dimrc:: -In addition there's 2 permanent topic branches: +http://cgit.freedesktop.org/drm-intel/tree/dimrc.sample?h=maintainer-tools -- topic/drm-misc carries core drm patches aimed at the next merge window. +Plus, there's bash completion in the same directory if you feel like using that. +Run:: -- topic/drm-fixes carries core drm fixes for the current -rc kernels. +$ dim help -Additional topic branches are created as needed using *create-branch* and -*remove-branch*. +for tons of details about how this thing works. Also see the git repository +specific pages for details on the patch merging process for each tree. Adjust +your .dimrc to match your setup and then run:: + +$ dim setup + +This will also check out the latest maintainer-tools branches, so please replace +the dim you just downloaded with a symlink after this step. And by the way, if +you have improvements for dim, please submit them to intel-gfx. + +You should now have a main repository for patch application. The directory +corresponding to this repository is defined by DIM_DRM_INTEL in your .dimrc. +You should also have directories called maintainer-tools, drm-tip (for +rebuilding the tree), and drm-rerere for some dim-internal book-keeping. + +If someone else has pushed patches first resync using:: + + $ dim update-branches + +Since dim supports lots of different branches in different repositories you +first need to check out the right branch using:: + + $ dim checkout + +Applying patches is done in the main repository with:: + +$ cat patch.mbox | dim apply-branch + +This works like a glorified version of git apply-mbox and does basic patch +checking and adds stuff like patchwork links of the merged patch. It is +preferred to use the patch email file instead of the original patch file since +it contains some interesting headers like the message ID. When you're happy +(remember that with a shared tree any mistake is permanent and there's no +rebasing) push out the new tree with:: + +$ dim push-branch + +This will also rebuild a new drm-tip integration tree. For historical reasons +there's shortcut for the drm-intel specific branches for most of these commands. OPTIONS === @@ -375,68 +401,6 @@ DIM_TEMPLATE_SIGNATURE -- Path to a file containing a signature template for pull request mails. -QUICKSTART -== - -For getting started grab the latest drm (drm-intel-maintainer) script from:: - -http://cgit.freedesktop.org/drm-intel/tree/dim?h=maintainer-tools - -There's also a sample config file for ~/.dimrc:: - -http://cgit.freedesktop.org/drm-intel/tree/dimrc.sampl
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev2)
== Series Details == Series: series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev2) URL : https://patchwork.freedesktop.org/series/17829/ State : failure == Summary == Series 17829v2 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17829/revisions/2/mbox/ Test drv_module_reload: Subgroup basic-reload-final: pass -> TIMEOUT(fi-skl-6260u) Test gem_basic: Subgroup bad-close: pass -> INCOMPLETE (fi-skl-6260u) Test gem_busy: Subgroup basic-hang-default: pass -> DMESG-WARN (fi-bxt-t5700) pass -> DMESG-WARN (fi-bxt-j4205) pass -> DMESG-WARN (fi-skl-6770hq) pass -> DMESG-WARN (fi-skl-6700k) pass -> DMESG-WARN (fi-skl-6700hq) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-bxt-j4205) pass -> INCOMPLETE (fi-skl-6770hq) Subgroup basic-s4-devices: pass -> INCOMPLETE (fi-skl-6700k) Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-a: pass -> INCOMPLETE (fi-skl-6700hq) fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:82 pass:69 dwarn:1 dfail:0 fail:0 skip:11 fi-bxt-t5700 total:82 pass:68 dwarn:1 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:9pass:7dwarn:0 dfail:0 fail:0 skip:0 fi-skl-6700hqtotal:208 pass:187 dwarn:1 dfail:0 fail:0 skip:19 fi-skl-6700k total:83 pass:67 dwarn:4 dfail:0 fail:0 skip:11 fi-skl-6770hqtotal:82 pass:77 dwarn:1 dfail:0 fail:0 skip:3 fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 b69fc4c941bef6d10750ce3f07daedfffc7017d1 drm-tip: 2017y-01m-11d-17h-30m-02s UTC integration manifest c4d7f54 HAX enable guc submission for CI cf4330e drm/i915/scheduler: emulate a scheduler for guc 21d5983 drm/i915: Invalidate the guc ggtt TLB upon insertion == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3488/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/37] drm/i915: Provide a hook for selftests
Some pieces of code are independent of hardware but are very tricky to
exercise through the normal userspace ABI or via debugfs hooks. Being
able to create mock unit tests and execute them through CI is vital.
Start by adding a central point where we can execute unit tests and
a parameter to enable them. This is disabled by default as the
expectation is that these tests will occasionally explode.
To facilitate integration with igt, any parameter beginning with
i915.igt__ is interpreted as a subtest executable independently via
igt/drv_selftest.
Two classes of selftests are recognised: mock unit tests and integration
tests. Mock unit tests are run as soon as the module is loaded, before
the device is probed. At that point there is no driver instantiated and
all hw interactions must be "mocked". This is very useful for writing
universal tests to exercise code not typically run on a broad range of
architectures. Alternatively, you can hook into the live selftests and
run when the device has been instantiated - hw interactions are real.
v2: Add a macro for compiling conditional code for mock objects inside
real objects.
v3: Differentiate between mock unit tests and late integration test.
v4: List the tests in natural order, use igt to sort after modparam.
v5: s/late/live/
v6: s/unsigned long/unsigned int/
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin #v1
---
drivers/gpu/drm/i915/Kconfig.debug | 16 ++
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/i915_pci.c| 19 +-
drivers/gpu/drm/i915/i915_selftest.h | 91 +
.../gpu/drm/i915/selftests/i915_live_selftests.h | 11 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 11 +
drivers/gpu/drm/i915/selftests/i915_selftest.c | 226 +
tools/testing/selftests/drivers/gpu/i915.sh| 1 +
8 files changed, 377 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/i915_selftest.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_live_selftests.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
create mode 100644 drivers/gpu/drm/i915/selftests/i915_selftest.c
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 598551dbf62c..a4d8cfd77c3c 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -26,6 +26,7 @@ config DRM_I915_DEBUG
select DRM_DEBUG_MM if DRM=y
select DRM_DEBUG_MM_SELFTEST
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
+ select DRM_I915_SELFTEST
default n
help
Choose this option to turn on extra driver debugging that may affect
@@ -59,3 +60,18 @@ config DRM_I915_SW_FENCE_DEBUG_OBJECTS
Recommended for driver developers only.
If in doubt, say "N".
+
+config DRM_I915_SELFTEST
+ bool "Enable selftests upon driver load"
+ depends on DRM_I915
+ default n
+ select PRIME_NUMBERS
+ help
+ Choose this option to allow the driver to perform selftests upon
+ loading; also requires the i915.selftest=1 module parameter. To
+ exit the module after running the selftests (i.e. to prevent normal
+ module initialisation afterwards) use i915.selftest=-1.
+
+ Recommended for driver developers only.
+
+ If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5196509e71cf..c9d1554de35d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -3,6 +3,7 @@
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) := -Werror
+subdir-ccflags-$(CONFIG_DRM_I915_SELFTEST) += -I$(src) -I$(src)/selftests
subdir-ccflags-y += \
$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
@@ -114,6 +115,8 @@ i915-y += dvo_ch7017.o \
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
+i915-$(CONFIG_DRM_I915_SELFTEST) += \
+ selftests/i915_selftest.o
# virtual gpu code
i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ecb487b5356f..b3bf9474f081 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -27,6 +27,7 @@
#include
#include "i915_drv.h"
+#include "i915_selftest.h"
#define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
@@ -476,6 +477,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
{
struct intel_device_info *intel_info =
(struct intel_device_info *) ent->driver_data;
+ int err;
if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
DRM_INFO("The driver support for your hardware in this kernel
version is alpha quality\n"
@@ -499,7 +501,
[Intel-gfx] Selftests
A small smattering of selftests. Coverage is getting better, but still a long way from providing coverage of every path I have planned. :| The tests we do have do nicely demonstrated the ease at which some in-depth testing can be done in the kernel, some that would be impossible from userspace. (But uabi still requires thorough testing of its own, ofc.) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/37] drm: Provide a driver hook for drm_dev_release()
Some state is coupled into the device lifetime outside of the
load/unload timeframe and requires teardown during final unreference
from drm_dev_release(). For example, dmabufs hold both a device and
module reference and may live longer than expected (i.e. the current
pattern of the driver tearing down its state and then releasing a
reference to the drm device) and yet touch driver private state when
destroyed.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_drv.c | 3 +++
include/drm/drm_drv.h | 9 +
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 1b11ab628da7..a150f0c6a299 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -598,6 +598,9 @@ static void drm_dev_release(struct kref *ref)
{
struct drm_device *dev = container_of(ref, struct drm_device, ref);
+ if (dev->driver->release)
+ dev->driver->release(dev);
+
if (drm_core_check_feature(dev, DRIVER_GEM))
drm_gem_destroy(dev);
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 34ece393c639..dfddd8c15b62 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -103,6 +103,15 @@ struct drm_driver {
*
*/
void (*unload) (struct drm_device *);
+
+ /**
+* @release:
+*
+* Optional callback for destroying device state after the final
+* reference is released, i.e. the device is being destroyed.
+*/
+ void (*release) (struct drm_device *);
+
int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file
*file_priv);
int (*dma_quiescent) (struct drm_device *);
int (*context_dtor) (struct drm_device *dev, int context);
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/37] drm/i915: Add unit tests for the breadcrumb rbtree, completion
Second retroactive test, make sure that the waiters are removed from the
global wait-tree when their seqno completes.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 107 +
drivers/gpu/drm/i915/selftests/mock_engine.h | 6 ++
2 files changed, 113 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
index 23b09fd5d3aa..e9dff6eee323 100644
--- a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
@@ -64,6 +64,27 @@ static int check_rbtree(struct intel_engine_cs *engine,
return 0;
}
+static int check_completion(struct intel_engine_cs *engine,
+ const unsigned long *bitmap,
+ const struct intel_wait *waiters,
+ const int count)
+{
+ int n;
+
+ for (n = 0; n < count; n++) {
+ if (intel_wait_complete(&waiters[n]) != !!test_bit(n, bitmap))
+ continue;
+
+ pr_err("waiter[%d, seqno=%d] is %s, but expected %s\n",
+ n, waiters[n].seqno,
+ intel_wait_complete(&waiters[n]) ? "complete" : "active",
+ test_bit(n, bitmap) ? "active" : "complete");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int check_rbtree_empty(struct intel_engine_cs *engine)
{
struct intel_breadcrumbs *b = &engine->breadcrumbs;
@@ -157,10 +178,96 @@ static int igt_random_insert_remove(void *arg)
return err;
}
+static int igt_insert_complete(void *arg)
+{
+ const u32 seqno_bias = 0x1000;
+ struct intel_engine_cs *engine = arg;
+ struct intel_wait *waiters;
+ const int count = 4096;
+ unsigned long *bitmap;
+ int err = -ENOMEM;
+ int n, m;
+
+ mock_engine_reset(engine);
+
+ waiters = drm_malloc_gfp(count, sizeof(*waiters), GFP_TEMPORARY);
+ if (!waiters)
+ goto out_engines;
+
+ bitmap = kcalloc(DIV_ROUND_UP(count, BITS_PER_LONG), sizeof(*bitmap),
+GFP_TEMPORARY);
+ if (!bitmap)
+ goto out_waiters;
+
+ for (n = 0; n < count; n++) {
+ intel_wait_init(&waiters[n], n + seqno_bias);
+ intel_engine_add_wait(engine, &waiters[n]);
+ __set_bit(n, bitmap);
+ }
+ err = check_rbtree(engine, bitmap, waiters, count);
+ if (err)
+ goto err;
+
+ /* On each step, we advance the seqno so that several waiters are then
+* complete (we increase the seqno by increasingly larger values to
+* retire more and more waiters at once). All retired waiters should
+* be woken and removed from the rbtree, and so that we check.
+*/
+ for (n = 0; n < count; n = m) {
+ int seqno = 2 * n;
+
+ GEM_BUG_ON(find_first_bit(bitmap, count) != n);
+
+ if (intel_wait_complete(&waiters[n])) {
+ pr_err("waiter[%d, seqno=%d] completed too early\n",
+ n, waiters[n].seqno);
+ err = -EINVAL;
+ goto err;
+ }
+
+ /* complete the following waiters */
+ mock_seqno_advance(engine, seqno + seqno_bias);
+ for (m = n; m <= seqno; m++) {
+ if (m == count)
+ break;
+
+ GEM_BUG_ON(!test_bit(m, bitmap));
+ __clear_bit(m, bitmap);
+ }
+
+ intel_engine_remove_wait(engine, &waiters[n]);
+ RB_CLEAR_NODE(&waiters[n].node);
+
+ err = check_rbtree(engine, bitmap, waiters, count);
+ if (err) {
+ pr_err("rbtree corrupt after seqno advance to %d\n",
+ seqno + seqno_bias);
+ goto err;
+ }
+
+ err = check_completion(engine, bitmap, waiters, count);
+ if (err) {
+ pr_err("completions after seqno advance to %d failed\n",
+ seqno + seqno_bias);
+ goto err;
+ }
+ }
+
+ err = check_rbtree_empty(engine);
+err:
+ kfree(bitmap);
+out_waiters:
+ drm_free_large(waiters);
+out_engines:
+ mock_engine_flush(engine);
+ return err;
+}
+
int intel_breadcrumbs_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_random_insert_remove),
+ SUBTEST(igt_insert_complete),
};
struct intel_engine_cs *engine;
int err;
diff --git a/drivers/gpu/drm/i915/selftests/mock_engine.h
b/drivers/gpu/drm/i915/selftests/mock_engine.h
index 0ae9a94aaa1e..9cfe9
[Intel-gfx] [PATCH 04/37] drm/i915: Add unit tests for the breadcrumb rbtree, insert/remove
First retroactive test, make sure that the waiters are in global seqno
order after random inserts and removals.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/intel_breadcrumbs.c | 21 +++
drivers/gpu/drm/i915/intel_engine_cs.c | 4 +
drivers/gpu/drm/i915/intel_ringbuffer.h| 2 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_random.c | 63
drivers/gpu/drm/i915/selftests/i915_random.h | 47 ++
drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 176 +
drivers/gpu/drm/i915/selftests/mock_engine.c | 55 +++
drivers/gpu/drm/i915/selftests/mock_engine.h | 32
10 files changed, 402 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_random.c
create mode 100644 drivers/gpu/drm/i915/selftests/i915_random.h
create mode 100644 drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_engine.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_engine.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c9d1554de35d..b5da9aa98764 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -116,6 +116,7 @@ i915-y += dvo_ch7017.o \
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
+ selftests/i915_random.o \
selftests/i915_selftest.o
# virtual gpu code
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index fcfa423d08bd..5682c8aa8064 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -109,6 +109,18 @@ static void __intel_breadcrumbs_enable_irq(struct
intel_breadcrumbs *b)
if (b->rpm_wakelock)
return;
+ if (I915_SELFTEST_ONLY(b->mock)) {
+ /* For our mock objects we want to avoid interaction
+* with the real hardware (which is not set up). So
+* we simply pretend we have enabled the powerwell
+* and the irq, and leave it up to the mock
+* implementation to call intel_engine_wakeup()
+* itself when it wants to simulate a user interrupt,
+*/
+ b->rpm_wakelock = true;
+ return;
+ }
+
/* Since we are waiting on a request, the GPU should be busy
* and should have its own rpm reference. For completeness,
* record an rpm reference for ourselves to cover the
@@ -143,6 +155,11 @@ static void __intel_breadcrumbs_disable_irq(struct
intel_breadcrumbs *b)
if (!b->rpm_wakelock)
return;
+ if (I915_SELFTEST_ONLY(b->mock)) {
+ b->rpm_wakelock = false;
+ return;
+ }
+
if (b->irq_enabled) {
irq_disable(engine);
b->irq_enabled = false;
@@ -661,3 +678,7 @@ unsigned int intel_breadcrumbs_busy(struct drm_i915_private
*i915)
return mask;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/intel_breadcrumbs.c"
+#endif
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 97bbbc3d6aa8..c6332096d870 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -482,3 +482,7 @@ void intel_engine_get_instdone(struct intel_engine_cs
*engine,
break;
}
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/mock_engine.c"
+#endif
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 79c2b8d72322..eba238095497 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -5,6 +5,7 @@
#include "i915_gem_batch_pool.h"
#include "i915_gem_request.h"
#include "i915_gem_timeline.h"
+#include "i915_selftest.h"
#define I915_CMD_HASH_ORDER 9
@@ -244,6 +245,7 @@ struct intel_engine_cs {
bool irq_enabled : 1;
bool rpm_wakelock : 1;
+ I915_SELFTEST_DECLARE(bool mock : 1);
} breadcrumbs;
/*
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 5f0bdda42ed8..80458e2a2b04 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -10,3 +10,4 @@
*/
selftest(sanitycheck, i915_mock_sanitycheck) /* keep first (igt selfcheck) */
selftest(scatterlist, scatterlist_mock_selftests)
+selftest(breadcrumbs, intel_breadcrumbs_mock_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_random.c
b/drivers/gpu/drm/i915/selftests/i915_rand
[Intel-gfx] [PATCH 09/37] drm/i915: Mock infrastructure for request emission
Create a fake engine that runs requests using a timer to simulate hw.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c| 4 +
drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 11 +-
drivers/gpu/drm/i915/selftests/mock_context.c | 70 +
drivers/gpu/drm/i915/selftests/mock_context.h | 34
drivers/gpu/drm/i915/selftests/mock_engine.c | 172 +++--
drivers/gpu/drm/i915/selftests/mock_engine.h | 18 ++-
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 95 +++-
drivers/gpu/drm/i915/selftests/mock_gem_device.h | 1 +
drivers/gpu/drm/i915/selftests/mock_request.c | 44 ++
drivers/gpu/drm/i915/selftests/mock_request.h | 44 ++
10 files changed, 475 insertions(+), 18 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/mock_context.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_context.h
create mode 100644 drivers/gpu/drm/i915/selftests/mock_request.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_request.h
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index fbd3b8ecbe20..91551b01a62c 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1185,3 +1185,7 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev,
return 0;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/mock_context.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
index bee86470a91d..2742103247c0 100644
--- a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
@@ -25,6 +25,7 @@
#include "i915_random.h"
#include "i915_selftest.h"
+#include "mock_gem_device.h"
#include "mock_engine.h"
static int check_rbtree(struct intel_engine_cs *engine,
@@ -440,15 +441,15 @@ int intel_breadcrumbs_mock_selftests(void)
SUBTEST(igt_insert_complete),
SUBTEST(igt_wakeup),
};
- struct intel_engine_cs *engine;
+ struct drm_i915_private *i915;
int err;
- engine = mock_engine("mock");
- if (!engine)
+ i915 = mock_gem_device();
+ if (!i915)
return -ENOMEM;
- err = i915_subtests(tests, engine);
- kfree(engine);
+ err = i915_subtests(tests, i915->engine[RCS]);
+ drm_dev_unref(&i915->drm);
return err;
}
diff --git a/drivers/gpu/drm/i915/selftests/mock_context.c
b/drivers/gpu/drm/i915/selftests/mock_context.c
new file mode 100644
index ..5098dbbc81d5
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/mock_context.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "mock_context.h"
+#include "mock_gtt.h"
+
+struct i915_gem_context *
+mock_context(struct drm_i915_private *i915,
+const char *name)
+{
+ struct i915_gem_context *ctx;
+ int ret;
+
+ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return NULL;
+
+ kref_init(&ctx->ref);
+ INIT_LIST_HEAD(&ctx->link);
+ ctx->name = name ? kstrdup(name, GFP_KERNEL) : NULL;
+ ctx->i915 = i915;
+
+ ret = ida_simple_get(&i915->context_hw_ida,
+0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+ if (ret < 0) {
+ kfree(ctx);
+ return NULL;
+ }
+ ctx->hw_id = ret;
+
+ if (name) {
+ ctx->ppgtt = mock_ppgtt(i915, name);
+ if (!ctx->ppgtt) {
+ kfree(ctx);
+ return NULL;
+ }
+ }
+
+ return ctx;
+}
+
+void mock_context_close(struct i915_gem_context *ctx)
+{
+ i915_gem_context_
[Intel-gfx] [PATCH 10/37] drm/i915: Create a fake object for testing huge allocations
We would like to be able to exercise huge allocations even on memory
constrained devices. To do this we create an object that allocates only
a few pages and remaps them across its whole range - each page is reused
multiple times. We can therefore pretend we are rendering into a much
larger object.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_object.h | 20 ++--
drivers/gpu/drm/i915/selftests/huge_gem_object.c | 130 +++
drivers/gpu/drm/i915/selftests/huge_gem_object.h | 33 ++
4 files changed, 176 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/huge_gem_object.c
create mode 100644 drivers/gpu/drm/i915/selftests/huge_gem_object.h
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ddc85a7c8d82..07b4ba3df94c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4897,4 +4897,5 @@ i915_gem_object_get_dma_address(struct
drm_i915_gem_object *obj,
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/scatterlist.c"
#include "selftests/mock_gem_device.c"
+#include "selftests/huge_gem_object.c"
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem_object.h
b/drivers/gpu/drm/i915/i915_gem_object.h
index 290eaa7fc9eb..4114cc8a0b9b 100644
--- a/drivers/gpu/drm/i915/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/i915_gem_object.h
@@ -167,14 +167,18 @@ struct drm_i915_gem_object {
/** Record of address bit 17 of each page at last unbind. */
unsigned long *bit_17;
- struct i915_gem_userptr {
- uintptr_t ptr;
- unsigned read_only :1;
-
- struct i915_mm_struct *mm;
- struct i915_mmu_object *mmu_object;
- struct work_struct *work;
- } userptr;
+ union {
+ struct i915_gem_userptr {
+ uintptr_t ptr;
+ unsigned read_only :1;
+
+ struct i915_mm_struct *mm;
+ struct i915_mmu_object *mmu_object;
+ struct work_struct *work;
+ } userptr;
+
+ unsigned long scratch;
+ };
/** for phys allocated objects */
struct drm_dma_handle *phys_handle;
diff --git a/drivers/gpu/drm/i915/selftests/huge_gem_object.c
b/drivers/gpu/drm/i915/selftests/huge_gem_object.c
new file mode 100644
index ..df00e14ce8bc
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/huge_gem_object.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "huge_gem_object.h"
+
+static void huge_free_pages(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ unsigned long nreal = obj->scratch / PAGE_SIZE;
+ struct scatterlist *sg;
+
+ for (sg = pages->sgl; sg && nreal--; sg = sg_next(sg))
+ __free_page(sg_page(sg));
+
+ sg_free_table(pages);
+ kfree(pages);
+}
+
+static struct sg_table *
+huge_get_pages(struct drm_i915_gem_object *obj)
+{
+#define GFP (GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY)
+ const unsigned long nreal = obj->scratch / PAGE_SIZE;
+ const unsigned long npages = obj->base.size / PAGE_SIZE;
+ struct scatterlist *sg, *src, *end;
+ struct sg_table *pages;
+ unsigned long n;
+
+ pages = kmalloc(sizeof(*pages), GFP);
+ if (!pages)
+ return ERR_PTR(-ENOMEM);
+
+ if (sg_alloc_table(pages, npages, GFP)) {
+ kfree(pages);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ sg = pages->sgl;
+ for (n = 0; n < nreal; n++) {
+ struct page *page;
+
+ page = alloc_page(GFP | __GFP_HIGHMEM);
+ if (!page) {
+
[Intel-gfx] [PATCH 03/37] drm/i915: Add some selftests for sg_table manipulation
Start exercising the scattergather lists, especially looking at
iteration after coalescing.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c| 11 +-
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/scatterlist.c | 255 +
3 files changed, 264 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/scatterlist.c
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4c6d40e28cf5..e88541b5b72b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2219,17 +2219,17 @@ void __i915_gem_object_put_pages(struct
drm_i915_gem_object *obj,
mutex_unlock(&obj->mm.lock);
}
-static void i915_sg_trim(struct sg_table *orig_st)
+static bool i915_sg_trim(struct sg_table *orig_st)
{
struct sg_table new_st;
struct scatterlist *sg, *new_sg;
unsigned int i;
if (orig_st->nents == orig_st->orig_nents)
- return;
+ return false;
if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
- return;
+ return false;
new_sg = new_st.sgl;
for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
@@ -2242,6 +2242,7 @@ static void i915_sg_trim(struct sg_table *orig_st)
sg_free_table(orig_st);
*orig_st = new_st;
+ return true;
}
static struct sg_table *
@@ -4892,3 +4893,7 @@ i915_gem_object_get_dma_address(struct
drm_i915_gem_object *obj,
sg = i915_gem_object_get_sg(obj, n, &offset);
return sg_dma_address(sg) + (offset << PAGE_SHIFT);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/scatterlist.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 69e97a2ba4a6..5f0bdda42ed8 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -9,3 +9,4 @@
* Tests are executed in order by igt/drv_selftest
*/
selftest(sanitycheck, i915_mock_sanitycheck) /* keep first (igt selfcheck) */
+selftest(scatterlist, scatterlist_mock_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/scatterlist.c
b/drivers/gpu/drm/i915/selftests/scatterlist.c
new file mode 100644
index ..1573be8961bf
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/scatterlist.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include
+
+#include "i915_selftest.h"
+
+#define PFN_BIAS (1 << 10)
+
+struct pfn_table {
+ struct sg_table st;
+ unsigned long start, end;
+};
+
+static noinline int expect_pfn_sg(struct pfn_table *pt, const char *who)
+{
+ struct scatterlist *sg;
+ unsigned long pfn, n;
+
+ pfn = pt->start;
+ for_each_sg(pt->st.sgl, sg, pt->st.nents, n) {
+ struct page *page = sg_page(sg);
+
+ if (page_to_pfn(page) != pfn) {
+ pr_err("%s left pages out of order, expected pfn %lu,
found pfn %lu (using for_each_sg)\n",
+ who, pfn, page_to_pfn(page));
+ return -EINVAL;
+ }
+
+ if (sg->length != (n + 1) * PAGE_SIZE) {
+ pr_err("%s: %s copied wrong sg length, expected size
%lu, found %u (using for_each_sg)\n",
+ __func__, who, (n + 1) * PAGE_SIZE, sg->length);
+ return -EINVAL;
+ }
+
+ cond_resched();
+ if (signal_pending(current))
+ return -EINTR;
+
+ pfn += n + 1;
+ }
+ if (pfn != pt->end) {
+ pr_err("%s: %s finished on wrong pfn, expected %l
[Intel-gfx] [PATCH 14/37] drm/i915: Simple selftest to exercise live requests
Just create several batches of requests and expect it to not fall over!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 78 ++
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
index f348f5f81351..63e69d360764 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
@@ -22,6 +22,8 @@
*
*/
+#include
+
#include "i915_selftest.h"
#include "mock_gem_device.h"
@@ -155,3 +157,79 @@ int i915_gem_request_mock_selftests(void)
return err;
}
+
+static int live_nop_request(void *arg)
+{
+ I915_SELFTEST_TIMEOUT(end_time);
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_request *request;
+ unsigned int reset_count = i915_reset_count(&i915->gpu_error);
+ unsigned long n, prime;
+ ktime_t times[2] = {};
+ int err;
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED);
+ if (err) {
+ pr_err("Failed to idle GPU before %s\n", __func__);
+ goto out_unlock;
+ }
+
+ i915->gpu_error.missed_irq_rings = 0;
+
+ for_each_prime_number_from(prime, 1, 8192) {
+ times[1] = ktime_get_raw();
+
+ for (n = 0; n < prime; n++) {
+ request = i915_gem_request_alloc(i915->engine[RCS],
+i915->kernel_context);
+ if (IS_ERR(request)) {
+ err = PTR_ERR(request);
+ goto out_unlock;
+ }
+
+ i915_add_request(request);
+ }
+ i915_wait_request(request, I915_WAIT_LOCKED,
MAX_SCHEDULE_TIMEOUT);
+ times[1] = ktime_sub(ktime_get_raw(), times[1]);
+ if (prime == 1)
+ times[0] = times[1];
+
+ if (time_after(jiffies, end_time)) {
+ pr_warn("%s timed out: last batch size %lu\n",
+ __func__, prime);
+ break;
+ }
+ }
+
+ if (reset_count != i915_reset_count(&i915->gpu_error)) {
+ pr_err("GPU was reset %d times!\n",
+ i915_reset_count(&i915->gpu_error) - reset_count);
+ err = -EIO;
+ goto out_unlock;
+ }
+
+ if (i915->gpu_error.missed_irq_rings) {
+ pr_err("Missed interrupts on rings %lx\n",
+ i915->gpu_error.missed_irq_rings);
+ err = -EIO;
+ goto out_unlock;
+ }
+
+ pr_info("Request latencies: 1 = %lluns, %lu = %lluns\n",
+ ktime_to_ns(times[0]),
+ prime, div64_u64(ktime_to_ns(times[1]), prime));
+
+out_unlock:
+ mutex_unlock(&i915->drm.struct_mutex);
+ return err;
+}
+
+int i915_gem_request_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_nop_request),
+ };
+ return i915_subtests(tests, i915);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index f3e17cb10e05..09bf538826df 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -9,3 +9,4 @@
* Tests are executed in order by igt/drv_selftest
*/
selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
+selftest(requests, i915_gem_request_live_selftests)
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/37] drm/i915: Add selftests for i915_gem_request
Simple starting point for adding seltests for i915_gem_request, first
mock a device (with engines and contexts) that allows us to construct
and execute a request, along with waiting for the request to complete.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_request.c| 5 ++
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 66 ++
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
3 files changed, 72 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_request.c
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c
b/drivers/gpu/drm/i915/i915_gem_request.c
index 72b7f7d9461d..bd2aeb290cad 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1193,3 +1193,8 @@ void i915_gem_retire_requests(struct drm_i915_private
*dev_priv)
for_each_engine(engine, dev_priv, id)
engine_retire_requests(engine);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/mock_request.c"
+#include "selftests/i915_gem_request.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
new file mode 100644
index ..233c0bdb9e82
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+
+#include "mock_gem_device.h"
+
+static int igt_add_request(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_request *request;
+ int err = -ENOMEM;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ request = mock_request(i915->engine[RCS],
+ i915->kernel_context,
+ HZ / 10);
+ if (!request)
+ goto out_unlock;
+
+ i915_add_request(request);
+
+ err = 0;
+out_unlock:
+ mutex_unlock(&i915->drm.struct_mutex);
+ return err;
+}
+
+int i915_gem_request_mock_selftests(void)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_add_request),
+ };
+ struct drm_i915_private *i915;
+ int err;
+
+ i915 = mock_gem_device();
+ if (!i915)
+ return -ENOMEM;
+
+ err = i915_subtests(tests, i915);
+ drm_dev_unref(&i915->drm);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 80458e2a2b04..bda982404ad3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -11,3 +11,4 @@
selftest(sanitycheck, i915_mock_sanitycheck) /* keep first (igt selfcheck) */
selftest(scatterlist, scatterlist_mock_selftests)
selftest(breadcrumbs, intel_breadcrumbs_mock_selftests)
+selftest(requests, i915_gem_request_mock_selftests)
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/37] drm/i915: Mock the GEM device for self-testing
A simulacrum of drm_i915_private to let us pretend interactions with the
device.
v2: Tidy init error paths
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_drv.c | 4 +
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/selftests/fake_drm.c| 54
drivers/gpu/drm/i915/selftests/fake_drm.h| 31 +++
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 106 +++
drivers/gpu/drm/i915/selftests/mock_gem_device.h | 8 ++
drivers/gpu/drm/i915/selftests/mock_gem_object.h | 8 ++
7 files changed, 212 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/fake_drm.c
create mode 100644 drivers/gpu/drm/i915/selftests/fake_drm.h
create mode 100644 drivers/gpu/drm/i915/selftests/mock_gem_device.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_gem_device.h
create mode 100644 drivers/gpu/drm/i915/selftests/mock_gem_object.h
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index aefab9a1a68e..41bf81bdae4e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2604,3 +2604,7 @@ static struct drm_driver driver = {
.minor = DRIVER_MINOR,
.patchlevel = DRIVER_PATCHLEVEL,
};
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/fake_drm.c"
+#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e88541b5b72b..ddc85a7c8d82 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4896,4 +4896,5 @@ i915_gem_object_get_dma_address(struct
drm_i915_gem_object *obj,
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/scatterlist.c"
+#include "selftests/mock_gem_device.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/fake_drm.c
b/drivers/gpu/drm/i915/selftests/fake_drm.c
new file mode 100644
index ..76af50d2cbaf
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/fake_drm.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "fake_drm.h"
+
+static inline struct inode fake_inode(struct drm_i915_private *i915)
+{
+ return (struct inode){ .i_rdev = i915->drm.primary->index };
+}
+
+struct drm_file *fake_file(struct drm_i915_private *i915)
+{
+ struct inode inode = fake_inode(i915);
+ struct file filp = {};
+ struct drm_file *file;
+ int err;
+
+ err = drm_open(&inode, &filp);
+ if (unlikely(err))
+ return ERR_PTR(err);
+
+ file = filp.private_data;
+ file->authenticated = true;
+ return file;
+}
+
+void fake_file_free(struct drm_i915_private *i915, struct drm_file *file)
+{
+ struct inode inode = fake_inode(i915);
+ struct file filp = { .private_data = file };
+
+ drm_release(&inode, &filp);
+}
diff --git a/drivers/gpu/drm/i915/selftests/fake_drm.h
b/drivers/gpu/drm/i915/selftests/fake_drm.h
new file mode 100644
index ..5e1975084959
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/fake_drm.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS O
[Intel-gfx] [PATCH 17/37] drm/i915: Test partial mappings
Create partial mappings to cover a large object, investigating tiling
(fenced regions) and VMA reuse.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_object.c | 252 +++
1 file changed, 252 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index 08e6b49b1e77..df3625f551aa 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -132,6 +132,257 @@ static int igt_gem_huge(void *arg)
return err;
}
+struct tile {
+ unsigned int width;
+ unsigned int height;
+ unsigned int stride;
+ unsigned int size;
+ unsigned int tiling;
+ unsigned int swizzle;
+};
+
+static u64 swizzle_bit(unsigned bit, u64 offset)
+{
+ return (offset & BIT_ULL(bit)) >> (bit - 6);
+}
+
+static u64 tiled_offset(const struct tile *tile, u64 v)
+{
+ u64 x, y;
+
+ if (tile->tiling == I915_TILING_NONE)
+ return v;
+
+ switch (tile->swizzle) {
+ case I915_BIT_6_SWIZZLE_9:
+ v ^= swizzle_bit(9, v);
+ break;
+ case I915_BIT_6_SWIZZLE_9_10:
+ v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v);
+ break;
+ case I915_BIT_6_SWIZZLE_9_11:
+ v ^= swizzle_bit(9, v) ^ swizzle_bit(11, v);
+ break;
+ case I915_BIT_6_SWIZZLE_9_10_11:
+ v ^= swizzle_bit(9, v) ^ swizzle_bit(10, v) ^ swizzle_bit(11,
v);
+ break;
+ }
+
+ y = div64_u64_rem(v, tile->stride, &x);
+ v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
+
+ if (tile->tiling == I915_TILING_X) {
+ v += y * tile->width;
+ v += div64_u64_rem(x, tile->width, &x) << tile->size;
+ v += x;
+ } else {
+ const unsigned int ytile_span = 16;
+ const unsigned int ytile_height = 32 * ytile_span;
+
+ v += y * ytile_span;
+ v += div64_u64_rem(x, ytile_span, &x) * ytile_height;
+ v += x;
+ }
+
+ return v;
+}
+
+static int check_partial_mapping(struct drm_i915_gem_object *obj,
+const struct tile *tile)
+{
+ const unsigned int nreal = obj->scratch / PAGE_SIZE;
+ const unsigned long npages = obj->base.size / PAGE_SIZE;
+ struct i915_vma *vma;
+ unsigned long page;
+ int err;
+
+ cond_resched();
+ if (signal_pending(current))
+ return -EINTR;
+
+ err = i915_gem_object_set_tiling(obj, tile->tiling, tile->stride);
+ if (err)
+ return err;
+
+ GEM_BUG_ON(i915_gem_object_get_tiling(obj) != tile->tiling);
+ GEM_BUG_ON(i915_gem_object_get_stride(obj) != tile->stride);
+
+ for_each_prime_number_from(page, 1, npages) {
+ struct i915_ggtt_view view =
+ compute_partial_view(obj, page, MIN_CHUNK_PAGES);
+ u32 __iomem *io;
+ struct page *p;
+ unsigned int n;
+ u64 offset;
+ u32 *cpu;
+
+ GEM_BUG_ON(intel_partial_get_page_count(&view.partial) > nreal);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, true);
+ if (err)
+ return err;
+
+ vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma)) {
+ pr_err("Failed to pin partial view: offset=%lu\n",
+ page);
+ return PTR_ERR(vma);
+ }
+
+ n = page - intel_partial_get_page_offset(&view.partial);
+ GEM_BUG_ON(n >= intel_partial_get_page_count(&view.partial));
+
+ io = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(io)) {
+ pr_err("Failed to iomap partial view: offset=%lu\n",
+ page);
+ return PTR_ERR(io);
+ }
+
+ err = i915_vma_get_fence(vma);
+ if (err) {
+ pr_err("Failed to get fence for partial view:
offset=%lu\n",
+ page);
+ i915_vma_unpin_iomap(vma);
+ return PTR_ERR(io);
+ }
+
+ iowrite32(page, io + n * PAGE_SIZE/sizeof(*io));
+ i915_vma_unpin_iomap(vma);
+
+ offset = tiled_offset(tile, page << PAGE_SHIFT);
+ if (offset >= obj->base.size)
+ continue;
+
+ i915_gem_object_flush_gtt_write_domain(obj);
+
+ p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
+ cpu = kmap(p) + offset_in_page(offset);
+ drm_clflush_virt_range(cpu, sizeof(*cpu));
+
[Intel-gfx] [PATCH 16/37] drm/i915: Add a live seftest for GEM objects
Starting with a placeholder test just to reassure that we can create a
test object,
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_object.c | 47 ++
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index f243d4e73d7b..08e6b49b1e77 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -94,6 +94,44 @@ static int igt_phys_object(void *arg)
return err;
}
+static int igt_gem_huge(void *arg)
+{
+ const unsigned int nreal = 509; /* just to be awkward */
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ unsigned int n;
+ int err;
+
+ obj = huge_gem_object(i915,
+ nreal * PAGE_SIZE,
+ i915->ggtt.base.total + PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ err = i915_gem_object_pin_pages(obj);
+ if (err) {
+ pr_err("Failed to allocate %u pages (%zu total), err=%d\n",
+ nreal, obj->base.size / PAGE_SIZE, err);
+ goto err;
+ }
+
+ for (n = 0; n < obj->base.size / PAGE_SIZE; n++) {
+ if (i915_gem_object_get_page(obj, n) !=
+ i915_gem_object_get_page(obj, n % nreal)) {
+ pr_err("Page lookup mismatch at index %u [%u]\n",
+ n, n % nreal);
+ err = -EINVAL;
+ goto err_unpin;
+ }
+ }
+
+err_unpin:
+ i915_gem_object_unpin_pages(obj);
+err:
+ i915_gem_object_put(obj);
+ return err;
+}
+
int i915_gem_object_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
@@ -112,3 +150,12 @@ int i915_gem_object_mock_selftests(void)
drm_dev_unref(&i915->drm);
return err;
}
+
+int i915_gem_object_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_gem_huge),
+ };
+
+ return i915_subtests(tests, i915);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 09bf538826df..1822ac99d577 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -10,3 +10,4 @@
*/
selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
selftest(requests, i915_gem_request_live_selftests)
+selftest(object, i915_gem_object_live_selftests)
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/37] drm/i915: Mock a GGTT for self-testing
A very simple mockery, just a random manager and timeline. Useful for
inserting objects and ordering retirement; and not much else.
v2: mock_fini_ggtt() to complement mock_init_ggtt().
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +
drivers/gpu/drm/i915/selftests/mock_gem_device.c | 31 +
drivers/gpu/drm/i915/selftests/mock_gtt.c| 138 +++
drivers/gpu/drm/i915/selftests/mock_gtt.h| 35 ++
4 files changed, 208 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/mock_gtt.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_gtt.h
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index e505de295848..f0057b812337 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3764,3 +3764,7 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
size, alignment, color,
start, end, DRM_MM_INSERT_EVICT);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/mock_gtt.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 0d5484467a4b..8f5fbc18a607 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -26,13 +26,20 @@
#include "mock_gem_device.h"
#include "mock_gem_object.h"
+#include "mock_gtt.h"
static void mock_device_release(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
+ mutex_lock(&i915->drm.struct_mutex);
+ mock_fini_ggtt(i915);
+ i915_gem_timeline_fini(&i915->gt.global_timeline);
+ mutex_unlock(&i915->drm.struct_mutex);
+
i915_gem_drain_freed_objects(i915);
+ kmem_cache_destroy(i915->vmas);
kmem_cache_destroy(i915->objects);
put_device(&i915->drm.pdev->dev);
}
@@ -84,19 +91,43 @@ struct drm_i915_private *mock_gem_device(void)
i915->drm.pdev = pdev;
i915->drm.dev_private = i915;
+ /* Using the global GTT may ask questions about KMS users, so prepare */
+ drm_mode_config_init(&i915->drm);
+
mkwrite_device_info(i915)->gen = -1;
spin_lock_init(&i915->mm.object_stat_lock);
INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
init_llist_head(&i915->mm.free_list);
+ INIT_LIST_HEAD(&i915->mm.unbound_list);
+ INIT_LIST_HEAD(&i915->mm.bound_list);
i915->objects = KMEM_CACHE(mock_object, SLAB_HWCACHE_ALIGN);
if (!i915->objects)
goto put_device;
+ i915->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN);
+ if (!i915->vmas)
+ goto err_objects;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ INIT_LIST_HEAD(&i915->gt.timelines);
+ err = i915_gem_timeline_init__global(i915);
+ if (err) {
+ mutex_unlock(&i915->drm.struct_mutex);
+ goto err_vmas;
+ }
+
+ mock_init_ggtt(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
+
return i915;
+err_vmas:
+ kmem_cache_destroy(i915->vmas);
+err_objects:
+ kmem_cache_destroy(i915->objects);
put_device:
put_device(&pdev->dev);
free_device:
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c
b/drivers/gpu/drm/i915/selftests/mock_gtt.c
new file mode 100644
index ..e176a04f482b
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "mock_gtt.h"
+
+static void mock_insert_page(struct i915_address_space *vm,
+dma_addr_t addr,
+uint64_t offset,
+
[Intel-gfx] [PATCH 12/37] drm/i915: Add a simple request selftest for waiting
A trivial kselftest to submit a request and wait upon it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 44 +++
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
index 233c0bdb9e82..ef72b32f9bc3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
@@ -47,10 +47,54 @@ static int igt_add_request(void *arg)
return err;
}
+static int igt_wait_request(void *arg)
+{
+ const long T = HZ / 4;
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_request *request;
+ int err = -EINVAL;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ request = mock_request(i915->engine[RCS], i915->kernel_context, T);
+ if (!request) {
+ err = -ENOMEM;
+ goto out_unlock;
+ }
+
+ i915_add_request(request);
+
+ if (i915_gem_request_completed(request)) {
+ pr_err("request completed immediately!\n");
+ goto out_unlock;
+ }
+
+ if (i915_wait_request(request, I915_WAIT_LOCKED, T / 2) != -ETIME) {
+ pr_err("request wait succeeded (expected tiemout!)\n");
+ goto out_unlock;
+ }
+
+ if (i915_wait_request(request, I915_WAIT_LOCKED, T) == -ETIME) {
+ pr_err("request wait timed out!\n");
+ goto out_unlock;
+ }
+
+ if (!i915_gem_request_completed(request)) {
+ pr_err("request not complete after waiting!\n");
+ goto out_unlock;
+ }
+
+ err = 0;
+out_unlock:
+ mock_device_flush(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
+ return err;
+}
+
int i915_gem_request_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_add_request),
+ SUBTEST(igt_wait_request),
};
struct drm_i915_private *i915;
int err;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/37] drm/i915: Add unit tests for the breadcrumb rbtree, wakeups
Third retroactive test, make sure that the seqno waiters are woken.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 171 +
1 file changed, 171 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
index e9dff6eee323..bee86470a91d 100644
--- a/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c
@@ -263,11 +263,182 @@ static int igt_insert_complete(void *arg)
return err;
}
+struct igt_wakeup {
+ struct task_struct *tsk;
+ atomic_t *ready, *set, *done;
+ struct intel_engine_cs *engine;
+ unsigned long flags;
+ wait_queue_head_t *wq;
+ u32 seqno;
+};
+
+static int wait_atomic(atomic_t *p)
+{
+ schedule();
+ return 0;
+}
+
+static int wait_atomic_timeout(atomic_t *p)
+{
+ return schedule_timeout(10 * HZ) ? 0 : -ETIMEDOUT;
+}
+
+static int igt_wakeup_thread(void *arg)
+{
+ struct igt_wakeup *w = arg;
+ struct intel_wait wait;
+
+ while (!kthread_should_stop()) {
+ DEFINE_WAIT(ready);
+
+ for (;;) {
+ prepare_to_wait(w->wq, &ready, TASK_INTERRUPTIBLE);
+ if (atomic_read(w->ready) == 0)
+ break;
+
+ schedule();
+ }
+ finish_wait(w->wq, &ready);
+ if (atomic_dec_and_test(w->set))
+ wake_up_atomic_t(w->set);
+
+ if (test_bit(0, &w->flags))
+ break;
+
+ intel_wait_init(&wait, w->seqno);
+ intel_engine_add_wait(w->engine, &wait);
+ for (;;) {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ if (i915_seqno_passed(intel_engine_get_seqno(w->engine),
+ w->seqno))
+ break;
+
+ schedule();
+ }
+ intel_engine_remove_wait(w->engine, &wait);
+ __set_current_state(TASK_RUNNING);
+
+ if (atomic_dec_and_test(w->done))
+ wake_up_atomic_t(w->done);
+ }
+
+ if (atomic_dec_and_test(w->done))
+ wake_up_atomic_t(w->done);
+ return 0;
+}
+
+static void igt_wake_all_sync(atomic_t *ready,
+ atomic_t *set,
+ atomic_t *done,
+ wait_queue_head_t *wq,
+ int count)
+{
+ atomic_set(set, count);
+ atomic_set(done, count);
+
+ atomic_set(ready, 0);
+ wake_up_all(wq);
+
+ wait_on_atomic_t(set, wait_atomic, TASK_UNINTERRUPTIBLE);
+ atomic_set(ready, count);
+}
+
+static int igt_wakeup(void *arg)
+{
+ const int state = TASK_UNINTERRUPTIBLE;
+ struct intel_engine_cs *engine = arg;
+ struct igt_wakeup *waiters;
+ DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wq);
+ const int count = 4096;
+ const u32 max_seqno = count / 4;
+ atomic_t ready, set, done;
+ int err = -ENOMEM;
+ int n, step;
+
+ mock_engine_reset(engine);
+
+ waiters = drm_malloc_gfp(count, sizeof(*waiters), GFP_TEMPORARY);
+ if (!waiters)
+ goto out_engines;
+
+ /* Create a large number of threads, each waiting on a random seqno.
+* Multiple waiters will be waiting for the same seqno.
+*/
+ atomic_set(&ready, count);
+ for (n = 0; n < count; n++) {
+ waiters[n].wq = &wq;
+ waiters[n].ready = &ready;
+ waiters[n].set = &set;
+ waiters[n].done = &done;
+ waiters[n].engine = engine;
+ waiters[n].flags = 0;
+
+ waiters[n].tsk = kthread_run(igt_wakeup_thread, &waiters[n],
+"i915/igt:%d", n);
+ if (IS_ERR(waiters[n].tsk))
+ goto out_waiters;
+
+ get_task_struct(waiters[n].tsk);
+ }
+
+ for (step = 1; step <= max_seqno; step <<= 1) {
+ u32 seqno;
+
+ for (n = 0; n < count; n++)
+ waiters[n].seqno = 1 + get_random_int() % max_seqno;
+
+ mock_seqno_advance(engine, 0);
+ igt_wake_all_sync(&ready, &set, &done, &wq, count);
+
+ for (seqno = 1; seqno <= max_seqno + step; seqno += step) {
+ usleep_range(50, 500);
+ mock_seqno_advance(engine, seqno);
+ }
+ GEM_BUG_ON(intel_engine_get_seqno(engine) < 1 + max_seqno);
+
+ err = wait_on_atomic_t(&done, wait_atomic_timeout, state);
+ if (err) {
+ pr_err("Timed out waiting for %d remaining waiters\n",
+
[Intel-gfx] [PATCH 26/37] drm/i915: Assert that we have allocated the drm_mm_node upon pinning
We currently check after the slow path that the vma is bound correctly,
but we don't currently check after the fast path. This is important in
case we accidentally take the fast path and leave the vma misplaced.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_vma.c | 1 +
drivers/gpu/drm/i915/i915_vma.h | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 2307e1610743..6424352a69b2 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -474,6 +474,7 @@ int __i915_vma_do_pin(struct i915_vma *vma,
if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND)
__i915_vma_set_map_and_fenceable(vma);
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags));
return 0;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 9d6913b10f30..47b5ceb386c4 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -237,8 +237,11 @@ i915_vma_pin(struct i915_vma *vma, u64 size, u64
alignment, u64 flags)
/* Pin early to prevent the shrinker/eviction logic from destroying
* our vma as we insert and bind.
*/
- if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0))
+ if (likely(((++vma->flags ^ flags) & I915_VMA_BIND_MASK) == 0)) {
+ GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
+ GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags));
return 0;
+ }
return __i915_vma_do_pin(vma, size, alignment, flags);
}
--
2.11.0
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 24/37] drm/i915: Add initial selftests for i915_gem_gtt
Simple starting point for adding selftests for i915_gem_gtt, first
try creating a ppGTT and filling it.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c| 1 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 95 ++
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 97 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f0057b812337..5f30d81e842e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3767,4 +3767,5 @@ int i915_gem_gtt_insert(struct i915_address_space *vm,
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_gtt.c"
+#include "selftests/i915_gem_gtt.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
new file mode 100644
index ..97b55e9726d8
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+
+static int igt_ppgtt_alloc(void *arg)
+{
+ struct drm_i915_private *dev_priv = arg;
+ struct i915_hw_ppgtt *ppgtt;
+ u64 size, last;
+ int err;
+
+ if (!USES_PPGTT(dev_priv))
+ return 0;
+
+ ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
+ if (!ppgtt)
+ return -ENOMEM;
+
+ err = __hw_ppgtt_init(ppgtt, dev_priv);
+ if (err)
+ goto err_ppgtt;
+
+ if (!ppgtt->base.allocate_va_range)
+ goto err_ppgtt_cleanup;
+
+ /* Check we can allocate the entire range */
+ for (size = 4096;
+size <= ppgtt->base.total;
+size <<= 2) {
+ err = ppgtt->base.allocate_va_range(&ppgtt->base, 0, size);
+ if (err) {
+ if (err == -ENOMEM) {
+ pr_info("[1] Ran out of memory for va_range [0
+ %llx] [bit %d]\n",
+ size, ilog2(size));
+ err = 0; /* virtual space too large! */
+ }
+ goto err_ppgtt_cleanup;
+ }
+
+ ppgtt->base.clear_range(&ppgtt->base, 0, size);
+ }
+
+ /* Check we can incrementally allocate the entire range */
+ for (last = 0, size = 4096;
+size <= ppgtt->base.total;
+last = size, size <<= 2) {
+ err = ppgtt->base.allocate_va_range(&ppgtt->base,
+ last, size - last);
+ if (err) {
+ if (err == -ENOMEM) {
+ pr_info("[2] Ran out of memory for va_range
[%llx + %llx] [bit %d]\n",
+ last, size - last, ilog2(size));
+ err = 0; /* virtual space too large! */
+ }
+ goto err_ppgtt_cleanup;
+ }
+ }
+
+err_ppgtt_cleanup:
+ ppgtt->base.cleanup(&ppgtt->base);
+err_ppgtt:
+ kfree(ppgtt);
+ return err;
+}
+
+int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_ppgtt_alloc),
+ };
+
+ return i915_subtests(tests, i915);
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index c060bf24928e..94517ad6dbd1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -13,3 +13,4 @@ selftest(uncore, intel_uncore_live_selftests)
selfte
[Intel-gfx] [PATCH 15/37] drm/i915: Add selftests for object allocation, phys
The phys object is a rarely used device (only very old machines require
a chunk of physically contiguous pages for a few hardware interactions).
As such, it is not exercised by CI and to combat that we want to add a
test that exercises the phys object on all platforms.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c| 1 +
drivers/gpu/drm/i915/selftests/i915_gem_object.c | 114 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
3 files changed, 116 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_object.c
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 07b4ba3df94c..4a52c5872898 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4898,4 +4898,5 @@ i915_gem_object_get_dma_address(struct
drm_i915_gem_object *obj,
#include "selftests/scatterlist.c"
#include "selftests/mock_gem_device.c"
#include "selftests/huge_gem_object.c"
+#include "selftests/i915_gem_object.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
new file mode 100644
index ..f243d4e73d7b
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+
+#include "mock_gem_device.h"
+
+static int igt_gem_object(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ int err = -ENOMEM;
+
+ obj = i915_gem_object_create(i915, PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ pr_err("i915_gem_object_create failed, err=%d\n", err);
+ goto out;
+ }
+
+ err = 0;
+ i915_gem_object_put(obj);
+out:
+ return err;
+}
+
+static int igt_phys_object(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ int err = -ENOMEM;
+
+ obj = i915_gem_object_create(i915, PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ pr_err("i915_gem_object_create failed, err=%d\n", err);
+ goto out;
+ }
+
+ err = -EINVAL;
+ mutex_lock(&i915->drm.struct_mutex);
+ err = i915_gem_object_attach_phys(obj, PAGE_SIZE);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (err) {
+ pr_err("i915_gem_object_attach_phys failed, err=%d\n", err);
+ goto err;
+ }
+
+ if (obj->ops != &i915_gem_phys_ops) {
+ pr_err("i915_gem_object_attach_phys did not create a phys
object\n");
+ goto err;
+ }
+
+ if (!atomic_read(&obj->mm.pages_pin_count)) {
+ pr_err("i915_gem_object_attach_phys did not pin its phys
pages\n");
+ goto err;
+ }
+
+ /* Make the object dirty so that put_pages must do copy back the data */
+ mutex_lock(&i915->drm.struct_mutex);
+ err = i915_gem_object_set_to_gtt_domain(obj, true);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (err) {
+ pr_err("i915_gem_object_set_to_gtt_domain failed with err=%d\n",
+ err);
+ goto err;
+ }
+
+ err = 0;
+err:
+ i915_gem_object_put(obj);
+out:
+ return err;
+}
+
+int i915_gem_object_mock_selftests(void)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(igt_gem_object),
+ SUBTEST(igt_phys_object),
+ };
+ struct drm_i915_private *i915;
+ int err;
+
+ i915 = mock_gem_device();
+ if (!i915)
+ return -ENOMEM;
+
+ err = i915_subtests(tests, i915);
+
+ drm_dev_unref(&i915->drm);
+
[Intel-gfx] [PATCH 25/37] drm/i915: Move i915_ppgtt_close() into i915_gem_gtt.c
Move it alongside its ppgtt counterparts, in order to make it available
for the ppgtt selftests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c | 21 -
drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
3 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 91551b01a62c..6fcb35ecd6a7 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -205,27 +205,6 @@ alloc_context_obj(struct drm_i915_private *dev_priv, u64
size)
return obj;
}
-static void i915_ppgtt_close(struct i915_address_space *vm)
-{
- struct list_head *phases[] = {
- &vm->active_list,
- &vm->inactive_list,
- &vm->unbound_list,
- NULL,
- }, **phase;
-
- GEM_BUG_ON(vm->closed);
- vm->closed = true;
-
- for (phase = phases; *phase; phase++) {
- struct i915_vma *vma, *vn;
-
- list_for_each_entry_safe(vma, vn, *phase, vm_link)
- if (!i915_vma_is_closed(vma))
- i915_vma_close(vma);
- }
-}
-
static void context_close(struct i915_gem_context *ctx)
{
i915_gem_context_set_closed(ctx);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5f30d81e842e..5bbaa24d8a91 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2260,6 +2260,27 @@ i915_ppgtt_create(struct drm_i915_private *dev_priv,
return ppgtt;
}
+void i915_ppgtt_close(struct i915_address_space *vm)
+{
+ struct list_head *phases[] = {
+ &vm->active_list,
+ &vm->inactive_list,
+ &vm->unbound_list,
+ NULL,
+ }, **phase;
+
+ GEM_BUG_ON(vm->closed);
+ vm->closed = true;
+
+ for (phase = phases; *phase; phase++) {
+ struct i915_vma *vma, *vn;
+
+ list_for_each_entry_safe(vma, vn, *phase, vm_link)
+ if (!i915_vma_is_closed(vma))
+ i915_vma_close(vma);
+ }
+}
+
void i915_ppgtt_release(struct kref *kref)
{
struct i915_hw_ppgtt *ppgtt =
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 7ce4e2aaa159..28a3eca17b39 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -535,6 +535,7 @@ void i915_ppgtt_release(struct kref *kref);
struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
struct drm_i915_file_private *fpriv,
const char *name);
+void i915_ppgtt_close(struct i915_address_space *vm);
static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
{
if (ppgtt)
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/37] drm/i915: Add a simple fence selftest to i915_gem_request
Do a quick selftest on in the interoperability of dma_fence_wait on a
i915_gem_request.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/i915_gem_request.c | 47 +++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
index ef72b32f9bc3..f348f5f81351 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_request.c
@@ -90,11 +90,58 @@ static int igt_wait_request(void *arg)
return err;
}
+static int igt_fence_wait(void *arg)
+{
+ const long T = HZ / 4;
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_request *request;
+ int err = -EINVAL;
+
+ mutex_lock(&i915->drm.struct_mutex);
+ request = mock_request(i915->engine[RCS], i915->kernel_context, T);
+ if (!request) {
+ err = -ENOMEM;
+ goto out_locked;
+ }
+
+ i915_add_request(request);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ if (dma_fence_is_signaled(&request->fence)) {
+ pr_err("fence signaled immediately!\n");
+ goto out_device;
+ }
+
+ if (dma_fence_wait_timeout(&request->fence, false, T / 2) != -ETIME) {
+ pr_err("fence wait success after submit (expected timeout)!\n");
+ goto out_device;
+ }
+
+ if (dma_fence_wait_timeout(&request->fence, false, T) <= 0) {
+ pr_err("fence wait timed out (expected success)!\n");
+ goto out_device;
+ }
+
+ if (!dma_fence_is_signaled(&request->fence)) {
+ pr_err("fence unsignaled after waiting!\n");
+ goto out_device;
+ }
+
+ err = 0;
+out_device:
+ mutex_lock(&i915->drm.struct_mutex);
+out_locked:
+ mock_device_flush(i915);
+ mutex_unlock(&i915->drm.struct_mutex);
+ return err;
+}
+
int i915_gem_request_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_add_request),
SUBTEST(igt_wait_request),
+ SUBTEST(igt_fence_wait),
};
struct drm_i915_private *i915;
int err;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 20/37] drm/i915: Move uncore selfchecks to live selftest infrastructure
Now that the kselftest infrastructure exists, put it to use and add to
it the existing consistency checks on the fw register lookup tables.
v2: s/tabke/table/
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/intel_uncore.c| 52 +---
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 99 ++
3 files changed, 104 insertions(+), 48 deletions(-)
create mode 100644 drivers/gpu/drm/i915/selftests/intel_uncore.c
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index abe08885a5ba..b6ce8de2cc86 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -635,33 +635,6 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32
offset)
return entry->domains;
}
-static void
-intel_fw_table_check(struct drm_i915_private *dev_priv)
-{
- const struct intel_forcewake_range *ranges;
- unsigned int num_ranges;
- s32 prev;
- unsigned int i;
-
- if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
- return;
-
- ranges = dev_priv->uncore.fw_domains_table;
- if (!ranges)
- return;
-
- num_ranges = dev_priv->uncore.fw_domains_table_entries;
-
- for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
- WARN_ON_ONCE(IS_GEN9(dev_priv) &&
-(prev + 1) != (s32)ranges->start);
- WARN_ON_ONCE(prev >= (s32)ranges->start);
- prev = ranges->start;
- WARN_ON_ONCE(prev >= (s32)ranges->end);
- prev = ranges->end;
- }
-}
-
#define GEN_FW_RANGE(s, e, d) \
{ .start = (s), .end = (e), .domains = (d) }
@@ -700,23 +673,6 @@ static const i915_reg_t gen8_shadowed_regs[] = {
/* TODO: Other registers are not yet used */
};
-static void intel_shadow_table_check(void)
-{
- const i915_reg_t *reg = gen8_shadowed_regs;
- s32 prev;
- u32 offset;
- unsigned int i;
-
- if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG))
- return;
-
- for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
- offset = i915_mmio_reg_offset(*reg);
- WARN_ON_ONCE(prev >= (s32)offset);
- prev = offset;
- }
-}
-
static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
{
u32 offset = i915_mmio_reg_offset(*reg);
@@ -1445,10 +1401,6 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
break;
}
- intel_fw_table_check(dev_priv);
- if (INTEL_GEN(dev_priv) >= 8)
- intel_shadow_table_check();
-
if (intel_vgpu_active(dev_priv)) {
ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
ASSIGN_READ_MMIO_VFUNCS(vgpu);
@@ -1971,3 +1923,7 @@ intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv,
return fw_domains;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/intel_uncore.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index fde9ef22cfe8..c060bf24928e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -9,6 +9,7 @@
* Tests are executed in order by igt/drv_selftest
*/
selftest(sanitycheck, i915_live_sanitycheck) /* keep first (igt selfcheck) */
+selftest(uncore, intel_uncore_live_selftests)
selftest(requests, i915_gem_request_live_selftests)
selftest(object, i915_gem_object_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
b/drivers/gpu/drm/i915/selftests/intel_uncore.c
new file mode 100644
index ..0ac467940a4f
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, W
[Intel-gfx] [PATCH 35/37] drm/i915: Live testing for context execution
Check we can create and execution within a context.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c| 1 +
drivers/gpu/drm/i915/selftests/i915_gem_context.c | 302 +
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 304 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_context.c
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 6fcb35ecd6a7..9966dfd56a1b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1167,4 +1167,5 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev,
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_context.c"
+#include "selftests/i915_gem_context.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
new file mode 100644
index ..53951dce67e9
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+#include "fake_drm.h"
+#include "huge_gem_object.h"
+
+static struct i915_vma *vma_lookup(struct drm_i915_gem_object *obj,
+ struct i915_address_space *vm)
+{
+ return i915_gem_obj_lookup_or_create_vma(obj, vm, NULL);
+}
+
+static struct i915_vma *
+gpu_fill_pages(struct i915_vma *vma,
+ unsigned long first_page,
+ unsigned int offset_in_page,
+ unsigned long count,
+ u32 value)
+{
+ struct drm_i915_gem_object *obj;
+ const int gen = INTEL_GEN(vma->vm->i915);
+ unsigned long sz = (4*count + 1)*sizeof(u32);
+ u64 offset;
+ u32 *cmd;
+ int err;
+
+ GEM_BUG_ON(offset_in_page >= PAGE_SIZE);
+
+ obj = i915_gem_object_create_internal(vma->vm->i915,
+ round_up(sz, PAGE_SIZE));
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ cmd = i915_gem_object_pin_map(obj, I915_MAP_WB);
+ if (IS_ERR(cmd)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(cmd);
+ }
+
+ offset = PAGE_SIZE * first_page + offset_in_page;
+ offset += vma->node.start;
+ for (sz = 0; sz < count; sz++) {
+ if (gen >= 8) {
+ *cmd++ = MI_STORE_DWORD_IMM_GEN4;
+ *cmd++ = lower_32_bits(offset);
+ *cmd++ = upper_32_bits(offset);
+ *cmd++ = value;
+ } else if (gen >= 6) {
+ *cmd++ = MI_STORE_DWORD_IMM_GEN4;
+ *cmd++ = 0;
+ *cmd++ = offset;
+ *cmd++ = value;
+ } else if (gen >= 4) {
+ *cmd++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
+ *cmd++ = 0;
+ *cmd++ = offset;
+ *cmd++ = value;
+ } else {
+ *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
+ *cmd++ = offset;
+ *cmd++ = value;
+ }
+ offset += PAGE_SIZE;
+ }
+ *cmd = MI_BATCH_BUFFER_END;
+ i915_gem_object_unpin_map(obj);
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ vma = vma_lookup(obj, vma->vm);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(er
[Intel-gfx] [PATCH 33/37] drm/i915: Verify page layout for rotated VMA
Exercise creating rotated VMA and checking the page order within.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 130 ++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index d229adabc5f8..95c5db2b0881 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -287,11 +287,141 @@ static int igt_vma_pin1(void *arg)
return err;
}
+static unsigned long rotated_index(const struct intel_rotation_info *r,
+ unsigned int n,
+ unsigned int x,
+ unsigned int y)
+{
+ return r->plane[n].stride * (r->plane[n].height - y - 1) + x;
+}
+
+static struct scatterlist *
+assert_rotated(struct drm_i915_gem_object *obj,
+ const struct intel_rotation_info *r, unsigned int n,
+ struct scatterlist *sg)
+{
+ unsigned int x, y;
+
+ for (x = 0; x < r->plane[n].width; x++) {
+ for (y = 0; y < r->plane[n].height; y++) {
+ unsigned long src_idx;
+ dma_addr_t src;
+
+ src_idx = rotated_index(r, n, x, y);
+ src = i915_gem_object_get_dma_address(obj, src_idx);
+
+ if (sg_dma_len(sg) != PAGE_SIZE) {
+ pr_err("Invalid sg.length, found %d, expected
%lu for rotated page (%d, %d) [src index %lu]\n",
+ sg_dma_len(sg), PAGE_SIZE,
+ x, y, src_idx);
+ return NULL;
+ }
+
+ if (sg_dma_address(sg) != src) {
+ pr_err("Invalid address for rotated page (%d,
%d) [src index %lu]\n",
+ x, y, src_idx);
+ return NULL;
+ }
+
+ sg = sg_next(sg);
+ }
+ }
+
+ return sg;
+}
+
+static int igt_vma_rotate(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ const unsigned int width = 6;
+ const unsigned int height = 4;
+ const unsigned int npages = 24;
+ struct i915_vma *vma;
+ struct i915_ggtt_view view;
+ struct scatterlist *sg;
+ unsigned int n;
+ int err = -ENOMEM;
+
+ obj = i915_gem_object_create_internal(i915, npages*PAGE_SIZE);
+ if (IS_ERR(obj))
+ goto err;
+
+ view.type = I915_GGTT_VIEW_ROTATED;
+ view.rotated.plane[0].offset = 0;
+ view.rotated.plane[0].width = width;
+ view.rotated.plane[0].height = height;
+ view.rotated.plane[0].stride = width;
+
+ view.rotated.plane[1].offset = 0;
+ view.rotated.plane[1].width = height;
+ view.rotated.plane[1].height = width;
+ view.rotated.plane[1].stride = height;
+
+ vma = i915_gem_obj_lookup_or_create_vma(obj, &i915->ggtt.base, &view);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_object;
+ }
+
+ if (!i915_vma_is_ggtt(vma)) {
+ pr_err("VMA is not in the GGTT!\n");
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto err_object;
+
+ if (memcmp(&vma->ggtt_view, &view, sizeof(view))) {
+ pr_err("VMA mismatch upon creation!\n");
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ if (vma->size != 2*npages*PAGE_SIZE) {
+ pr_err("VMA is wrong size, expected %lu, found %llu\n",
+ 2*npages*PAGE_SIZE, vma->size);
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ if (vma->node.size < vma->size) {
+ pr_err("VMA binding too small, expected %llu, found %llu\n",
+ vma->size, vma->node.size);
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ if (vma->pages == obj->mm.pages) {
+ pr_err("VMA using unrotated object pages!\n");
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ sg = vma->pages->sgl;
+ for (n = 0; n < ARRAY_SIZE(view.rotated.plane); n++) {
+ sg = assert_rotated(obj, &view.rotated, n, sg);
+ if (!sg) {
+ pr_err("Inconsistent VMA pages for plane %d\n", n);
+ err = -EINVAL;
+ goto err_object;
+ }
+ }
+
+err_object:
+ i915_gem_object_put(obj);
+err:
+ return err;
+}
+
int i915_vma_mock_selftests(void)
{
static const struct i915_subtest tests[] = {
SUBTEST(igt_vma_create),
[Intel-gfx] [PATCH 30/37] drm/i915: Exercise filling and removing random ranges from the live GTT
Test the low-level i915_address_space interfaces to sanity check the
live insertion/removal of address ranges.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 140 ++
1 file changed, 140 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 68f7bfb7502e..b20406631120 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -25,6 +25,7 @@
#include
#include "i915_selftest.h"
+#include "i915_random.h"
#include "fake_drm.h"
#include "huge_gem_object.h"
@@ -290,6 +291,74 @@ static int walk_hole(struct drm_i915_private *i915,
return err;
}
+static u64 scale(u64 offset, unsigned int shift)
+{
+ return offset << shift;
+}
+
+static int random_hole(struct drm_i915_private *i915,
+ struct i915_address_space *vm,
+ u64 hole_start, u64 hole_end)
+{
+ I915_RND_STATE(prng);
+ unsigned int size;
+
+ for (size = 12; (hole_end - hole_start) >> (size + 2); size++) {
+ I915_SELFTEST_TIMEOUT(end_time);
+ struct drm_i915_gem_object *obj;
+ unsigned int *order, count, n;
+ u64 hole_size;
+
+ hole_size = (hole_end - hole_start) >> size;
+ if (hole_size > KMALLOC_MAX_SIZE / sizeof(u32))
+ hole_size = KMALLOC_MAX_SIZE / sizeof(u32);
+ count = hole_size;
+ do {
+ count >>= 1;
+ order = i915_random_order(count, &prng);
+ } while (!order && count);
+
+ obj = huge_gem_object(i915, PAGE_SIZE, scale(1, size));
+ if (IS_ERR(obj))
+ break;
+
+ GEM_BUG_ON(obj->base.size != scale(1, size));
+
+ if (i915_gem_object_pin_pages(obj)) {
+ i915_gem_object_put(obj);
+ break;
+ }
+
+ for (n = 0; n < count; n++) {
+ if (vm->allocate_va_range &&
+ vm->allocate_va_range(vm,
+ scale(order[n], size),
+ scale(1, size)))
+ break;
+
+ vm->insert_entries(vm, obj->mm.pages,
+ scale(order[n], size),
+ I915_CACHE_NONE, 0);
+ if (time_after(jiffies, end_time))
+ break;
+ }
+ count = n;
+
+ i915_random_reorder(order, count, &prng);
+ for (n = 0; n < count; n++)
+ vm->clear_range(vm,
+ scale(order[n], size),
+ scale(1, size));
+
+ i915_gem_object_unpin_pages(obj);
+ i915_gem_object_put(obj);
+
+ kfree(order);
+ }
+
+ return 0;
+}
+
static int igt_ppgtt_fill(void *arg)
{
struct drm_i915_private *dev_priv = arg;
@@ -356,6 +425,39 @@ static int igt_ppgtt_walk(void *arg)
return err;
}
+static int igt_ppgtt_drunk(void *arg)
+{
+ struct drm_i915_private *dev_priv = arg;
+ struct drm_file *file;
+ struct i915_hw_ppgtt *ppgtt;
+ int err;
+
+ if (!USES_FULL_PPGTT(dev_priv))
+ return 0;
+
+ file = fake_file(dev_priv);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ ppgtt = i915_ppgtt_create(dev_priv, file->driver_priv, "mock");
+ if (IS_ERR(ppgtt)) {
+ err = PTR_ERR(ppgtt);
+ goto err_unlock;
+ }
+ GEM_BUG_ON(ppgtt->base.total & ~PAGE_MASK);
+
+ err = random_hole(dev_priv, &ppgtt->base, 0, ppgtt->base.total);
+
+ i915_ppgtt_close(&ppgtt->base);
+ i915_ppgtt_put(ppgtt);
+err_unlock:
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
+ fake_file_free(dev_priv, file);
+ return err;
+}
+
static int igt_ggtt_fill(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -428,12 +530,50 @@ static int igt_ggtt_walk(void *arg)
return err;
}
+static int igt_ggtt_drunk(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ u64 hole_start = U64_MAX, hole_end = 0, hole_size = 0;
+ u64 this_start, this_end;
+ struct drm_mm_node *node;
+ int err;
+
+ GEM_BUG_ON(ggtt->base.total & ~PAGE_MASK);
+
+ mutex_lock(&i915->drm.struct_mutex);
+ drm_mm_for_each_hole(node, &ggtt->base.mm, this_start, this_end) {
+ u64 this_size;
+
+ if (ggtt->base.mm.color_adjust)
+ ggtt->base. mm.color_
[Intel-gfx] [PATCH 23/37] drm/i915: Add some mock tests for dmabuf interop
Check that we can create both dmabuf and objects from dmabuf.
v2: Cleanups, correct include, fix unpin on dead path and prevent
explosion on dmabuf init failure
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_dmabuf.c | 5 +
drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c | 298 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/mock_dmabuf.c | 176
drivers/gpu/drm/i915/selftests/mock_dmabuf.h | 41 +++
5 files changed, 521 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_dmabuf.c
create mode 100644 drivers/gpu/drm/i915/selftests/mock_dmabuf.h
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index d037adcda6f2..3e276eee0450 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -307,3 +307,8 @@ struct drm_gem_object *i915_gem_prime_import(struct
drm_device *dev,
return ERR_PTR(ret);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/mock_dmabuf.c"
+#include "selftests/i915_gem_dmabuf.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
new file mode 100644
index ..75187a06bcb6
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_dmabuf.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+
+#include "mock_gem_device.h"
+#include "mock_dmabuf.h"
+
+static int igt_dmabuf_export(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct dma_buf *dmabuf;
+ int err;
+
+ obj = i915_gem_object_create(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ dmabuf = i915_gem_prime_export(&i915->drm, &obj->base, 0);
+ if (IS_ERR(dmabuf)) {
+ pr_err("i915_gem_prime_export failed with err=%d\n",
+ (int)PTR_ERR(dmabuf));
+ err = PTR_ERR(dmabuf);
+ goto err;
+ }
+
+ err = 0;
+ dma_buf_put(dmabuf);
+err:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static int igt_dmabuf_import_self(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct drm_gem_object *import;
+ struct dma_buf *dmabuf;
+ int err;
+
+ obj = i915_gem_object_create(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ dmabuf = i915_gem_prime_export(&i915->drm, &obj->base, 0);
+ if (IS_ERR(dmabuf)) {
+ pr_err("i915_gem_prime_export failed with err=%d\n",
+ (int)PTR_ERR(dmabuf));
+ err = PTR_ERR(dmabuf);
+ goto err;
+ }
+
+ import = i915_gem_prime_import(&i915->drm, dmabuf);
+ if (IS_ERR(import)) {
+ pr_err("i915_gem_prime_import failed with err=%d\n",
+ (int)PTR_ERR(import));
+ err = PTR_ERR(import);
+ goto err_dmabuf;
+ }
+
+ if (import != &obj->base) {
+ pr_err("i915_gem_prime_import created a new object!\n");
+ err = -EINVAL;
+ goto err_import;
+ }
+
+ err = 0;
+err_import:
+ i915_gem_object_put(to_intel_bo(import));
+err_dmabuf:
+ dma_buf_put(dmabuf);
+err:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static int igt_dmabuf_import(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_i915_gem_object *obj;
+ struct dma_buf *dmabuf;
+ void *obj_map, *dma_map;
+ u32 patt
[Intel-gfx] [PATCH 27/37] drm/i915: Exercising filling the top/bottom portions of the ppgtt
Allocate objects with varying number of pages (which should hopefully
consist of a mixture of contiguous page chunks and so coalesced sg
lists) and check that the sg walkers in insert_pages cope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_internal.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 159 ++
3 files changed, 163 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b84c1d1fa12c..65298edc0e9c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3506,7 +3506,7 @@ i915_gem_object_create_stolen_for_preallocated(struct
drm_i915_private *dev_priv
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
- unsigned int size);
+ unsigned long size);
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c
b/drivers/gpu/drm/i915/i915_gem_internal.c
index 863e505f..92f66e959a9f 100644
--- a/drivers/gpu/drm/i915/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/i915_gem_internal.c
@@ -151,10 +151,12 @@ static const struct drm_i915_gem_object_ops
i915_gem_object_internal_ops = {
*/
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *i915,
- unsigned int size)
+ unsigned long size)
{
struct drm_i915_gem_object *obj;
+ GEM_BUG_ON(!size);
+
obj = i915_gem_object_alloc(i915);
if (!obj)
return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 97b55e9726d8..5d0e6f60bea7 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -22,7 +22,10 @@
*
*/
+#include
+
#include "i915_selftest.h"
+#include "huge_gem_object.h"
static int igt_ppgtt_alloc(void *arg)
{
@@ -85,10 +88,166 @@ static int igt_ppgtt_alloc(void *arg)
return err;
}
+static struct i915_vma *vma_lookup(struct drm_i915_gem_object *obj,
+ struct i915_address_space *vm)
+{
+ return i915_gem_obj_lookup_or_create_vma(obj, vm, NULL);
+}
+
+static int igt_ppgtt_fill(void *arg)
+{
+ struct drm_i915_private *dev_priv = arg;
+ unsigned long npages, max_pages = 1 << 20, prime;
+ struct drm_i915_gem_object *obj, *on;
+ struct i915_hw_ppgtt *ppgtt;
+ struct i915_vma *vma;
+ LIST_HEAD(objects);
+ int err = 0;
+
+ if (!USES_FULL_PPGTT(dev_priv))
+ return 0;
+
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ ppgtt = i915_ppgtt_create(dev_priv, NULL, "mock");
+ if (IS_ERR(ppgtt)) {
+ err = PTR_ERR(ppgtt);
+ goto err_unlock;
+ }
+ GEM_BUG_ON(ppgtt->base.total & ~PAGE_MASK);
+
+ max_pages = min_t(u64, max_pages, ppgtt->base.total/2 >> PAGE_SHIFT);
+
+ for_each_prime_number_from(prime, 2, 13) {
+ for (npages = 1; npages <= max_pages; npages *= prime) {
+ u64 flags;
+
+ GEM_BUG_ON(!npages);
+ obj = huge_gem_object(dev_priv,
+ PAGE_SIZE,
+ npages << PAGE_SHIFT);
+ if (IS_ERR(obj))
+ break;
+
+ list_add(&obj->batch_pool_link, &objects);
+
+ /* Fill the GTT top down - hope we don't overstep the
end */
+ flags = ppgtt->base.total | PIN_OFFSET_FIXED | PIN_USER;
+ list_for_each_entry(obj, &objects, batch_pool_link) {
+ vma = vma_lookup(obj, &ppgtt->base);
+ if (IS_ERR(vma))
+ continue;
+
+ flags -= obj->base.size;
+ err = i915_vma_pin(vma, 0, 0, flags);
+ if (err) {
+ pr_err("Fill top-down failed with
err=%d on size=%lu pages (prime=%lu)\n", err, npages, prime);
+ goto err;
+ }
+
+ i915_vma_unpin(vma);
+ }
+
+ flags = ppgtt->base.total | PIN_OFFSET_FIXED | PIN_USER;
+ list_for_each_entry(obj, &objects, batch_pool_link) {
+ vma = vma_lookup(obj, &ppgtt->base);
+ if (IS_ERR(vma))
+ continue;
+
+
[Intel-gfx] [PATCH 34/37] drm/i915: Test creation of partial VMA
Mock testing to ensure we can create and lookup partial VMA.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_vma.c | 179 ++
1 file changed, 179 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index 95c5db2b0881..7511f383868c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -416,12 +416,191 @@ static int igt_vma_rotate(void *arg)
return err;
}
+static bool assert_partial(struct drm_i915_gem_object *obj,
+ struct i915_vma *vma,
+ unsigned long offset,
+ unsigned long size)
+{
+ struct sgt_iter sgt;
+ dma_addr_t dma;
+
+ for_each_sgt_dma(dma, sgt, vma->pages) {
+ dma_addr_t src;
+
+ if (!size) {
+ pr_err("Partial scattergather list too long\n");
+ return false;
+ }
+
+ src = i915_gem_object_get_dma_address(obj, offset);
+ if (src != dma) {
+ pr_err("DMA mismatch for partial page offset %lu\n",
+ offset);
+ return false;
+ }
+
+ offset++;
+ size--;
+ }
+
+ return true;
+}
+
+static int igt_vma_partial(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const unsigned int npages = 1021; /* prime! */
+ struct drm_i915_gem_object *obj;
+ unsigned int sz, offset, loop;
+ struct i915_vma *vma;
+ int err = -ENOMEM;
+
+ obj = i915_gem_object_create_internal(i915, npages*PAGE_SIZE);
+ if (IS_ERR(obj))
+ goto err;
+
+ for (loop = 0; loop <= 1; loop++) { /* exercise both create/lookup */
+ unsigned int count, nvma;
+
+ nvma = loop;
+ for_each_prime_number_from(sz, 1, npages) {
+ for_each_prime_number_from(offset, 0, npages - sz) {
+ struct i915_ggtt_view view;
+
+ view.type = I915_GGTT_VIEW_PARTIAL;
+ view.partial.offset_size =
+ offset << INTEL_PARTIAL_SIZE_BITS | (sz
- 1);
+
+ if (sz == npages)
+ view.type = I915_GGTT_VIEW_NORMAL;
+
+ vma = i915_gem_obj_lookup_or_create_vma(obj,
&i915->ggtt.base, &view);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_object;
+ }
+
+ if (!i915_vma_is_ggtt(vma)) {
+ pr_err("VMA is not in the GGTT!\n");
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto err_object;
+
+ if (vma->size != sz*PAGE_SIZE) {
+ pr_err("VMA is wrong size, expected
%lu, found %llu\n",
+ sz*PAGE_SIZE, vma->size);
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ if (vma->node.size < vma->size) {
+ pr_err("VMA binding too small, expected
%llu, found %llu\n",
+ vma->size, vma->node.size);
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ if (view.type != I915_GGTT_VIEW_NORMAL) {
+ if (memcmp(&vma->ggtt_view, &view,
sizeof(view))) {
+ pr_err("VMA mismatch upon
creation!\n");
+ err = -EINVAL;
+ goto err_object;
+ }
+
+ if (vma->pages == obj->mm.pages) {
+ pr_err("VMA using unrotated
object pages!\n");
+ err = -EINVAL;
+ goto err_object;
+ }
+ }
+
+ if (!assert_partial(obj, vma, offset, sz)) {
+ pr_err("Inconsistent partial p
[Intel-gfx] [PATCH 31/37] drm/i915: Test creation of VMA
Simple test to exercise creation and lookup of VMA within an object.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_vma.c| 3 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_vma.c | 176 +
3 files changed, 180 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_vma.c
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 6424352a69b2..af8738a84a85 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -621,3 +621,6 @@ int i915_vma_unbind(struct i915_vma *vma)
return 0;
}
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_vma.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 955a4d6ccdaf..b450eab7e6e1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -15,3 +15,4 @@ selftest(breadcrumbs, intel_breadcrumbs_mock_selftests)
selftest(requests, i915_gem_request_mock_selftests)
selftest(objects, i915_gem_object_mock_selftests)
selftest(dmabuf, i915_gem_dmabuf_mock_selftests)
+selftest(vma, i915_vma_mock_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
new file mode 100644
index ..ebd200245f88
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "i915_selftest.h"
+
+#include "mock_gem_device.h"
+#include "mock_context.h"
+
+static bool assert_vma(struct i915_vma *vma,
+ struct drm_i915_gem_object *obj,
+ struct i915_gem_context *ctx)
+{
+ if (vma->vm != &ctx->ppgtt->base) {
+ pr_err("VMA created with wrong VM\n");
+ return false;
+ }
+
+ if (vma->size != obj->base.size) {
+ pr_err("VMA created with wrong size, found %llu, expected
%zu\n",
+ vma->size, obj->base.size);
+ return false;
+ }
+
+ if (vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) {
+ pr_err("VMA created with wrong type [%d]\n",
+ vma->ggtt_view.type);
+ return false;
+ }
+
+ return true;
+}
+
+static int vma_create(struct drm_i915_private *i915,
+ struct list_head *objects,
+ struct list_head *contexts)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_gem_context *ctx;
+ int pinned;
+
+ list_for_each_entry(obj, objects, batch_pool_link) {
+ for (pinned = 0; pinned <= 1; pinned++) {
+ list_for_each_entry(ctx, contexts, link) {
+ struct i915_vma *vma;
+ int err;
+
+ vma = i915_gem_obj_lookup_or_create_vma(obj,
&ctx->ppgtt->base, NULL);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ if (!assert_vma(vma, obj, ctx)) {
+ pr_err("VMA lookup/create failed\n");
+ return -EINVAL;
+ }
+
+ if (!pinned) {
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ pr_err("Failed to pin VMA\n");
+ return err;
+ }
+ } else {
+
[Intel-gfx] [PATCH 21/37] drm/i915: Test all fw tables during mock selftests
In addition to just testing the fw table we load, during the initial
mock testing we can test that all tables are valid (so the testing is
not limited to just the platforms that load that particular table).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Reviewed-by: Matthew Auld
---
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/intel_uncore.c | 49 --
2 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
index 2ed94e3a71b7..c61e08de7913 100644
--- a/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_mock_selftests.h
@@ -10,6 +10,7 @@
*/
selftest(sanitycheck, i915_mock_sanitycheck) /* keep first (igt selfcheck) */
selftest(scatterlist, scatterlist_mock_selftests)
+selftest(uncore, intel_uncore_mock_selftests)
selftest(breadcrumbs, intel_breadcrumbs_mock_selftests)
selftest(requests, i915_gem_request_mock_selftests)
selftest(objects, i915_gem_object_mock_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 0ac467940a4f..c18fddb12d00 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -24,20 +24,16 @@
#include "i915_selftest.h"
-static int intel_fw_table_check(struct drm_i915_private *i915)
+static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
+ unsigned int num_ranges,
+ bool is_watertight)
{
- const struct intel_forcewake_range *ranges;
- unsigned int num_ranges, i;
+ unsigned int i;
s32 prev;
- ranges = i915->uncore.fw_domains_table;
- if (!ranges)
- return 0;
-
- num_ranges = i915->uncore.fw_domains_table_entries;
for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
/* Check that the table is watertight */
- if (IS_GEN9(i915) && (prev + 1) != (s32)ranges->start) {
+ if (is_watertight && (prev + 1) != (s32)ranges->start) {
pr_err("%s: entry[%d]:(%x, %x) is not watertight to
previous (%x)\n",
__func__, i, ranges->start, ranges->end, prev);
return -EINVAL;
@@ -83,15 +79,42 @@ static int intel_shadow_table_check(void)
return 0;
}
-int intel_uncore_live_selftests(struct drm_i915_private *i915)
+int intel_uncore_mock_selftests(void)
{
- int err;
+ struct {
+ const struct intel_forcewake_range *ranges;
+ unsigned int num_ranges;
+ bool is_watertight;
+ } fw[] = {
+ { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
+ { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
+ { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
+ };
+ int err, i;
+
+ for (i = 0; i < ARRAY_SIZE(fw); i++) {
+ err = intel_fw_table_check(fw[i].ranges,
+ fw[i].num_ranges,
+ fw[i].is_watertight);
+ if (err)
+ return err;
+ }
- err = intel_fw_table_check(i915);
+ err = intel_shadow_table_check();
if (err)
return err;
- err = intel_shadow_table_check();
+ return 0;
+}
+
+int intel_uncore_live_selftests(struct drm_i915_private *i915)
+{
+ int err;
+
+ /* Confirm the table we load is still valid */
+ err = intel_fw_table_check(i915->uncore.fw_domains_table,
+ i915->uncore.fw_domains_table_entries,
+ INTEL_GEN(i915) >= 9);
if (err)
return err;
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 19/37] drm/i915: Test coherency of and barriers between cache domains
Write into an object using WB, WC, GTT, and GPU paths and make sure that
our internal API is sufficient to ensure coherent reads and writes.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c| 1 +
.../gpu/drm/i915/selftests/i915_gem_coherency.c| 355 +
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
3 files changed, 357 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4a52c5872898..242d894b356e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4899,4 +4899,5 @@ i915_gem_object_get_dma_address(struct
drm_i915_gem_object *obj,
#include "selftests/mock_gem_device.c"
#include "selftests/huge_gem_object.c"
#include "selftests/i915_gem_object.c"
+#include "selftests/i915_gem_coherency.c"
#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
new file mode 100644
index ..3e57b7a3c73f
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include
+
+#include "i915_selftest.h"
+#include "i915_random.h"
+
+static int cpu_set(struct drm_i915_gem_object *obj,
+ unsigned long offset,
+ u32 v)
+{
+ unsigned int needs_clflush;
+ struct page *page;
+ typeof(v) *map;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush);
+ if (err)
+ return err;
+
+ page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
+ map = kmap_atomic(page);
+ if (needs_clflush & CLFLUSH_BEFORE)
+ clflush(map+offset_in_page(offset) / sizeof(*map));
+ map[offset_in_page(offset) / sizeof(*map)] = v;
+ if (needs_clflush & CLFLUSH_AFTER)
+ clflush(map+offset_in_page(offset) / sizeof(*map));
+ kunmap_atomic(map);
+
+ i915_gem_obj_finish_shmem_access(obj);
+ return 0;
+}
+
+static int cpu_get(struct drm_i915_gem_object *obj,
+ unsigned long offset,
+ u32 *v)
+{
+ unsigned int needs_clflush;
+ struct page *page;
+ typeof(v) map;
+ int err;
+
+ err = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
+ if (err)
+ return err;
+
+ page = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
+ map = kmap_atomic(page);
+ if (needs_clflush & CLFLUSH_BEFORE)
+ clflush(map+offset_in_page(offset) / sizeof(*map));
+ *v = map[offset_in_page(offset) / sizeof(*map)];
+ kunmap_atomic(map);
+
+ i915_gem_obj_finish_shmem_access(obj);
+ return 0;
+}
+
+static int gtt_set(struct drm_i915_gem_object *obj,
+ unsigned long offset,
+ u32 v)
+{
+ struct i915_vma *vma;
+ typeof(v) *map;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(obj, true);
+ if (err)
+ return err;
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ map = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ map[offset / sizeof(*map)] = v;
+ i915_vma_unpin_iomap(vma);
+
+ return 0;
+}
+
+static int gtt_get(struct drm_i915_gem_object *obj,
+ unsigned long offset,
+ u32 *v)
+{
+ struct i915_vma *vma;
+ typeof(v) map;
+ int err;
+
+ err = i915_gem_object_set_to_gtt_domain(obj, false);
+ if (err)
+ return err;
+
+ vma = i915_gem_object_gg
[Intel-gfx] [PATCH 32/37] drm/i915: Exercise i915_vma_pin/i915_vma_insert
High-level testing of the struct drm_mm by verifying our handling of
weird requests to i915_vma_pin.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_vma.c | 4 +-
drivers/gpu/drm/i915/i915_vma.h | 4 +-
drivers/gpu/drm/i915/selftests/i915_vma.c | 133 ++
3 files changed, 137 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index af8738a84a85..38c5f1039569 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -259,8 +259,8 @@ void i915_vma_unpin_and_release(struct i915_vma **p_vma)
__i915_gem_object_release_unless_active(obj);
}
-bool
-i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
+bool i915_vma_misplaced(const struct i915_vma *vma,
+ u64 size, u64 alignment, u64 flags)
{
if (!drm_mm_node_allocated(&vma->node))
return false;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 47b5ceb386c4..7211c9bef637 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -218,8 +218,8 @@ i915_vma_compare(struct i915_vma *vma,
int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
u32 flags);
bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long cache_level);
-bool
-i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags);
+bool i915_vma_misplaced(const struct i915_vma *vma,
+ u64 size, u64 alignment, u64 flags);
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
int __must_check i915_vma_unbind(struct i915_vma *vma);
void i915_vma_close(struct i915_vma *vma);
diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c
b/drivers/gpu/drm/i915/selftests/i915_vma.c
index ebd200245f88..d229adabc5f8 100644
--- a/drivers/gpu/drm/i915/selftests/i915_vma.c
+++ b/drivers/gpu/drm/i915/selftests/i915_vma.c
@@ -155,10 +155,143 @@ static int igt_vma_create(void *arg)
return err;
}
+struct pin_mode {
+ u64 size;
+ u64 flags;
+ bool (*assert)(const struct i915_vma *,
+ const struct pin_mode *mode,
+ int result);
+};
+
+static bool assert_pin_valid(const struct i915_vma *vma,
+const struct pin_mode *mode,
+int result)
+{
+ if (result)
+ return false;
+
+ if (i915_vma_misplaced(vma, mode->size, 0, mode->flags))
+ return false;
+
+ return true;
+}
+
+__maybe_unused
+static bool assert_pin_e2big(const struct i915_vma *vma,
+const struct pin_mode *mode,
+int result)
+{
+ return result == -E2BIG;
+}
+
+__maybe_unused
+static bool assert_pin_enospc(const struct i915_vma *vma,
+ const struct pin_mode *mode,
+ int result)
+{
+ return result == -ENOSPC;
+}
+
+__maybe_unused
+static bool assert_pin_einval(const struct i915_vma *vma,
+ const struct pin_mode *mode,
+ int result)
+{
+ return result == -EINVAL;
+}
+
+static int igt_vma_pin1(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ const struct pin_mode modes[] = {
+ [0] = { 0, PIN_GLOBAL, assert_pin_valid },
+ [1] = { 0, PIN_GLOBAL | PIN_MAPPABLE, assert_pin_valid },
+
+ [2] = { 0, PIN_GLOBAL | PIN_OFFSET_BIAS | 4096,
assert_pin_valid },
+ [3] = { 0, PIN_GLOBAL | PIN_OFFSET_BIAS | 8192,
assert_pin_valid },
+ [4] = { 0, PIN_GLOBAL | PIN_OFFSET_BIAS |
(i915->ggtt.mappable_end - 4096), assert_pin_valid },
+ [5] = { 0, PIN_GLOBAL | PIN_MAPPABLE | PIN_OFFSET_BIAS |
(i915->ggtt.mappable_end - 4096), assert_pin_valid },
+ [6] = { 0, PIN_GLOBAL | PIN_OFFSET_BIAS |
(i915->ggtt.base.total - 4096), assert_pin_valid },
+
+ [7] = { 0, PIN_GLOBAL | PIN_MAPPABLE | PIN_OFFSET_FIXED |
(i915->ggtt.mappable_end - 4096), assert_pin_valid },
+ [8] = { 0, PIN_GLOBAL | PIN_MAPPABLE | PIN_OFFSET_FIXED |
i915->ggtt.mappable_end, assert_pin_einval },
+ [9] = { 0, PIN_GLOBAL | PIN_OFFSET_FIXED |
(i915->ggtt.base.total - 4096), assert_pin_valid },
+ [10] = { 0, PIN_GLOBAL | PIN_OFFSET_FIXED |
i915->ggtt.base.total, assert_pin_einval },
+ [11] = { 0, PIN_GLOBAL | PIN_OFFSET_FIXED | round_down(U64_MAX,
PAGE_SIZE), assert_pin_einval },
+
+ [12] = { 4096, PIN_GLOBAL, assert_pin_valid },
+ [13] = { 8192, PIN_GLOBAL, assert_pin_valid },
+ [14] = { i915->ggtt.mappable_end - 4096, PIN_GLOBAL |
PIN_MAPPABLE, assert_pin_valid },
+ [15] = { i915->ggtt.mappable_end, PIN_GLOBAL | PIN_MAPPABLE,
assert_pin_valid },
+
[Intel-gfx] [PATCH 18/37] drm/i915: Test exhaustion of the mmap space
An unlikely error condition that we can simulate by stealing the most of
the range before trying to insert new objects.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_object.c | 137 +++
1 file changed, 137 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
index df3625f551aa..46512a67877d 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c
@@ -25,6 +25,7 @@
#include "i915_selftest.h"
#include "mock_gem_device.h"
+#include "huge_gem_object.h"
static int igt_gem_object(void *arg)
{
@@ -383,6 +384,141 @@ static int igt_partial_tiling(void *arg)
return err;
}
+static int make_obj_busy(struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_i915_gem_request *rq;
+ struct i915_vma *vma;
+ int err;
+
+ vma = i915_gem_obj_lookup_or_create_vma(obj, &i915->ggtt.base, NULL);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err)
+ return err;
+
+ rq = i915_gem_request_alloc(i915->engine[RCS], i915->kernel_context);
+ if (IS_ERR(rq)) {
+ i915_vma_unpin(vma);
+ return PTR_ERR(rq);
+ }
+
+ i915_vma_move_to_active(vma, rq, 0);
+ i915_add_request(rq);
+
+ i915_gem_object_set_active_reference(obj);
+ i915_vma_unpin(vma);
+ return 0;
+}
+
+static bool assert_mmap_offset(struct drm_i915_private *i915,
+ unsigned long size,
+ int expected)
+{
+ struct drm_i915_gem_object *obj;
+ int err;
+
+ obj = i915_gem_object_create_internal(i915, size);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ err = i915_gem_object_create_mmap_offset(obj);
+ i915_gem_object_put(obj);
+
+ return err == expected;
+}
+
+static int igt_mmap_offset_exhaustion(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct drm_mm *mm = &i915->drm.vma_offset_manager->vm_addr_space_mm;
+ struct drm_i915_gem_object *obj;
+ struct drm_mm_node resv, *hole;
+ u64 hole_start, hole_end;
+ int loop, err;
+
+ /* Trim the VMA mmap space to only a page */
+ memset(&resv, 0, sizeof(resv));
+ drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
+ resv.start = hole_start;
+ resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
+ err = drm_mm_reserve_node(mm, &resv);
+ if (err) {
+ pr_err("Failed to trim VMA manager, err=%d\n", err);
+ return err;
+ }
+ break;
+ }
+
+ /* Just fits! */
+ if (!assert_mmap_offset(i915, PAGE_SIZE, 0)) {
+ pr_err("Unable to insert object into single page hole\n");
+ err = -EINVAL;
+ goto err;
+ }
+
+ /* Too large */
+ if (!assert_mmap_offset(i915, 2*PAGE_SIZE, -ENOSPC)) {
+ pr_err("Unexpectedly succeded in inserting too large object
into single page hole\n");
+ err = -EINVAL;
+ goto err;
+ }
+
+ /* Fill the hole, should then fail */
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err;
+ }
+
+ err = i915_gem_object_create_mmap_offset(obj);
+ if (err) {
+ pr_err("Unable to insert object into reclaimed hole\n");
+ goto err_obj;
+ }
+
+ if (!assert_mmap_offset(i915, PAGE_SIZE, -ENOSPC)) {
+ pr_err("Unexpectedly succeded in inserting object into no
holes!\n");
+ err = -EINVAL;
+ goto err_obj;
+ }
+
+ i915_gem_object_put(obj);
+
+ /* Now fill with busy dead objects that we expect to reap */
+ for (loop = 0; loop < 3; loop++) {
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err;
+ }
+
+ mutex_lock(&i915->drm.struct_mutex);
+ err = make_obj_busy(obj);
+ mutex_unlock(&i915->drm.struct_mutex);
+ if (err) {
+ pr_err("[loop %d] Failed to busy the object\n", loop);
+ goto err_obj;
+ }
+
+ err = i915_gem_object_create_mmap_offset(obj);
+ if (err) {
+ pr_err("[loop %d] i915_gem_object_create_mmap_offset
failed with err=%d\n",
+ loop, err);
+ goto err;
+ }
+ }
+
+err:
+ drm_mm_rem
[Intel-gfx] [PATCH 29/37] drm/i915: Fill different pages of the GTT
Exercise filling different pages of the GTT
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 130 ++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 8ed88f438eef..68f7bfb7502e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -231,6 +231,65 @@ static int fill_hole(struct drm_i915_private *i915,
return err;
}
+static int walk_hole(struct drm_i915_private *i915,
+struct i915_address_space *vm,
+u64 hole_start, u64 hole_end)
+{
+ I915_SELFTEST_TIMEOUT(end_time);
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u64 addr;
+ int err;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vma = vma_lookup(obj, vm);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err;
+ }
+
+ for (addr = hole_start; addr < hole_end; addr += PAGE_SIZE) {
+ cond_resched();
+
+ err = i915_vma_pin(vma, 0, 0,
+ addr | PIN_OFFSET_FIXED | PIN_USER);
+ if (err) {
+ pr_err("Walk bind failed at %llx with err=%d\n",
+ addr, err);
+ break;
+ }
+ i915_vma_unpin(vma);
+
+ if (!drm_mm_node_allocated(&vma->node) ||
+ i915_vma_misplaced(vma, 0, 0, addr | PIN_OFFSET_FIXED)) {
+ pr_err("Walk incorrect at %llx\n", addr);
+ err = -EINVAL;
+ break;
+ }
+
+ err = i915_vma_unbind(vma);
+ if (err) {
+ pr_err("Walk unbind failed at %llx with err=%d\n",
+ addr, err);
+ break;
+ }
+
+ if (time_after(jiffies, end_time)) {
+ pr_warn("Walk timed out at %llx\n", addr);
+ break;
+ }
+ }
+
+ if (!i915_vma_is_ggtt(vma))
+ i915_vma_close(vma);
+err:
+ i915_gem_object_put(obj);
+ return err;
+}
+
static int igt_ppgtt_fill(void *arg)
{
struct drm_i915_private *dev_priv = arg;
@@ -264,6 +323,39 @@ static int igt_ppgtt_fill(void *arg)
return err;
}
+static int igt_ppgtt_walk(void *arg)
+{
+ struct drm_i915_private *dev_priv = arg;
+ struct drm_file *file;
+ struct i915_hw_ppgtt *ppgtt;
+ int err;
+
+ if (!USES_FULL_PPGTT(dev_priv))
+ return 0;
+
+ file = fake_file(dev_priv);
+ if (IS_ERR(file))
+ return PTR_ERR(file);
+
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ ppgtt = i915_ppgtt_create(dev_priv, file->driver_priv, "mock");
+ if (IS_ERR(ppgtt)) {
+ err = PTR_ERR(ppgtt);
+ goto err_unlock;
+ }
+ GEM_BUG_ON(ppgtt->base.total & ~PAGE_MASK);
+
+ err = walk_hole(dev_priv, &ppgtt->base, 0, ppgtt->base.total);
+
+ i915_ppgtt_close(&ppgtt->base);
+ i915_ppgtt_put(ppgtt);
+err_unlock:
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
+ fake_file_free(dev_priv, file);
+ return err;
+}
+
static int igt_ggtt_fill(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -300,11 +392,49 @@ static int igt_ggtt_fill(void *arg)
return err;
}
+static int igt_ggtt_walk(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ u64 hole_start = U64_MAX, hole_end = 0, hole_size = 0;
+ u64 this_start, this_end;
+ struct drm_mm_node *node;
+ int err;
+
+ GEM_BUG_ON(ggtt->base.total & ~PAGE_MASK);
+
+ mutex_lock(&i915->drm.struct_mutex);
+ drm_mm_for_each_hole(node, &ggtt->base.mm, this_start, this_end) {
+ u64 this_size;
+
+ if (ggtt->base.mm.color_adjust)
+ ggtt->base. mm.color_adjust(node, 0,
+ &this_start, &this_end);
+
+ this_size = this_end - this_start;
+ if (this_size > hole_size) {
+ hole_size = this_size;
+ hole_start = this_start;
+ hole_end = this_end;
+ }
+ }
+ pr_info("Found GGTT hole [%llx, %llx], size %llx\n",
+ hole_start, hole_end, hole_size);
+ GEM_BUG_ON(hole_start >= hole_end);
+
+ err = walk_hole(i915, &ggtt->base, hole_start, hole_end);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ return err;
+}
+
int i915_gem_gtt_live_selftests(struct drm_i915_private *i915)
{
static const struct
[Intel-gfx] [PATCH 28/37] drm/i915: Exercising filling the top/bottom portions of the global GTT
Same test as previously for the per-process GTT instead applied to the
global GTT.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 118 +++---
1 file changed, 88 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 5d0e6f60bea7..8ed88f438eef 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -25,6 +25,7 @@
#include
#include "i915_selftest.h"
+#include "fake_drm.h"
#include "huge_gem_object.h"
static int igt_ppgtt_alloc(void *arg)
@@ -94,35 +95,25 @@ static struct i915_vma *vma_lookup(struct
drm_i915_gem_object *obj,
return i915_gem_obj_lookup_or_create_vma(obj, vm, NULL);
}
-static int igt_ppgtt_fill(void *arg)
+static int fill_hole(struct drm_i915_private *i915,
+struct i915_address_space *vm,
+u64 hole_start, u64 hole_end)
{
- struct drm_i915_private *dev_priv = arg;
unsigned long npages, max_pages = 1 << 20, prime;
+ u64 hole_size = hole_end - hole_start;
struct drm_i915_gem_object *obj, *on;
- struct i915_hw_ppgtt *ppgtt;
struct i915_vma *vma;
LIST_HEAD(objects);
- int err = 0;
-
- if (!USES_FULL_PPGTT(dev_priv))
- return 0;
-
- mutex_lock(&dev_priv->drm.struct_mutex);
- ppgtt = i915_ppgtt_create(dev_priv, NULL, "mock");
- if (IS_ERR(ppgtt)) {
- err = PTR_ERR(ppgtt);
- goto err_unlock;
- }
- GEM_BUG_ON(ppgtt->base.total & ~PAGE_MASK);
+ int err;
- max_pages = min_t(u64, max_pages, ppgtt->base.total/2 >> PAGE_SHIFT);
+ max_pages = min_t(u64, max_pages, hole_size/2 >> PAGE_SHIFT);
for_each_prime_number_from(prime, 2, 13) {
for (npages = 1; npages <= max_pages; npages *= prime) {
u64 flags;
GEM_BUG_ON(!npages);
- obj = huge_gem_object(dev_priv,
+ obj = huge_gem_object(i915,
PAGE_SIZE,
npages << PAGE_SHIFT);
if (IS_ERR(obj))
@@ -131,9 +122,9 @@ static int igt_ppgtt_fill(void *arg)
list_add(&obj->batch_pool_link, &objects);
/* Fill the GTT top down - hope we don't overstep the
end */
- flags = ppgtt->base.total | PIN_OFFSET_FIXED | PIN_USER;
+ flags = hole_end | PIN_OFFSET_FIXED | PIN_USER;
list_for_each_entry(obj, &objects, batch_pool_link) {
- vma = vma_lookup(obj, &ppgtt->base);
+ vma = vma_lookup(obj, vm);
if (IS_ERR(vma))
continue;
@@ -147,9 +138,9 @@ static int igt_ppgtt_fill(void *arg)
i915_vma_unpin(vma);
}
- flags = ppgtt->base.total | PIN_OFFSET_FIXED | PIN_USER;
+ flags = hole_end | PIN_OFFSET_FIXED | PIN_USER;
list_for_each_entry(obj, &objects, batch_pool_link) {
- vma = vma_lookup(obj, &ppgtt->base);
+ vma = vma_lookup(obj, vm);
if (IS_ERR(vma))
continue;
@@ -173,9 +164,9 @@ static int igt_ppgtt_fill(void *arg)
}
/* And again from the bottom */
- flags = PIN_OFFSET_FIXED | PIN_USER;
+ flags = hole_start | PIN_OFFSET_FIXED | PIN_USER;
list_for_each_entry(obj, &objects, batch_pool_link) {
- vma = vma_lookup(obj, &ppgtt->base);
+ vma = vma_lookup(obj, vm);
if (IS_ERR(vma))
continue;
@@ -189,9 +180,9 @@ static int igt_ppgtt_fill(void *arg)
flags += obj->base.size;
}
- flags = PIN_OFFSET_FIXED | PIN_USER;
+ flags = hole_start | PIN_OFFSET_FIXED | PIN_USER;
list_for_each_entry(obj, &objects, batch_pool_link) {
- vma = vma_lookup(obj, &ppgtt->base);
+ vma = vma_lookup(obj, vm);
if (IS_ERR(vma))
continue;
@@ -218,28 +209,94 @@ static int igt_ppgtt_fill(void *arg)
list_for_each_entry_safe(obj, on, &objects, batch_pool_link) {
list_del(&obj->batch_pool_link);
- vma = vma_lookup(obj, &pp
[Intel-gfx] [PATCH 22/37] drm/i915: Sanity check all registers for matching fw domains
Add a late selftest that walks over all forcewake registers (those below
0x4) and uses the mmio debug register to check to see if any are
unclaimed. This is possible if we fail to wake the appropriate
powerwells for the register.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/selftests/intel_uncore.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c
b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index c18fddb12d00..fba76fef4d55 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -107,6 +107,50 @@ int intel_uncore_mock_selftests(void)
return 0;
}
+static int intel_uncore_check_forcewake_domains(struct drm_i915_private
*dev_priv)
+{
+#define FW_RANGE 0x4
+ unsigned long *valid;
+ u32 offset;
+ int err;
+
+ valid = kzalloc(BITS_TO_LONGS(FW_RANGE) * sizeof(*valid),
+ GFP_TEMPORARY);
+ if (!valid)
+ return -ENOMEM;
+
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+ check_for_unclaimed_mmio(dev_priv);
+ for (offset = 0; offset < FW_RANGE; offset += 4) {
+ i915_reg_t reg = { offset };
+
+ (void)I915_READ_FW(reg);
+ if (!check_for_unclaimed_mmio(dev_priv))
+ set_bit(offset, valid);
+ }
+
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ err = 0;
+ for_each_set_bit(offset, valid, FW_RANGE) {
+ i915_reg_t reg = { offset };
+
+ intel_uncore_forcewake_reset(dev_priv, false);
+ check_for_unclaimed_mmio(dev_priv);
+
+ (void)I915_READ(reg);
+ if (check_for_unclaimed_mmio(dev_priv)) {
+ pr_err("Unclaimed mmio read to register 0x%04x\n",
+ offset);
+ err = -EINVAL;
+ }
+ }
+
+ kfree(valid);
+ return err;
+}
+
int intel_uncore_live_selftests(struct drm_i915_private *i915)
{
int err;
@@ -118,5 +162,9 @@ int intel_uncore_live_selftests(struct drm_i915_private
*i915)
if (err)
return err;
+ err = intel_uncore_check_forcewake_domains(i915);
+ if (err)
+ return err;
+
return 0;
}
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 37/37] drm/i915: Add initial selftests for hang detection and resets
Check that we can reset the GPU and continue executing from the next
request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_hangcheck.c | 4 +
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 455 +
3 files changed, 460 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/intel_hangcheck.c
diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c
b/drivers/gpu/drm/i915/intel_hangcheck.c
index f05971f5586f..dce742243ba6 100644
--- a/drivers/gpu/drm/i915/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/intel_hangcheck.c
@@ -480,3 +480,7 @@ void intel_hangcheck_init(struct drm_i915_private *i915)
INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
i915_hangcheck_elapsed);
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/intel_hangcheck.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 0c925f17b445..e6699c59f244 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -15,3 +15,4 @@ selftest(object, i915_gem_object_live_selftests)
selftest(coherency, i915_gem_coherency_live_selftests)
selftest(gtt, i915_gem_gtt_live_selftests)
selftest(context, i915_gem_context_live_selftests)
+selftest(hangcheck, intel_hangcheck_live_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
new file mode 100644
index ..6d2741624f81
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -0,0 +1,455 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+
+struct hang {
+ struct drm_i915_private *i915;
+ struct drm_i915_gem_object *hws;
+ struct drm_i915_gem_object *obj;
+ u32 *seqno;
+ u32 *batch;
+};
+
+static int hang_init(struct hang *h, struct drm_i915_private *i915)
+{
+ void *vaddr;
+
+ memset(h, 0, sizeof(*h));
+ h->i915 = i915;
+
+ h->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(h->hws))
+ return PTR_ERR(h->hws);
+
+ h->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(h->obj)) {
+ i915_gem_object_put(h->obj);
+ return PTR_ERR(h->obj);
+ }
+
+ i915_gem_object_set_cache_level(h->hws, I915_CACHE_LLC);
+ vaddr = i915_gem_object_pin_map(h->hws, I915_MAP_WB);
+ if (IS_ERR(vaddr)) {
+ i915_gem_object_put(h->hws);
+ i915_gem_object_put(h->obj);
+ return PTR_ERR(vaddr);
+ }
+ h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
+
+ vaddr = i915_gem_object_pin_map(h->obj,
+ HAS_LLC(i915) ? I915_MAP_WB :
I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ i915_gem_object_unpin_map(h->hws);
+ i915_gem_object_put(h->hws);
+ i915_gem_object_put(h->obj);
+ return PTR_ERR(vaddr);
+ }
+ h->batch = vaddr;
+
+ return 0;
+}
+
+static u64 hws_address(const struct i915_vma *hws,
+ const struct drm_i915_gem_request *rq)
+{
+ return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
+}
+
+static int emit_recurse_batch(struct hang *h,
+ struct drm_i915_gem_request *rq)
+{
+ struct drm_i915_private *i915 = h->i915;
+ struct i915_address_space *vm = rq->ctx->ppgtt ? &rq->ctx->ppgtt->base
: &i915->ggtt.base;
+ struct i915_vma *hws, *vma;
+ u32 *batch;
+ int err;
+
+ vma = i915_gem_obj_lookup_or_create_vma(h->obj, vm, NULL);
+ if (IS_ERR(vma))
+
[Intel-gfx] [PATCH 36/37] drm/i915: Initial selftests for exercising eviction
Very simple tests to just ask eviction to find some free space in a full
GTT and one with some available space.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_evict.c | 4 +
drivers/gpu/drm/i915/selftests/i915_gem_evict.c| 232 +
.../gpu/drm/i915/selftests/i915_mock_selftests.h | 1 +
3 files changed, 237 insertions(+)
create mode 100644 drivers/gpu/drm/i915/selftests/i915_gem_evict.c
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index c181b1bb3d2c..609a8fcb48ca 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -387,3 +387,7 @@ int i915_gem_evict_vm(struct i915_address_space *vm, bool
do_idle)
return 0;
}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftests/i915_gem_evict.c"
+#endif
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
new file mode 100644
index ..f3730abac5fb
--- /dev/null
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_selftest.h"
+
+#include "mock_gem_device.h"
+
+static int populate_ggtt(struct drm_i915_private *i915)
+{
+ struct drm_i915_gem_object *obj;
+ u64 size;
+
+ for (size = 0; size < i915->ggtt.base.total; size += PAGE_SIZE) {
+ struct i915_vma *vma;
+
+ obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+ }
+
+ if (!list_empty(&i915->mm.unbound_list)) {
+ size = 0;
+ list_for_each_entry(obj, &i915->mm.unbound_list, global_link)
+ size++;
+
+ pr_err("Found %lld objects unbound!\n", size);
+ return -EINVAL;
+ }
+
+ if (list_empty(&i915->ggtt.base.inactive_list)) {
+ pr_err("No objects on the GGTT inactive list!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void unpin_ggtt(struct drm_i915_private *i915)
+{
+ struct i915_vma *vma;
+
+ list_for_each_entry(vma, &i915->ggtt.base.inactive_list, vm_link)
+ i915_vma_unpin(vma);
+}
+
+static void cleanup_objects(struct drm_i915_private *i915)
+{
+ struct drm_i915_gem_object *obj, *on;
+
+ list_for_each_entry_safe(obj, on, &i915->mm.unbound_list, global_link)
+ i915_gem_object_put(obj);
+
+ list_for_each_entry_safe(obj, on, &i915->mm.bound_list, global_link)
+ i915_gem_object_put(obj);
+
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ i915_gem_drain_freed_objects(i915);
+
+ mutex_lock(&i915->drm.struct_mutex);
+}
+
+static int igt_evict_something(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct i915_ggtt *ggtt = &i915->ggtt;
+ int err;
+
+ err = populate_ggtt(i915);
+ if (err)
+ goto cleanup;
+
+ err = i915_gem_evict_something(&ggtt->base,
+ PAGE_SIZE, 0, 0,
+ 0, U64_MAX,
+ 0);
+ if (err != -ENOSPC) {
+ pr_err("i915_gem_evict_something failed on a full GGTT with
err=%d\n",
+ err);
+ goto cleanup;
+ }
+
+ unpin_ggtt(i915);
+
+ err = i915_gem_evict_something(&ggtt->base,
+ PAGE_SIZE, 0, 0,
+ 0, U64_MAX,
+ 0);
+
[Intel-gfx] [PATCH v4] drm/i915/scheduler: emulate a scheduler for guc
This emulates execlists on top of the GuC in order to defer submission of
requests to the hardware. This deferral allows time for high priority
requests to gazump their way to the head of the queue, however it nerfs
the GuC by converting it back into a simple execlist (where the CPU has
to wake up after every request to feed new commands into the GuC).
v2: Drop hack status - though iirc there is still a lockdep inversion
between fence and engine->timeline->lock (which is impossible as the
nesting only occurs on different fences - hopefully just requires some
judicious lockdep annotation)
v3: Apply lockdep nesting to enabling signaling on the request, using
the pattern we already have in __i915_gem_request_submit();
v4: Replaying requests after a hang also now needs the timeline
spinlock, to disable the interrupts at least
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_guc_submission.c | 95 +++---
drivers/gpu/drm/i915/i915_irq.c| 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 5 +-
3 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 913d87358972..2f0a853f820a 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -350,7 +350,7 @@ int i915_guc_wq_reserve(struct drm_i915_gem_request
*request)
u32 freespace;
int ret;
- spin_lock(&client->wq_lock);
+ spin_lock_irq(&client->wq_lock);
freespace = CIRC_SPACE(client->wq_tail, desc->head, client->wq_size);
freespace -= client->wq_rsvd;
if (likely(freespace >= wqi_size)) {
@@ -360,7 +360,7 @@ int i915_guc_wq_reserve(struct drm_i915_gem_request
*request)
client->no_wq_space++;
ret = -EAGAIN;
}
- spin_unlock(&client->wq_lock);
+ spin_unlock_irq(&client->wq_lock);
return ret;
}
@@ -372,9 +372,9 @@ void i915_guc_wq_unreserve(struct drm_i915_gem_request
*request)
GEM_BUG_ON(READ_ONCE(client->wq_rsvd) < wqi_size);
- spin_lock(&client->wq_lock);
+ spin_lock_irq(&client->wq_lock);
client->wq_rsvd -= wqi_size;
- spin_unlock(&client->wq_lock);
+ spin_unlock_irq(&client->wq_lock);
}
/* Construct a Work Item and append it to the GuC's Work Queue */
@@ -534,10 +534,87 @@ static void __i915_guc_submit(struct drm_i915_gem_request
*rq)
static void i915_guc_submit(struct drm_i915_gem_request *rq)
{
- i915_gem_request_submit(rq);
+ __i915_gem_request_submit(rq);
__i915_guc_submit(rq);
}
+static void nested_enable_signaling(struct drm_i915_gem_request *rq)
+{
+ if (test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
+&rq->fence.flags))
+ return;
+
+ GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
+
+ spin_lock_nested(&rq->lock, SINGLE_DEPTH_NESTING);
+ intel_engine_enable_signaling(rq);
+ spin_unlock(&rq->lock);
+}
+
+static bool i915_guc_dequeue(struct intel_engine_cs *engine)
+{
+ struct execlist_port *port = engine->execlist_port;
+ struct drm_i915_gem_request *last = port[0].request;
+ unsigned long flags;
+ struct rb_node *rb;
+ bool submit = false;
+
+ spin_lock_irqsave(&engine->timeline->lock, flags);
+ rb = engine->execlist_first;
+ while (rb) {
+ struct drm_i915_gem_request *cursor =
+ rb_entry(rb, typeof(*cursor), priotree.node);
+
+ if (last && cursor->ctx != last->ctx) {
+ if (port != engine->execlist_port)
+ break;
+
+ i915_gem_request_assign(&port->request, last);
+ nested_enable_signaling(last);
+ port++;
+ }
+
+ rb = rb_next(rb);
+ rb_erase(&cursor->priotree.node, &engine->execlist_queue);
+ RB_CLEAR_NODE(&cursor->priotree.node);
+ cursor->priotree.priority = INT_MAX;
+
+ i915_guc_submit(cursor);
+ last = cursor;
+ submit = true;
+ }
+ if (submit) {
+ i915_gem_request_assign(&port->request, last);
+ nested_enable_signaling(last);
+ engine->execlist_first = rb;
+ }
+ spin_unlock_irqrestore(&engine->timeline->lock, flags);
+
+ return submit;
+}
+
+static void i915_guc_irq_handler(unsigned long data)
+{
+ struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
+ struct execlist_port *port = engine->execlist_port;
+ struct drm_i915_gem_request *rq;
+ bool submit;
+
+ do {
+ rq = port[0].request;
+ while (rq && i915_gem_request_completed(rq)) {
+ i915_gem_request_put(rq);
+
Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Add render decompression support
On Tue, Jan 10, 2017 at 9:04 AM, Ville Syrjälä <
ville.syrj...@linux.intel.com> wrote:
> On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote:
> > On Thu, Jan 5, 2017 at 7:14 AM, wrote:
> >
> > > From: Ville Syrjälä
> > >
> > > SKL+ display engine can scan out certain kinds of compressed surfaces
> > > produced by the render engine. This involved telling the display engine
> > > the location of the color control surfae (CCS) which describes
> > > which parts of the main surface are compressed and which are not. The
> > > location of CCS is provided by userspace as just another plane with its
> > > own offset.
> > >
> > > Add the required stuff to validate the user provided AUX plane metadata
> > > and convert the user provided linear offset into something the hardware
> > > can consume.
> > >
> > > Due to hardware limitations we require that the main surface and
> > > the AUX surface (CCS) be part of the same bo. The hardware also
> > > makes life hard by not allowing you to provide separate x/y offsets
> > > for the main and AUX surfaces (excpet with NV12), so finding suitable
> > > offsets for both requires a bit of work. Assuming we still want keep
> > > playing tricks with the offsets. I've just gone with a dumb "search
> > > backward for suitable offsets" approach, which is far from optimal,
> > > but it works.
> > >
> > > Also not all planes will be capable of scanning out compressed
> surfaces,
> > > and eg. 90/270 degree rotation is not supported in combination with
> > > decompression either.
> > >
> > > This patch may contain work from at least the following people:
> > > * Vandana Kannan
> > > * Daniel Vetter
> > > * Ben Widawsky
> > >
> > > v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
> > >
> > > Cc: Paulo Zanoni
> > > Cc: Vandana Kannan
> > > Cc: Daniel Vetter
> > > Cc: Ben Widawsky
> > > Cc: Jason Ekstrand
> > > Signed-off-by: Ville Syrjälä
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 23
> > > drivers/gpu/drm/i915/intel_display.c | 234
> ++
> > > ++---
> > > drivers/gpu/drm/i915/intel_pm.c | 29 -
> > > drivers/gpu/drm/i915/intel_sprite.c | 5 +
> > > 4 files changed, 274 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_
> > > reg.h
> > > index 00970aa77afa..6849ba93f1d9 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6209,6 +6209,28 @@ enum {
> > > _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
> > > _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
> > >
> > > +#define PLANE_AUX_DIST_1_A 0x701c0
> > > +#define PLANE_AUX_DIST_2_A 0x702c0
> > > +#define PLANE_AUX_DIST_1_B 0x711c0
> > > +#define PLANE_AUX_DIST_2_B 0x712c0
> > > +#define _PLANE_AUX_DIST_1(pipe) \
> > > + _PIPE(pipe, PLANE_AUX_DIST_1_A,
> PLANE_AUX_DIST_1_B)
> > > +#define _PLANE_AUX_DIST_2(pipe) \
> > > + _PIPE(pipe, PLANE_AUX_DIST_2_A,
> PLANE_AUX_DIST_2_B)
> > > +#define PLANE_AUX_DIST(pipe, plane) \
> > > + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
> > > _PLANE_AUX_DIST_2(pipe))
> > > +
> > > +#define PLANE_AUX_OFFSET_1_A 0x701c4
> > > +#define PLANE_AUX_OFFSET_2_A 0x702c4
> > > +#define PLANE_AUX_OFFSET_1_B 0x711c4
> > > +#define PLANE_AUX_OFFSET_2_B 0x712c4
> > > +#define _PLANE_AUX_OFFSET_1(pipe) \
> > > + _PIPE(pipe, PLANE_AUX_OFFSET_1_A, PLANE_AUX_OFFSET_1_B)
> > > +#define _PLANE_AUX_OFFSET_2(pipe) \
> > > + _PIPE(pipe, PLANE_AUX_OFFSET_2_A, PLANE_AUX_OFFSET_2_B)
> > > +#define PLANE_AUX_OFFSET(pipe, plane) \
> > > + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
> > > _PLANE_AUX_OFFSET_2(pipe))
> > > +
> > > /* legacy palette */
> > > #define _LGC_PALETTE_A 0x4a000
> > > #define _LGC_PALETTE_B 0x4a800
> > > @@ -6433,6 +6455,7 @@ enum {
> > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
> > >
> > > #define CHICKEN_PAR1_1 _MMIO(0x42080)
> > > +#define SKL_RC_HASH_OUTSIDE (1 << 15)
> > > #define DPA_MASK_VBLANK_SRD (1 << 15)
> > > #define FORCE_ARB_IDLE_PLANES (1 << 14)
> > > #define SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 38de9df0ec60..2236abebd8bc 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
> > > drm_framebuffer *fb, int plane)
> > > return 128;
> > > else
> > > return 512;
> > > + case I915_FORMAT_MOD_Y_TILED_CCS:
> > > + if (plane == 1)
> > > + return 64;
> > > +
[Intel-gfx] Anonymous ggtt_view params
It makes reading the vma->ggtt_view code more pleasant, but at an unfortunate cost in header complexity to ensure that no unwanted bits are in the struct and that gcc doesn't double the size of a few inlined functions. I like it, but I am biased. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/6] drm/i915: Compact memcmp in i915_vma_compare()
In preparation for the next patch to convert to using an anonymous union
and leaving the excess bytes in the union uninitialised, we first need
to make sure we do not compare using those uninitialised bytes. We also
want to preserve the compactness of the code, avoiding a second call to
memcmp or introducing a switch, so we take advantage of using the type
as an encoded size (as well as a unique identifier for each type of view).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +++---
drivers/gpu/drm/i915/i915_vma.h | 15 +--
2 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 3187a260e6e1..36d85599ffc9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -145,12 +145,6 @@ typedef uint64_t gen8_ppgtt_pml4e_t;
struct sg_table;
-enum i915_ggtt_view_type {
- I915_GGTT_VIEW_NORMAL = 0,
- I915_GGTT_VIEW_ROTATED,
- I915_GGTT_VIEW_PARTIAL,
-};
-
struct intel_rotation_info {
struct intel_rotation_plane_info {
/* tiles */
@@ -184,10 +178,16 @@ static inline u64 intel_partial_get_page_offset(const
struct intel_partial_info
return pi->offset_size >> INTEL_PARTIAL_SIZE_BITS;
}
+enum i915_ggtt_view_type {
+ I915_GGTT_VIEW_NORMAL = 0,
+ I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
+ I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
+};
+
struct i915_ggtt_view {
enum i915_ggtt_view_type type;
-
union {
+ /* Members need to contain no holes/padding */
struct intel_partial_info partial;
struct intel_rotation_info rotated;
} params;
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index a969bbb65871..19f049cef9e3 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -199,15 +199,18 @@ i915_vma_compare(struct i915_vma *vma,
if (cmp)
return cmp;
+ BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL != 0);
+ cmp = vma->ggtt_view.type;
if (!view)
- return vma->ggtt_view.type;
+ return cmp;
+
+ cmp -= view->type;
+ if (cmp)
+ return cmp;
- if (vma->ggtt_view.type != view->type)
- return vma->ggtt_view.type - view->type;
+ BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL == I915_GGTT_VIEW_ROTATED);
- return memcmp(&vma->ggtt_view.params,
- &view->params,
- sizeof(view->params));
+ return memcmp(&vma->ggtt_view.params, &view->params, view->type);
}
int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/6] drm/i915: Name the anonymous structs inside i915_ggtt_view
Naming this pair will become useful shortly...
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 6c40088f8cf4..5dd3755a5a45 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -152,20 +152,22 @@ enum i915_ggtt_view_type {
};
struct intel_rotation_info {
- struct {
+ struct intel_rotation_plane_info {
/* tiles */
unsigned int width, height, stride, offset;
} plane[2];
};
+struct intel_partial_info {
+ u64 offset;
+ unsigned int size;
+};
+
struct i915_ggtt_view {
enum i915_ggtt_view_type type;
union {
- struct {
- u64 offset;
- unsigned int size;
- } partial;
+ struct intel_partial_info partial;
struct intel_rotation_info rotated;
} params;
};
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/6] drm/i915: Convert i915_ggtt_view to use an anonymous union
Save a lot of characters by making the union anonymous, with the
side-effect of ignoring unset bits when comparing views.
v2: Roll up the memcmps back into one.
v3: And split again as Ville points out we can't trust the compiler.
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/i915_gem.c | 11 +--
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 9 -
drivers/gpu/drm/i915/i915_vma.h | 4 +++-
drivers/gpu/drm/i915/intel_display.c | 2 +-
6 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3107fff970fd..04e569d5ac40 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1762,13 +1762,12 @@ compute_partial_view(struct drm_i915_gem_object *obj,
if (i915_gem_object_is_tiled(obj))
chunk = roundup(chunk, tile_row_pages(obj));
- memset(&view, 0, sizeof(view));
view.type = I915_GGTT_VIEW_PARTIAL;
- view.params.partial.offset_size = rounddown(page_offset, chunk);
- view.params.partial.offset_size =
- (view.params.partial.offset_size << INTEL_PARTIAL_SIZE_BITS) |
+ view.partial.offset_size = rounddown(page_offset, chunk);
+ view.partial.offset_size =
+ (view.partial.offset_size << INTEL_PARTIAL_SIZE_BITS) |
(min_t(unsigned int, chunk,
- (obj->base.size >> PAGE_SHIFT) -
view.params.partial.offset_size) - 1);
+ (obj->base.size >> PAGE_SHIFT) -
view.partial.offset_size) - 1);
/* If the partial covers the entire object, just create a normal VMA. */
if (chunk >= obj->base.size >> PAGE_SHIFT)
@@ -1884,7 +1883,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct
vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
- area->vm_start +
intel_partial_get_offset(&vma->ggtt_view.params.partial),
+ area->vm_start +
intel_partial_get_offset(&vma->ggtt_view.partial),
(ggtt->mappable_base + vma->node.start) >>
PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end -
area->vm_start),
&ggtt->mappable);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c36c196546f8..73581d1b2da6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3497,13 +3497,13 @@ intel_partial_pages(const struct i915_ggtt_view *view,
if (!st)
goto err_st_alloc;
- count = intel_partial_get_page_count(&view->params.partial);
+ count = intel_partial_get_page_count(&view->partial);
ret = sg_alloc_table(st, count, GFP_KERNEL);
if (ret)
goto err_sg_alloc;
iter = i915_gem_object_get_sg(obj,
-
intel_partial_get_page_offset(&view->params.partial),
+
intel_partial_get_page_offset(&view->partial),
&offset);
GEM_BUG_ON(!iter);
@@ -3556,7 +3556,8 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
vma->pages = vma->obj->mm.pages;
else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
vma->pages =
-
intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
+ intel_rotate_fb_obj_pages(&vma->ggtt_view.rotated,
+ vma->obj);
else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
else
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 36d85599ffc9..0ddb5f6731ce 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -190,7 +190,7 @@ struct i915_ggtt_view {
/* Members need to contain no holes/padding */
struct intel_partial_info partial;
struct intel_rotation_info rotated;
- } params;
+ };
};
extern const struct i915_ggtt_view i915_ggtt_view_normal;
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 7226c5ef5410..2307e1610743 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -97,14 +97,13 @@ __i915_vma_create(struct drm_i915_gem_object *obj,
vma->ggtt_view = *view;
if (view->type == I915_GGTT_VIEW_PARTIAL) {
GEM_BUG_ON(range_overflows_t(u64,
-
intel_partial_get_offset(&view->params.partial),
-
[Intel-gfx] [PATCH 2/6] drm/i915: Pack the partial view size and offset into a single u64
Since the partial offset must be page aligned, we can use those low 12
bits to encode the size of the partial view (which then cannot be larger
than 8MiB in pages). A requirement for avoiding unused bits inside the
struct is imposed later by avoiding the clear of the struct (or of
copying around static initialisers). This is easier to guarantee by
manual packing into a single u64 - the presence of the u64 inside a
struct causes gcc to pad the struct out to a u64 boundary, even if we
use the __packed attribute.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 14 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 25 +++--
drivers/gpu/drm/i915/i915_vma.c | 9 -
4 files changed, 39 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3bf517e2430a..3107fff970fd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1696,6 +1696,9 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
static unsigned int tile_row_pages(struct drm_i915_gem_object *obj)
{
+ BUILD_BUG_ON(ilog2(GEN7_FENCE_MAX_PITCH_VAL*128*32 >> PAGE_SHIFT) >
+INTEL_PARTIAL_SIZE_BITS);
+
return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT;
}
@@ -1761,10 +1764,11 @@ compute_partial_view(struct drm_i915_gem_object *obj,
memset(&view, 0, sizeof(view));
view.type = I915_GGTT_VIEW_PARTIAL;
- view.params.partial.offset = rounddown(page_offset, chunk);
- view.params.partial.size =
- min_t(unsigned int, chunk,
- (obj->base.size >> PAGE_SHIFT) -
view.params.partial.offset);
+ view.params.partial.offset_size = rounddown(page_offset, chunk);
+ view.params.partial.offset_size =
+ (view.params.partial.offset_size << INTEL_PARTIAL_SIZE_BITS) |
+ (min_t(unsigned int, chunk,
+ (obj->base.size >> PAGE_SHIFT) -
view.params.partial.offset_size) - 1);
/* If the partial covers the entire object, just create a normal VMA. */
if (chunk >= obj->base.size >> PAGE_SHIFT)
@@ -1880,7 +1884,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct
vm_fault *vmf)
/* Finally, remap it using the new GTT offset */
ret = remap_io_mapping(area,
- area->vm_start +
(vma->ggtt_view.params.partial.offset << PAGE_SHIFT),
+ area->vm_start +
intel_partial_get_offset(&vma->ggtt_view.params.partial),
(ggtt->mappable_base + vma->node.start) >>
PAGE_SHIFT,
min_t(u64, vma->size, area->vm_end -
area->vm_start),
&ggtt->mappable);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ed120a1e7f93..c36c196546f8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3490,20 +3490,20 @@ intel_partial_pages(const struct i915_ggtt_view *view,
{
struct sg_table *st;
struct scatterlist *sg, *iter;
- unsigned int count = view->params.partial.size;
- unsigned int offset;
+ unsigned int count, offset;
int ret = -ENOMEM;
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
goto err_st_alloc;
+ count = intel_partial_get_page_count(&view->params.partial);
ret = sg_alloc_table(st, count, GFP_KERNEL);
if (ret)
goto err_sg_alloc;
iter = i915_gem_object_get_sg(obj,
- view->params.partial.offset,
+
intel_partial_get_page_offset(&view->params.partial),
&offset);
GEM_BUG_ON(!iter);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 5dd3755a5a45..3187a260e6e1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -159,10 +159,31 @@ struct intel_rotation_info {
};
struct intel_partial_info {
- u64 offset;
- unsigned int size;
+ /* offset is page-aligned, leaving just enough bits for the size */
+#define INTEL_PARTIAL_SIZE_BITS PAGE_SHIFT
+ u64 offset_size;
};
+static inline u32 intel_partial_get_page_count(const struct intel_partial_info
*pi)
+{
+ return 1 + (pi->offset_size & GENMASK(INTEL_PARTIAL_SIZE_BITS-1, 0));
+}
+
+static inline u32 intel_partial_get_size(const struct intel_partial_info *pi)
+{
+ return intel_partial_get_page_count(pi) << PAGE_SHIFT;
+}
+
+static inline u64 intel_partial_get_offset(const struct intel_partial_info *pi)
+{
+ return pi->offset_size & GENMASK(63, INTEL_PARTIAL_SIZE_BITS);
+}
+
+static inline u64 intel_partial_get_page_offset(const struct
intel_partial_info *pi)
+{
+
[Intel-gfx] [PATCH 5/6] drm/i915: Eliminate superfluous i915_ggtt_view_rotated
It is only being used to clear a struct and set the type, after which it
is overwritten. Since we no longer check the unset bits of the union,
skipping the clear is permissible.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 -
drivers/gpu/drm/i915/intel_display.c | 5 ++---
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 73581d1b2da6..70b7ab747a98 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -106,9 +106,6 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma);
const struct i915_ggtt_view i915_ggtt_view_normal = {
.type = I915_GGTT_VIEW_NORMAL,
};
-const struct i915_ggtt_view i915_ggtt_view_rotated = {
- .type = I915_GGTT_VIEW_ROTATED,
-};
static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 0ddb5f6731ce..4b91b009e14c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -194,7 +194,6 @@ struct i915_ggtt_view {
};
extern const struct i915_ggtt_view i915_ggtt_view_normal;
-extern const struct i915_ggtt_view i915_ggtt_view_rotated;
enum i915_cache_level;
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f9d4077b5c58..5c69e27fd92c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2137,11 +2137,10 @@ intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
unsigned int rotation)
{
+ view->type = I915_GGTT_VIEW_NORMAL;
if (drm_rotation_90_or_270(rotation)) {
- *view = i915_ggtt_view_rotated;
+ view->type = I915_GGTT_VIEW_ROTATED;
view->rotated = to_intel_framebuffer(fb)->rot_info;
- } else {
- *view = i915_ggtt_view_normal;
}
}
--
2.11.0
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 6/6] drm/i915: Eliminate superfluous i915_ggtt_view_normal
Since commit 058d88c4330f ("drm/i915: Track pinned VMA"), there is only
one user of i915_ggtt_view_normal rodate. Just treat NULL as no special
view in pin_to_display() like everywhere else.
Signed-off-by: Chris Wilson
Reviewed-by: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 4
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 --
drivers/gpu/drm/i915/intel_overlay.c | 3 +--
4 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 04e569d5ac40..0d9fb51aa3cc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3440,7 +3440,7 @@ i915_gem_object_pin_to_display_plane(struct
drm_i915_gem_object *obj,
* try to preserve the existing ABI).
*/
vma = ERR_PTR(-ENOSPC);
- if (view->type == I915_GGTT_VIEW_NORMAL)
+ if (!view || view->type == I915_GGTT_VIEW_NORMAL)
vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment,
PIN_MAPPABLE | PIN_NONBLOCK);
if (IS_ERR(vma)) {
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 70b7ab747a98..b2595c0cf8e9 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -103,10 +103,6 @@
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
-const struct i915_ggtt_view i915_ggtt_view_normal = {
- .type = I915_GGTT_VIEW_NORMAL,
-};
-
static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
{
/* Note that as an uncached mmio write, this should flush the
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 4b91b009e14c..7ce4e2aaa159 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -193,8 +193,6 @@ struct i915_ggtt_view {
};
};
-extern const struct i915_ggtt_view i915_ggtt_view_normal;
-
enum i915_cache_level;
struct i915_vma;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c
b/drivers/gpu/drm/i915/intel_overlay.c
index 4473a611c664..0608fad7f593 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -811,8 +811,7 @@ static int intel_overlay_do_put_image(struct intel_overlay
*overlay,
if (ret != 0)
return ret;
- vma = i915_gem_object_pin_to_display_plane(new_bo, 0,
- &i915_ggtt_view_normal);
+ vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
if (IS_ERR(vma))
return PTR_ERR(vma);
--
2.11.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Detect vma reserved for execbuf in evict-for-node
== Series Details == Series: drm/i915: Detect vma reserved for execbuf in evict-for-node URL : https://patchwork.freedesktop.org/series/17846/ State : success == Summary == Series 17846v1 drm/i915: Detect vma reserved for execbuf in evict-for-node https://patchwork.freedesktop.org/api/1.0/series/17846/revisions/1/mbox/ fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 60f8884d35facd41e1b085a19444205ec13a5da0 drm-tip: 2017y-01m-11d-20h-53m-23s UTC integration manifest 3d90981 drm/i915: Detect vma reserved for execbuf in evict-for-node == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3489/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/37] drm: Provide a driver hook for drm_dev_release()
== Series Details == Series: series starting with [01/37] drm: Provide a driver hook for drm_dev_release() URL : https://patchwork.freedesktop.org/series/17852/ State : success == Summary == Series 17852v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17852/revisions/1/mbox/ fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 60f8884d35facd41e1b085a19444205ec13a5da0 drm-tip: 2017y-01m-11d-20h-53m-23s UTC integration manifest 5ec6412 drm/i915: Mock the GEM device for self-testing 27489f4 drm/i915: Add unit tests for the breadcrumb rbtree, wakeups df115da drm/i915: Add unit tests for the breadcrumb rbtree, completion e571095 drm/i915: Add unit tests for the breadcrumb rbtree, insert/remove 0af4db2 drm/i915: Add some selftests for sg_table manipulation ab6bcab drm/i915: Provide a hook for selftests ff83217 drm: Provide a driver hook for drm_dev_release() == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3490/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] 4.10-rc2 oops in DRM connector code
On Wed, Jan 11, 2017 at 08:16:56AM -0800, Dave Hansen wrote: > On 01/11/2017 07:39 AM, Daniel Vetter wrote: > > Hm, just cherry-picked it on top of Linus' latest 4.10 git, applies > > cleanly there. The substituation was for 4.9. I can send you the patch > > here, but seems all fine from what I can tell ... > > All of the printk's that I added were making it fail to apply. > > So, I took a 4.10-rc3 kernel with i915 compiled in (not as a module) and > applied e73ab00e9a0f17, which I grabbed from linux-next. > > I'm seeing basically the same behavior that I did before applying > e73ab00e9a0f17. sysfs_create_dir_ns() fails because of a NULL kobj->parent. > > Have you guys tried testing this yourselves? It seems really easy to > reproduce if you just compile the driver in. With some screaming I can reproduce it. I'll try to take a look, but since I'm travelling to lca might need someone else to look into this too (I don't have an mst machine to carry around). And I still don't get why this blows up even. -Daniel > > > [1.400797] drm_dev_register(88040c73)::730 cpu: 2 > > [1.400860] drm_connector_register(88040c76b000)::382 > > connector->registered: 0 cpu: 1 > > [1.400870] sysfs_create_dir_ns()::53 error: -2 > > [1.400874] create_dir()::75 error: -2 cpu: 1 > > [1.400878] [ cut here ] > > [1.400884] WARNING: CPU: 1 PID: 91 at lib/kobject.c:249 > > kobject_add_internal+0x273/0x330 > > [1.400888] kobject_add_internal failed for card0-DP-3 (error: -2 > > parent: card0) > > [1.400892] Modules linked in: > > [1.400896] CPU: 1 PID: 91 Comm: kworker/1:2 Not tainted > > 4.10.0-rc3-i915borked-dirty #67 > > [1.400900] Hardware name: LENOVO 20F5S7V800/20F5S7V800, BIOS R02ET50W > > (1.23 ) 09/20/2016 > > [1.400906] Workqueue: events_long drm_dp_mst_link_probe_work > > [1.400909] Call Trace: > > [1.400914] dump_stack+0x67/0x99 > > [1.400918] __warn+0xd1/0xf0 > > [1.400922] warn_slowpath_fmt+0x4f/0x60 > > [1.400925] kobject_add_internal+0x273/0x330 > > [1.400927] kobject_add+0x65/0xb0 > > [1.400931] ? klist_init+0x31/0x40 > > [1.400936] device_add+0x102/0x5d0 > > [1.400940] ? kfree_const+0x22/0x30 > > [1.400944] device_create_groups_vargs+0xd8/0x100 > > [1.400947] device_create_with_groups+0x36/0x40 > > [1.400952] ? vprintk_default+0x29/0x50 > > [1.400957] ? __might_sleep+0x4a/0x90 > > [1.400962] drm_sysfs_connector_add+0x60/0xe0 > > [1.400967] drm_connector_register+0x74/0xd0 > > [1.400971] intel_dp_register_mst_connector+0x41/0x50 > > [1.400975] drm_dp_add_port+0x350/0x450 > > [1.400977] drm_connector_register(88040ee6f800)::382 > > connector->registered: 0 cpu: 2 > > [1.400982] ? rcu_early_boot_tests+0x1/0x10 > > [1.400986] ? schedule_timeout+0x1cd/0x390 > > [1.400989] ? __might_sleep+0x4a/0x90 > > [1.400992] ? mutex_lock+0x25/0x50 > > [1.400995] ? drm_dp_mst_wait_tx_reply+0x118/0x1e0 > > [1.400996] drm_sysfs_connector_add() connector: 88040ee6f800 kdev: > > 88040eef9c00 > > [1.401002] ? prepare_to_wait_event+0x120/0x120 > > [1.401005] ? drm_dp_check_mstb_guid+0x3d/0x120 > > [1.401008] drm_dp_send_link_address+0x185/0x1f0 > > [1.401012] drm_dp_check_and_send_link_address+0xad/0xc0 > > [1.401015] drm_dp_mst_link_probe_work+0x57/0xa0 > > [1.401018] process_one_work+0x14b/0x430 > > [1.401021] worker_thread+0x12b/0x4a0 > > [1.401025] kthread+0x10c/0x140 > > [1.401027] ? process_one_work+0x430/0x430 > > [1.401030] ? kthread_create_on_node+0x40/0x40 > > [1.401034] ret_from_fork+0x27/0x40 > > [1.401038] ---[ end trace ba43fc250fbf282d ]--- > > [1.401041] drm_sysfs_connector_add() connector: 88040c76b000 kdev: > > fffe > > [1.401043] drm_connector_register(88040c768000)::382 > > connector->registered: 0 cpu: 2 > > [1.401050] [drm:drm_sysfs_connector_add] *ERROR* failed to register > > connector device: -2 > > [1.401057] drm_sysfs_connector_add() connector: 88040c768000 kdev: > > 88040eefa000 > > [1.401093] drm_connector_register(88040c768800)::382 > > connector->registered: 0 cpu: 2 > > [1.401113] drm_sysfs_connector_add() connector: 88040c768800 kdev: > > 88040eefa400 > > [1.401122] drm_connector_register(88040c769000)::382 > > connector->registered: 0 cpu: 2 > > [1.401140] drm_sysfs_connector_add() connector: 88040c769000 kdev: > > 88040eefa800 > > [1.401167] drm_connector_register(88040c769800)::382 > > connector->registered: 0 cpu: 2 > > [1.401186] drm_sysfs_connector_add() connector: 88040c769800 kdev: > > 88040eefac00 > > [1.401195] drm_connector_register(88040c76b000)::382 > > connector->registered: 0 cpu: 2 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _
Re: [Intel-gfx] [PATCH] drm/i915/guc: Make sure vma containing firmware is GuC mappable
On 11/01/17 07:17, Michał Winiarski wrote:
Since commit 4741da925fa3 ("drm/i915/guc: Assert that all GGTT offsets used
by the GuC are mappable"), we're asserting that GuC firmware is in the
GuC mappable range.
Except we're not pinning the object with bias, which means it's possible
to trigger this assert. Let's add a proper bias.
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index aa2b866..5a6ab87 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -360,7 +360,8 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
return ret;
}
- vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0, 0);
+ vma = i915_gem_object_ggtt_pin(guc_fw->guc_fw_obj, NULL, 0, 0,
+ PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
if (IS_ERR(vma)) {
DRM_DEBUG_DRIVER("pin failed %d\n", (int)PTR_ERR(vma));
return PTR_ERR(vma);
This patch made me think about this again and actually I'm not sure
anymore that there is an offset requirement for the firmware object.
With the way we load the firmware the GuC should never access it in GGTT
because it is first copied in WOPCM via DMA, which should be able to
access the whole address range. I've asked a GuC dev but he has not been
able to confirm if there are any offset limitation with the DMA transfer
or not and unfortunately I don't have a platform to test this on at the
moment. I'll try to get my hands on a new SKL and double check.
Anyway, I'm happy to merge this while we clarify the requirement because
the firmware vma is immediately unpinned after the transfer so there
should be no risk of unneeded ggtt fragmentation; it also looks
generally cleaner to me to handle all guc-related objects the same way.
Thanks,
Daniele
___
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[Intel-gfx] [PATCH 08/10] drm/i915/psr: enable psr2 for y cordinate panels
Psr2 is enabled only for y cordinate panels.Once GTC (global time code)
is implemented,this restriction is removed so that psr2
can work on panels without y cordinate support.
v2: (Rodrigo)
- Move the check to intel_psr_match_conditions
v3: (Rodrigo)
- add return false
v4: rebase
Cc: Rodrigo Vivi
Cc: Jim Bride
Signed-off-by: Vathsala Nagaraju
Signed-off-by: Patil Deepti
Reviewed-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_psr.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index f9d620b..2c14f46 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -441,6 +441,15 @@ static bool intel_psr_match_conditions(struct intel_dp
*intel_dp)
return false;
}
+ /*
+* FIXME:enable psr2 only for y-cordinate psr2 panels
+* After gtc implementation , remove this restriction.
+*/
+ if (!dev_priv->psr.y_cord_support && dev_priv->psr.psr2_support) {
+ DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y
coordinate\n");
+ return false;
+ }
+
dev_priv->psr.source_ok = true;
return true;
}
--
1.9.1
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Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Add render decompression support
On Wed, Jan 11, 2017 at 1:49 PM, Jason Ekstrand
wrote:
> On Tue, Jan 10, 2017 at 9:04 AM, Ville Syrjälä <
> ville.syrj...@linux.intel.com> wrote:
>
>> On Mon, Jan 09, 2017 at 11:20:57AM -0800, Jason Ekstrand wrote:
>> > On Thu, Jan 5, 2017 at 7:14 AM, wrote:
>> >
>> > > From: Ville Syrjälä
>> > >
>> > > SKL+ display engine can scan out certain kinds of compressed surfaces
>> > > produced by the render engine. This involved telling the display
>> engine
>> > > the location of the color control surfae (CCS) which describes
>> > > which parts of the main surface are compressed and which are not. The
>> > > location of CCS is provided by userspace as just another plane with
>> its
>> > > own offset.
>> > >
>> > > Add the required stuff to validate the user provided AUX plane
>> metadata
>> > > and convert the user provided linear offset into something the
>> hardware
>> > > can consume.
>> > >
>> > > Due to hardware limitations we require that the main surface and
>> > > the AUX surface (CCS) be part of the same bo. The hardware also
>> > > makes life hard by not allowing you to provide separate x/y offsets
>> > > for the main and AUX surfaces (excpet with NV12), so finding suitable
>> > > offsets for both requires a bit of work. Assuming we still want keep
>> > > playing tricks with the offsets. I've just gone with a dumb "search
>> > > backward for suitable offsets" approach, which is far from optimal,
>> > > but it works.
>> > >
>> > > Also not all planes will be capable of scanning out compressed
>> surfaces,
>> > > and eg. 90/270 degree rotation is not supported in combination with
>> > > decompression either.
>> > >
>> > > This patch may contain work from at least the following people:
>> > > * Vandana Kannan
>> > > * Daniel Vetter
>> > > * Ben Widawsky
>> > >
>> > > v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
>> > >
>> > > Cc: Paulo Zanoni
>> > > Cc: Vandana Kannan
>> > > Cc: Daniel Vetter
>> > > Cc: Ben Widawsky
>> > > Cc: Jason Ekstrand
>> > > Signed-off-by: Ville Syrjälä
>> > > ---
>> > > drivers/gpu/drm/i915/i915_reg.h | 23
>> > > drivers/gpu/drm/i915/intel_display.c | 234
>> ++
>> > > ++---
>> > > drivers/gpu/drm/i915/intel_pm.c | 29 -
>> > > drivers/gpu/drm/i915/intel_sprite.c | 5 +
>> > > 4 files changed, 274 insertions(+), 17 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_
>> > > reg.h
>> > > index 00970aa77afa..6849ba93f1d9 100644
>> > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > @@ -6209,6 +6209,28 @@ enum {
>> > > _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
>> > > _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
>> > >
>> > > +#define PLANE_AUX_DIST_1_A 0x701c0
>> > > +#define PLANE_AUX_DIST_2_A 0x702c0
>> > > +#define PLANE_AUX_DIST_1_B 0x711c0
>> > > +#define PLANE_AUX_DIST_2_B 0x712c0
>> > > +#define _PLANE_AUX_DIST_1(pipe) \
>> > > + _PIPE(pipe, PLANE_AUX_DIST_1_A,
>> PLANE_AUX_DIST_1_B)
>> > > +#define _PLANE_AUX_DIST_2(pipe) \
>> > > + _PIPE(pipe, PLANE_AUX_DIST_2_A,
>> PLANE_AUX_DIST_2_B)
>> > > +#define PLANE_AUX_DIST(pipe, plane) \
>> > > + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe),
>> > > _PLANE_AUX_DIST_2(pipe))
>> > > +
>> > > +#define PLANE_AUX_OFFSET_1_A 0x701c4
>> > > +#define PLANE_AUX_OFFSET_2_A 0x702c4
>> > > +#define PLANE_AUX_OFFSET_1_B 0x711c4
>> > > +#define PLANE_AUX_OFFSET_2_B 0x712c4
>> > > +#define _PLANE_AUX_OFFSET_1(pipe) \
>> > > + _PIPE(pipe, PLANE_AUX_OFFSET_1_A,
>> PLANE_AUX_OFFSET_1_B)
>> > > +#define _PLANE_AUX_OFFSET_2(pipe) \
>> > > + _PIPE(pipe, PLANE_AUX_OFFSET_2_A,
>> PLANE_AUX_OFFSET_2_B)
>> > > +#define PLANE_AUX_OFFSET(pipe, plane) \
>> > > + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe),
>> > > _PLANE_AUX_OFFSET_2(pipe))
>> > > +
>> > > /* legacy palette */
>> > > #define _LGC_PALETTE_A 0x4a000
>> > > #define _LGC_PALETTE_B 0x4a800
>> > > @@ -6433,6 +6455,7 @@ enum {
>> > > # define CHICKEN3_DGMG_DONE_FIX_DISABLE(1 << 2)
>> > >
>> > > #define CHICKEN_PAR1_1 _MMIO(0x42080)
>> > > +#define SKL_RC_HASH_OUTSIDE (1 << 15)
>> > > #define DPA_MASK_VBLANK_SRD (1 << 15)
>> > > #define FORCE_ARB_IDLE_PLANES (1 << 14)
>> > > #define SKL_EDP_PSR_FIX_RDWRAP(1 << 3)
>> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
>> > > b/drivers/gpu/drm/i915/intel_display.c
>> > > index 38de9df0ec60..2236abebd8bc 100644
>> > > --- a/drivers/gpu/drm/i915/intel_display.c
>> > > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > > @@ -2064,11 +2064,19 @@ intel_tile_width_bytes(const struct
>> > > drm_framebuffer *fb, int plane)
>> > > return 128;
>> > > el
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev3)
== Series Details == Series: series starting with [1/3] drm/i915: Invalidate the guc ggtt TLB upon insertion (rev3) URL : https://patchwork.freedesktop.org/series/17829/ State : failure == Summary == Series 17829v3 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17829/revisions/3/mbox/ Test drv_module_reload: Subgroup basic-reload-final: dmesg-warn -> TIMEOUT(fi-skl-6700k) Test gem_basic: Subgroup bad-close: pass -> INCOMPLETE (fi-skl-6700k) Test gem_exec_suspend: Subgroup basic-s3: pass -> INCOMPLETE (fi-bxt-j4205) pass -> INCOMPLETE (fi-skl-6770hq) pass -> INCOMPLETE (fi-skl-6260u) Test gem_sync: Subgroup basic-store-all: pass -> TIMEOUT(fi-skl-6700hq) Subgroup basic-store-each: pass -> INCOMPLETE (fi-skl-6700hq) fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:82 pass:70 dwarn:0 dfail:0 fail:0 skip:11 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:82 pass:78 dwarn:0 dfail:0 fail:0 skip:3 fi-skl-6700hqtotal:124 pass:111 dwarn:0 dfail:0 fail:0 skip:11 fi-skl-6700k total:9pass:5dwarn:2 dfail:0 fail:0 skip:0 fi-skl-6770hqtotal:82 pass:78 dwarn:0 dfail:0 fail:0 skip:3 fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 60f8884d35facd41e1b085a19444205ec13a5da0 drm-tip: 2017y-01m-11d-20h-53m-23s UTC integration manifest 2a9691c HAX enable guc submission for CI 3f30f6a drm/i915/scheduler: emulate a scheduler for guc eb859d2 drm/i915: Invalidate the guc ggtt TLB upon insertion == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3491/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Name the anonymous structs inside i915_ggtt_view
== Series Details == Series: series starting with [1/6] drm/i915: Name the anonymous structs inside i915_ggtt_view URL : https://patchwork.freedesktop.org/series/17858/ State : success == Summary == Series 17858v1 Series without cover letter https://patchwork.freedesktop.org/api/1.0/series/17858/revisions/1/mbox/ fi-bdw-5557u total:246 pass:232 dwarn:0 dfail:0 fail:0 skip:14 fi-bsw-n3050 total:246 pass:207 dwarn:0 dfail:0 fail:0 skip:39 fi-bxt-j4205 total:246 pass:224 dwarn:0 dfail:0 fail:0 skip:22 fi-bxt-t5700 total:82 pass:69 dwarn:0 dfail:0 fail:0 skip:12 fi-byt-j1900 total:246 pass:219 dwarn:0 dfail:0 fail:0 skip:27 fi-byt-n2820 total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-hsw-4770 total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-hsw-4770r total:246 pass:227 dwarn:0 dfail:0 fail:0 skip:19 fi-ivb-3520m total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-ivb-3770 total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-kbl-7500u total:246 pass:225 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6260u total:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-skl-6700hqtotal:246 pass:226 dwarn:0 dfail:0 fail:0 skip:20 fi-skl-6700k total:246 pass:222 dwarn:3 dfail:0 fail:0 skip:21 fi-skl-6770hqtotal:246 pass:233 dwarn:0 dfail:0 fail:0 skip:13 fi-snb-2520m total:246 pass:215 dwarn:0 dfail:0 fail:0 skip:31 fi-snb-2600 total:246 pass:214 dwarn:0 dfail:0 fail:0 skip:32 60f8884d35facd41e1b085a19444205ec13a5da0 drm-tip: 2017y-01m-11d-20h-53m-23s UTC integration manifest 4e8ec77 drm/i915: Convert i915_ggtt_view to use an anonymous union 2470d28 drm/i915: Compact memcmp in i915_vma_compare() 623177a drm/i915: Pack the partial view size and offset into a single u64 c82de988 drm/i915: Name the anonymous structs inside i915_ggtt_view == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3492/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCHv2] drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.
Daniel Vetter writes:
> On Mon, Jan 09, 2017 at 01:07:56PM -0800, Francisco Jerez wrote:
>> The WaDisableLSQCROPERFforOCL workaround has the side effect of
>> disabling an L3SQ optimization that has huge performance implications
>> and is unlikely to be necessary for the correct functioning of usual
>> graphic workloads. Userspace is free to re-enable the workaround on
>> demand, and is generally in a better position to determine whether the
>> workaround is necessary than the DRM is (e.g. only during the
>> execution of compute kernels that rely on both L3 fences and HDC R/W
>> requests).
>>
>> The same workaround seems to apply to BDW (at least to production
>> stepping G1) and SKL as well (the internal workaround database claims
>> that it does for all steppings, while the BSpec workaround table only
>> mentions pre-production steppings), but the DRM doesn't do anything
>> beyond whitelisting the L3SQCREG4 register so userspace can enable it
>> when it sees fit. Do the same on KBL platforms.
>>
>> Improves performance of the GFXBench4 gl_manhattan31 benchmark by 60%,
>> and gl_4 (AKA car chase) by 14% on a KBL GT2 running Mesa master --
>> This is followed by a regression of 35% and 10% respectively for the
>> same benchmarks and platform caused by my recent patch series
>> switching userspace to use the dataport constant cache instead of the
>> sampler to implement uniform pull constant loads, which caused us to
>> hit more heavily the L3 cache (and on platforms other than KBL had the
>> opposite effect of improving performance of the same two benchmarks).
>> The overall effect on KBL of this change combined with the recent
>> userspace change is respectively 4.6% and 2.6%. SynMark2 OglShMapPcf
>> was affected by the constant cache changes (though it improved as it
>> did on other platforms rather than regressing), but is not
>> significantly affected by this patch (with statistical significance of
>> 5% and sample size 20).
>>
>> v2: Drop some more code to avoid unused variable warning.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99256
>> Signed-off-by: Francisco Jerez
>> Cc: Eero Tamminen
>> Cc: Jani Nikula
>> Cc: Mika Kuoppala
>> Cc: beig...@lists.freedesktop.org
>
> Don't we need some userspace flag/opt-in scheme to avoid stuff going boom
> for compute kernels? Are the patches for mesa compute/beignet
> ready&reviewed?
I don't think upstream userspace (neither Beignet nor Mesa) relies on
the workaround at this point, though Beignet devs may want to keep this
hardware bug in mind when they start doing SVM.
> -Daniel
>
>> ---
>> drivers/gpu/drm/i915/intel_lrc.c| 10 --
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 8
>> 2 files changed, 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c
>> b/drivers/gpu/drm/i915/intel_lrc.c
>> index 6db246a..656e0a3 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -970,18 +970,8 @@ static inline int gen8_emit_flush_coherentl3_wa(struct
>> intel_engine_cs *engine,
>> uint32_t *batch,
>> uint32_t index)
>> {
>> -struct drm_i915_private *dev_priv = engine->i915;
>> uint32_t l3sqc4_flush = (0x4040 | GEN8_LQSC_FLUSH_COHERENT_LINES);
>>
>> -/*
>> - * WaDisableLSQCROPERFforOCL:kbl
>> - * This WA is implemented in skl_init_clock_gating() but since
>> - * this batch updates GEN8_L3SQCREG4 with default value we need to
>> - * set this bit here to retain the WA during flush.
>> - */
>> -if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
>> -l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
>> -
>> wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
>> MI_SRM_LRM_GLOBAL_GTT));
>> wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 0971ac3..7cb2ab4 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -1095,14 +1095,6 @@ static int kbl_init_workarounds(struct
>> intel_engine_cs *engine)
>> WA_SET_BIT_MASKED(HDC_CHICKEN0,
>>HDC_FENCE_DEST_SLM_DISABLE);
>>
>> -/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
>> - * involving this register should also be added to WA batch as required.
>> - */
>> -if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
>> -/* WaDisableLSQCROPERFforOCL:kbl */
>> -I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
>> - GEN8_LQSC_RO_PERF_DIS);
>> -
>> /* WaToEnableHwFixForPushConstHWBug:kbl */
>> if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
>> WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>> --
>> 2.10.2
>>
>> _
Re: [Intel-gfx] [PATCHv2] drm/i915: Remove WaDisableLSQCROPERFforOCL KBL workaround.
Daniel Vetter writes: > On Wed, Jan 11, 2017 at 12:24:59PM +, Chris Wilson wrote: >> On Wed, Jan 11, 2017 at 02:07:37PM +0200, Mika Kuoppala wrote: >> > Daniel Vetter writes: >> > >> > > On Mon, Jan 09, 2017 at 01:07:56PM -0800, Francisco Jerez wrote: >> > >> The WaDisableLSQCROPERFforOCL workaround has the side effect of >> > >> disabling an L3SQ optimization that has huge performance implications >> > >> and is unlikely to be necessary for the correct functioning of usual >> > >> graphic workloads. Userspace is free to re-enable the workaround on >> > >> demand, and is generally in a better position to determine whether the >> > >> workaround is necessary than the DRM is (e.g. only during the >> > >> execution of compute kernels that rely on both L3 fences and HDC R/W >> > >> requests). >> > >> >> > >> The same workaround seems to apply to BDW (at least to production >> > >> stepping G1) and SKL as well (the internal workaround database claims >> > >> that it does for all steppings, while the BSpec workaround table only >> > >> mentions pre-production steppings), but the DRM doesn't do anything >> > >> beyond whitelisting the L3SQCREG4 register so userspace can enable it >> > >> when it sees fit. Do the same on KBL platforms. >> > >> >> > >> Improves performance of the GFXBench4 gl_manhattan31 benchmark by 60%, >> > >> and gl_4 (AKA car chase) by 14% on a KBL GT2 running Mesa master -- >> > >> This is followed by a regression of 35% and 10% respectively for the >> > >> same benchmarks and platform caused by my recent patch series >> > >> switching userspace to use the dataport constant cache instead of the >> > >> sampler to implement uniform pull constant loads, which caused us to >> > >> hit more heavily the L3 cache (and on platforms other than KBL had the >> > >> opposite effect of improving performance of the same two benchmarks). >> > >> The overall effect on KBL of this change combined with the recent >> > >> userspace change is respectively 4.6% and 2.6%. SynMark2 OglShMapPcf >> > >> was affected by the constant cache changes (though it improved as it >> > >> did on other platforms rather than regressing), but is not >> > >> significantly affected by this patch (with statistical significance of >> > >> 5% and sample size 20). >> > >> >> > >> v2: Drop some more code to avoid unused variable warning. >> > >> >> > >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99256 >> > >> Signed-off-by: Francisco Jerez >> > >> Cc: Eero Tamminen >> > >> Cc: Jani Nikula >> > >> Cc: Mika Kuoppala >> > >> Cc: beig...@lists.freedesktop.org >> > > >> > > Don't we need some userspace flag/opt-in scheme to avoid stuff going boom >> > > for compute kernels? Are the patches for mesa compute/beignet >> > > ready&reviewed? >> > >> > This is explicit setting on kbl/E0 only. So one could argue >> > that unless they filter based on PCI-IDs, things would already >> > blow up across the skl/kbl population, if they forgot >> > to set it. The whitelisting is in place and looks sane >> > so this E0 exception is a wart that got in by me reading wa >> > database slavishly without thinking. >> >> Add Fixes then? > > Yeah, cc: stable would be good to make sure it shows up in all supported > kernels, fast. Otherwise we'll get some good wtf bug reports. Agreed -- It would be nice for this to get to stable kernel branches. > -Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/3] drm/i915: Add format modifiers for Intel
This was based on a patch originally by Kristian. It has been modified
pretty heavily to use the new callbacks from the previous patch.
Cc: Kristian H. Kristensen
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 109 ++-
drivers/gpu/drm/i915/intel_sprite.c | 33 ++-
2 files changed, 137 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8715b1083d1d..26f3a911b999 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -61,6 +61,11 @@ static const uint32_t i8xx_primary_formats[] = {
DRM_FORMAT_XRGB,
};
+static const uint64_t i8xx_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_INVALID
+};
+
/* Primary plane formats for gen >= 4 */
static const uint32_t i965_primary_formats[] = {
DRM_FORMAT_C8,
@@ -71,6 +76,11 @@ static const uint32_t i965_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
};
+static const uint64_t i965_format_modifiers[] = {
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_INVALID
+};
+
static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -86,6 +96,12 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_VYUY,
};
+static const uint64_t skl_format_modifiers[] = {
+ I915_FORMAT_MOD_Y_TILED,
+ I915_FORMAT_MOD_X_TILED,
+ DRM_FORMAT_MOD_INVALID
+};
+
/* Cursor formats */
static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -15173,6 +15189,87 @@ void intel_plane_destroy(struct drm_plane *plane)
kfree(to_intel_plane(plane));
}
+static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
+{
+ if (modifier == DRM_FORMAT_MOD_NONE)
+ return true;
+
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_XRGB:
+ return modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool i965_mod_supported(uint32_t format, uint64_t modifier)
+{
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ return modifier == I915_FORMAT_MOD_X_TILED;
+ default:
+ return false;
+ }
+}
+
+static bool skl_mod_supported(uint32_t format, uint64_t modifier)
+{
+ switch (format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ARGB:
+ case DRM_FORMAT_ABGR:
+ return modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_X_TILED;
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_XBGR2101010:
+ return modifier == I915_FORMAT_MOD_X_TILED;
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_VYUY:
+ default:
+ return false;
+ }
+
+}
+
+static bool intel_plane_format_mod_supported(struct drm_plane *plane,
+uint32_t format,
+uint64_t modifier)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->dev);
+
+ if (modifier == DRM_FORMAT_MOD_NONE)
+ return true;
+
+ if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
+ return false;
+
+ if (WARN_ON(plane->type != DRM_PLANE_TYPE_PRIMARY &&
+ plane->type != DRM_PLANE_TYPE_OVERLAY))
+ return false;
+
+ if (INTEL_GEN(dev_priv) >= 9)
+ return skl_mod_supported(format, modifier);
+ else if (INTEL_GEN(dev_priv) >= 4)
+ return i965_mod_supported(format, modifier);
+ else
+ return i8xx_mod_supported(format, modifier);
+
+ return false;
+}
+
const struct drm_plane_funcs intel_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -15182,6 +15279,7 @@ const struct drm_plane_funcs intel_plane_funcs = {
.atomic_set_property = intel_plane_atomic_set_property,
.atomic_duplicate_state = intel_plane_duplicate_state,
.atomic_destroy_state = intel_plane_destroy_state,
+ .format_mod_supported = intel_plane_format_mod_supported,
};
static int
@@ -15324,6 +15422,7 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
const uint32_t *intel_primary_formats;
unsigned int supported_rotations;
unsigned int num_formats;
+ const uint64_t *intel_format_modifiers;
int r
[Intel-gfx] [PATCH 3/3] drm/i915: Add support for GET_PLANE2 CCS modifiers
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/intel_display.c | 10 --
drivers/gpu/drm/i915/intel_sprite.c | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 26f3a911b999..cf1b19447af1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -97,6 +97,8 @@ static const uint32_t skl_primary_formats[] = {
};
static const uint64_t skl_format_modifiers[] = {
+ I915_FORMAT_MOD_Yf_TILED_CCS,
+ I915_FORMAT_MOD_Y_TILED_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_INVALID
@@ -15225,15 +15227,19 @@ static bool skl_mod_supported(uint32_t format,
uint64_t modifier)
switch (format) {
case DRM_FORMAT_C8:
case DRM_FORMAT_RGB565:
+ return modifier == I915_FORMAT_MOD_Y_TILED ||
+ modifier == I915_FORMAT_MOD_X_TILED;
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
case DRM_FORMAT_ARGB:
case DRM_FORMAT_ABGR:
- return modifier == I915_FORMAT_MOD_Y_TILED ||
+ return modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ modifier == I915_FORMAT_MOD_Y_TILED ||
modifier == I915_FORMAT_MOD_X_TILED;
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
- return modifier == I915_FORMAT_MOD_X_TILED;
+ return modifier == I915_FORMAT_MOD_X_TILED;
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 152ec8196d41..eed7195212b7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1045,6 +1045,8 @@ static uint32_t skl_plane_formats[] = {
};
static const uint64_t skl_plane_format_modifiers[] = {
+ I915_FORMAT_MOD_Yf_TILED_CCS,
+ I915_FORMAT_MOD_Y_TILED_CCS,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_X_TILED,
DRM_FORMAT_MOD_INVALID
--
2.11.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2
Originally based off of a patch by Kristian.
This new ioctl extends DRM_IOCTL_MODE_GETPLANE, by returning information
about the modifiers that will work with each format.
It's modified from Kristian's patch in that the modifiers and formats
are setup by the driver, and then a callback is used to create the
format list. The LOC was enough difference that I don't think it made
sense to leave his authorship, but the new UABI was primarily his idea.
Additionally, I hit a couple of drivers which Kristian missed updating.
It also contains a change requested by Daniel to make the modifiers
array a sentinel based structure instead of a sized one. Upon discussion
on IRC, it was determined that having an invalid modifier might make
sense in general as well.
References: https://patchwork.kernel.org/patch/9482393/
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
drivers/gpu/drm/arm/malidp_planes.c | 2 +-
drivers/gpu/drm/armada/armada_crtc.c| 1 +
drivers/gpu/drm/armada/armada_overlay.c | 1 +
drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 4 +-
drivers/gpu/drm/drm_ioctl.c | 2 +-
drivers/gpu/drm/drm_modeset_helper.c| 1 +
drivers/gpu/drm/drm_plane.c | 67 -
drivers/gpu/drm/drm_simple_kms_helper.c | 3 ++
drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 +-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 2 +-
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 1 +
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 2 +-
drivers/gpu/drm/i915/intel_display.c| 7 ++-
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
drivers/gpu/drm/imx/ipuv3-plane.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_plane.c| 2 +-
drivers/gpu/drm/meson/meson_plane.c | 1 +
drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 2 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 2 +-
drivers/gpu/drm/mxsfb/mxsfb_drv.c | 2 +-
drivers/gpu/drm/nouveau/nv50_display.c | 5 +-
drivers/gpu/drm/omapdrm/omap_plane.c| 3 +-
drivers/gpu/drm/rcar-du/rcar_du_plane.c | 4 +-
drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 +-
drivers/gpu/drm/sti/sti_cursor.c| 1 +
drivers/gpu/drm/sti/sti_gdp.c | 2 +-
drivers/gpu/drm/sti/sti_hqvdp.c | 2 +-
drivers/gpu/drm/sun4i/sun4i_layer.c | 1 +
drivers/gpu/drm/tegra/dc.c | 12 ++---
drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
drivers/gpu/drm/virtio/virtgpu_plane.c | 2 +-
drivers/gpu/drm/zte/zx_plane.c | 2 +-
include/drm/drm_plane.h | 21 +++-
include/drm/drm_simple_kms_helper.h | 1 +
include/uapi/drm/drm.h | 1 +
include/uapi/drm/drm_fourcc.h | 11
include/uapi/drm/drm_mode.h | 27 ++
40 files changed, 182 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
b/drivers/gpu/drm/arc/arcpgu_crtc.c
index ad9a95916f1f..cd8a24c7c67d 100644
--- a/drivers/gpu/drm/arc/arcpgu_crtc.c
+++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
@@ -218,6 +218,7 @@ static struct drm_plane *arc_pgu_plane_init(struct
drm_device *drm)
ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
formats, ARRAY_SIZE(formats),
+ NULL,
DRM_PLANE_TYPE_PRIMARY, NULL);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
index 20ebfb4fbdfa..89fded880807 100644
--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
@@ -283,6 +283,7 @@ static struct drm_plane *hdlcd_plane_init(struct drm_device
*drm)
ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
formats, ARRAY_SIZE(formats),
+ NULL,
DRM_PLANE_TYPE_PRIMARY, NULL);
if (ret) {
devm_kfree(drm->dev, plane);
diff --git a/drivers/gpu/drm/arm/malidp_planes.c
b/drivers/gpu/drm/arm/malidp_planes.c
index eff2fe47e26a..94dbcbc9ad8f 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -283,7 +283,7 @@ int malidp_de_planes_init(struct drm_device *drm)
DRM_PLANE_TYPE_OVERLAY;
ret = drm_universal_plane_init(drm, &plane->base, crtcs,
&malidp_de_plane_funcs, formats,
- n, plane_
[Intel-gfx] [PATCH 0/3] GET_PLANE2 w/ i915 implementation
This patch series implements GET_PLANE2 support for Intel platforms and defines the new kernel UAPI. The idea was originally introduced by Kristian. Ultimately, the purpose of the new API is to provide the ability to query per-plane modifiers in KMS. These modifiers, which are just fb modifiers, will be used by the client to enable optimal modifications for framebuffers. A reference implementation in kmscube is referenced (in that code is a comment for an optimal algorithm not implemented). This work has been discussed on the mailing list and IRC over the last few weeks and this is a result of the agreed changes. There is still some debate about the UAPI, I believe, but I can firmly say that this seems entirely sufficient for Intel platforms in the foreseeable future. Cc: Kristian Høgsberg Cc: Rob Clark Cc: Ville Syrjälä Cc: Daniel Vetter References: (ccs modifier) https://lists.freedesktop.org/archives/intel-gfx/2017-January/116022.html References: (GBM modifiers) https://lists.freedesktop.org/archives/mesa-dev/2017-January/139284.html References: (kmscube) https://github.com/bwidawsk/kmscube/commit/55519640f5a1a21983e267fb39e4cf48f6312ef9 References: (libdrm) https://lists.freedesktop.org/archives/dri-devel/2016-December/127942.html Ben Widawsky (3): drm: Add new DRM_IOCTL_MODE_GETPLANE2 drm/i915: Add format modifiers for Intel drm/i915: Add support for GET_PLANE2 CCS modifiers drivers/gpu/drm/arc/arcpgu_crtc.c | 1 + drivers/gpu/drm/arm/hdlcd_crtc.c| 1 + drivers/gpu/drm/arm/malidp_planes.c | 2 +- drivers/gpu/drm/armada/armada_crtc.c| 1 + drivers/gpu/drm/armada/armada_overlay.c | 1 + drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 4 +- drivers/gpu/drm/drm_ioctl.c | 2 +- drivers/gpu/drm/drm_modeset_helper.c| 1 + drivers/gpu/drm/drm_plane.c | 67 +- drivers/gpu/drm/drm_simple_kms_helper.c | 3 + drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 +- drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 2 +- drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 1 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 2 +- drivers/gpu/drm/i915/intel_display.c| 116 +++- drivers/gpu/drm/i915/intel_sprite.c | 31 +++ drivers/gpu/drm/imx/ipuv3-plane.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_plane.c| 2 +- drivers/gpu/drm/meson/meson_plane.c | 1 + drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 2 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 2 +- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 2 +- drivers/gpu/drm/nouveau/nv50_display.c | 5 +- drivers/gpu/drm/omapdrm/omap_plane.c| 3 +- drivers/gpu/drm/rcar-du/rcar_du_plane.c | 4 +- drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 5 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 +- drivers/gpu/drm/sti/sti_cursor.c| 1 + drivers/gpu/drm/sti/sti_gdp.c | 2 +- drivers/gpu/drm/sti/sti_hqvdp.c | 2 +- drivers/gpu/drm/sun4i/sun4i_layer.c | 1 + drivers/gpu/drm/tegra/dc.c | 12 +-- drivers/gpu/drm/vc4/vc4_plane.c | 2 +- drivers/gpu/drm/virtio/virtgpu_plane.c | 2 +- drivers/gpu/drm/zte/zx_plane.c | 2 +- include/drm/drm_plane.h | 21 - include/drm/drm_simple_kms_helper.h | 1 + include/uapi/drm/drm.h | 1 + include/uapi/drm/drm_fourcc.h | 11 +++ include/uapi/drm/drm_mode.h | 27 ++ 40 files changed, 320 insertions(+), 36 deletions(-) -- 2.11.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for GET_PLANE2 w/ i915 implementation
== Series Details == Series: GET_PLANE2 w/ i915 implementation URL : https://patchwork.freedesktop.org/series/17873/ State : failure == Summary == LD [M] sound/pci/hda/snd-hda-codec-generic.o LD lib/built-in.o LD sound/pci/built-in.o LD drivers/acpi/built-in.o LD drivers/md/dm-mod.o LD sound/built-in.o LD drivers/scsi/scsi_mod.o LD drivers/video/fbdev/core/fb.o LD net/ipv6/ipv6.o LD drivers/video/fbdev/core/built-in.o LD drivers/pci/built-in.o LD drivers/usb/storage/usb-storage.o LD drivers/usb/storage/built-in.o drivers/gpu/drm/i915/intel_sprite.c:1043:2: error: ‘I915_FORMAT_MOD_Yf_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Yf_TILED_CCS, ^ drivers/gpu/drm/i915/intel_sprite.c:1044:2: error: ‘I915_FORMAT_MOD_Y_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Y_TILED_CCS, ^ LD net/ipv6/built-in.o scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/intel_sprite.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_sprite.o] Error 1 make[4]: *** Waiting for unfinished jobs LD [M] drivers/usb/serial/usbserial.o LD [M] drivers/misc/mei/mei-me.o LD drivers/misc/built-in.o LD drivers/thermal/thermal_sys.o LD drivers/thermal/built-in.o LD [M] drivers/gpu/drm/vgem/vgem.o LD drivers/tty/serial/8250/8250.o LD [M] drivers/mmc/core/mmc_block.o drivers/gpu/drm/i915/intel_display.c:100:2: error: ‘I915_FORMAT_MOD_Yf_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Yf_TILED_CCS, ^ drivers/gpu/drm/i915/intel_display.c:101:2: error: ‘I915_FORMAT_MOD_Y_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Y_TILED_CCS, ^ LD [M] drivers/net/ethernet/broadcom/genet/genet.o LD drivers/mmc/built-in.o LD drivers/usb/gadget/libcomposite.o LD drivers/video/fbdev/built-in.o LD drivers/spi/built-in.o drivers/gpu/drm/i915/intel_display.c: In function ‘skl_mod_supported’: drivers/gpu/drm/i915/intel_display.c:15053:20: error: comparison between pointer and integer [-Werror] return modifier == I915_FORMAT_MOD_Yf_TILED_CCS || ^ drivers/gpu/drm/i915/intel_display.c:15054:13: error: comparison between pointer and integer [-Werror] modifier == I915_FORMAT_MOD_Y_TILED_CCS || ^ LD drivers/scsi/sd_mod.o LD drivers/scsi/built-in.o LD net/ipv4/built-in.o LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o LD drivers/usb/gadget/udc/udc-core.o LD drivers/usb/gadget/udc/built-in.o cc1: all warnings being treated as errors scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/intel_display.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1 LD drivers/usb/gadget/built-in.o LD drivers/video/console/built-in.o LD drivers/video/built-in.o LD drivers/iommu/built-in.o LD drivers/tty/serial/8250/8250_base.o LD drivers/tty/serial/8250/built-in.o LD drivers/tty/serial/built-in.o LD fs/btrfs/btrfs.o LD fs/btrfs/built-in.o LD [M] drivers/net/ethernet/intel/e1000/e1000.o LD drivers/usb/core/usbcore.o CC arch/x86/kernel/cpu/capflags.o LD drivers/gpu/drm/drm.o LD drivers/usb/core/built-in.o LD arch/x86/kernel/cpu/built-in.o LD net/core/built-in.o LD arch/x86/kernel/built-in.o LD net/built-in.o LD drivers/usb/host/xhci-hcd.o LD drivers/tty/vt/built-in.o LD drivers/tty/built-in.o LD arch/x86/built-in.o LD [M] drivers/net/ethernet/intel/igb/igb.o LD drivers/usb/host/built-in.o LD drivers/md/md-mod.o LD drivers/usb/built-in.o LD drivers/md/built-in.o LD fs/ext4/ext4.o LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o LD fs/ext4/built-in.o LD fs/built-in.o scripts/Makefile.build:551: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:551: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:551: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 make[1]: *** Waiting for unfinished jobs LD drivers/net/ethernet/built-in.o LD drivers/net/built-in.o Makefile:988: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for GET_PLANE2 w/ i915 implementation
This is expected because it's based on Ville's patch series to define the new modifiers. On 17-01-12 01:01:31, Patchwork wrote: == Series Details == Series: GET_PLANE2 w/ i915 implementation URL : https://patchwork.freedesktop.org/series/17873/ State : failure == Summary == LD [M] sound/pci/hda/snd-hda-codec-generic.o LD lib/built-in.o LD sound/pci/built-in.o LD drivers/acpi/built-in.o LD drivers/md/dm-mod.o LD sound/built-in.o LD drivers/scsi/scsi_mod.o LD drivers/video/fbdev/core/fb.o LD net/ipv6/ipv6.o LD drivers/video/fbdev/core/built-in.o LD drivers/pci/built-in.o LD drivers/usb/storage/usb-storage.o LD drivers/usb/storage/built-in.o drivers/gpu/drm/i915/intel_sprite.c:1043:2: error: ‘I915_FORMAT_MOD_Yf_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Yf_TILED_CCS, ^ drivers/gpu/drm/i915/intel_sprite.c:1044:2: error: ‘I915_FORMAT_MOD_Y_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Y_TILED_CCS, ^ LD net/ipv6/built-in.o scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/intel_sprite.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_sprite.o] Error 1 make[4]: *** Waiting for unfinished jobs LD [M] drivers/usb/serial/usbserial.o LD [M] drivers/misc/mei/mei-me.o LD drivers/misc/built-in.o LD drivers/thermal/thermal_sys.o LD drivers/thermal/built-in.o LD [M] drivers/gpu/drm/vgem/vgem.o LD drivers/tty/serial/8250/8250.o LD [M] drivers/mmc/core/mmc_block.o drivers/gpu/drm/i915/intel_display.c:100:2: error: ‘I915_FORMAT_MOD_Yf_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Yf_TILED_CCS, ^ drivers/gpu/drm/i915/intel_display.c:101:2: error: ‘I915_FORMAT_MOD_Y_TILED_CCS’ undeclared here (not in a function) I915_FORMAT_MOD_Y_TILED_CCS, ^ LD [M] drivers/net/ethernet/broadcom/genet/genet.o LD drivers/mmc/built-in.o LD drivers/usb/gadget/libcomposite.o LD drivers/video/fbdev/built-in.o LD drivers/spi/built-in.o drivers/gpu/drm/i915/intel_display.c: In function ‘skl_mod_supported’: drivers/gpu/drm/i915/intel_display.c:15053:20: error: comparison between pointer and integer [-Werror] return modifier == I915_FORMAT_MOD_Yf_TILED_CCS || ^ drivers/gpu/drm/i915/intel_display.c:15054:13: error: comparison between pointer and integer [-Werror] modifier == I915_FORMAT_MOD_Y_TILED_CCS || ^ LD drivers/scsi/sd_mod.o LD drivers/scsi/built-in.o LD net/ipv4/built-in.o LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o LD drivers/usb/gadget/udc/udc-core.o LD drivers/usb/gadget/udc/built-in.o cc1: all warnings being treated as errors scripts/Makefile.build:293: recipe for target 'drivers/gpu/drm/i915/intel_display.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_display.o] Error 1 LD drivers/usb/gadget/built-in.o LD drivers/video/console/built-in.o LD drivers/video/built-in.o LD drivers/iommu/built-in.o LD drivers/tty/serial/8250/8250_base.o LD drivers/tty/serial/8250/built-in.o LD drivers/tty/serial/built-in.o LD fs/btrfs/btrfs.o LD fs/btrfs/built-in.o LD [M] drivers/net/ethernet/intel/e1000/e1000.o LD drivers/usb/core/usbcore.o CC arch/x86/kernel/cpu/capflags.o LD drivers/gpu/drm/drm.o LD drivers/usb/core/built-in.o LD arch/x86/kernel/cpu/built-in.o LD net/core/built-in.o LD arch/x86/kernel/built-in.o LD net/built-in.o LD drivers/usb/host/xhci-hcd.o LD drivers/tty/vt/built-in.o LD drivers/tty/built-in.o LD arch/x86/built-in.o LD [M] drivers/net/ethernet/intel/igb/igb.o LD drivers/usb/host/built-in.o LD drivers/md/md-mod.o LD drivers/usb/built-in.o LD drivers/md/built-in.o LD fs/ext4/ext4.o LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o LD fs/ext4/built-in.o LD fs/built-in.o scripts/Makefile.build:551: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:551: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:551: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 make[1]: *** Waiting for unfinished jobs LD drivers/net/ethernet/built-in.o LD drivers/net/built-in.o Makefile:988: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2
On Wed, Jan 11, 2017 at 7:51 PM, Ben Widawsky wrote:
>
> +struct drm_format_modifier {
> + /* Bitmask of formats in get_plane format list this info
> +* applies to. */
> + uint64_t formats;
re: the uabi, I'd suggest to at least make this 'u32 offset; u32
formats'.. we can keep the existing implementation in this patch and
always set 'offset' to zero, and let the first one to hit more than 32
formats deal with the implementation. (Maybe a strategically placed
WARN_ON() if you go that route..)
Otherwise I guess it is just a couple years until getplane3 ;-)
BR,
-R
> +
> + /* This modifier can be used with the format for this plane. */
> + uint64_t modifier;
> +};
___
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