[Intel-gfx] [PATCH v3 00/16] HDCP 2.2 DP MST Support
v3 version of this series has fixed the CI reported failures and added below patch in this series. [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed It has also added the Ack of Tomas to merge the mei_hdcp.c patch via drm-intel. This series has been tested with IGT changes to do a single commit to enable HDCP on all DP-MST connector. HDCP 2.2 support over DP MST actually starts from below patch [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init. Gen12 HDCP 1.4 support of this series has also floated separately with below series. (https://patchwork.freedesktop.org/series/82605/) Anshuman Gupta (16): drm/i915/hdcp: Update CP property in update_pipe drm/i915/hdcp: Get conn while content_type changed drm/i915/hotplug: Handle CP_IRQ for DP-MST drm/i915/hdcp: DP MST transcoder for link and stream drm/i915/hdcp: Move HDCP enc status timeout to header drm/i915/hdcp: HDCP stream encryption support drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support drm/i915/hdcp: Pass dig_port to intel_hdcp_init drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len drm/hdcp: Max MST content streams drm/i915/hdcp: MST streams support in hdcp port_data drm/i915/hdcp: Pass connector to check_2_2_link drm/i915/hdcp: Add HDCP 2.2 stream register drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks drm/i915/hdcp: Enable HDCP 2.2 MST support drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- .../drm/i915/display/intel_display_types.h| 20 +- drivers/gpu/drm/i915/display/intel_dp.c | 14 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 168 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 282 ++ drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/i915_reg.h | 31 ++ drivers/misc/mei/hdcp/mei_hdcp.c | 3 +- include/drm/drm_hdcp.h| 8 +- 12 files changed, 465 insertions(+), 120 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0d9e8d3b5603..42cf91cf4f20 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (content_protection_type_changed) {
mutex_lock(&hdcp->mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(&connector->base);
schedule_work(&hdcp->prop_work);
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
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[Intel-gfx] [PATCH v3 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24e0067c2e7c..dfb5be64e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 384e384cb9e2..a0c62e363c39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct
intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2e719df1e5b1..86a3ffadd97f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1942,7 +1942,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
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[Intel-gfx] [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++-
drivers/gpu/drm/i915/display/intel_hdcp.h| 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 652d4645f255..384e384cb9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
*dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 46c9bd588db1..10770bf0e85e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1985,12 +1985,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
-enum port port,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2063,14 +2064,15 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2080,7 +2082,7 @@ static void intel_hdcp2_init(struct intel_connector
*connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2091,7 +2093,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8
content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/in
[Intel-gfx] [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bf8730267cfd..fbeffdfd1a0d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder
*intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index c47124a679b6..59b8fc21e3e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..652d4645f255 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder
cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+ break;
+ case TRANSCODER_D:
+ stream_enc_mask = HDCP_STATUS_S
[Intel-gfx] [PATCH v3 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h| 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fbeffdfd1a0d..a46ba4e6a835 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder
*encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 59b8fc21e3e8..749c3a7e0b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1446,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 10770bf0e85e..207fa17129ae 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include
#include
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1031,7 +1032,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1060,7 +1062,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1087,7 +1090,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1112,7 +1116,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1138,7 +1143,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ stru
[Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86a9a5145e47..cb6ec2c241f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9882,6 +9882,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9921,6 +9922,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+
_TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_STREAM_STATUS(trans) : \
+PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_AUTH_STREAM(trans) : \
+PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
Enable HDCP 2.2 over DP MST.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 86a3ffadd97f..98225777c9f9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1696,6 +1696,32 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2
stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -1834,7 +1860,7 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1849,6 +1875,8 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1893,11 +1921,23 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream
enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1921,6 +1961,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -1998,6 +2039,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
}
out:
+ mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
@@ -2179,7 +2221,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 01/16] drm/i915/hdcp: Update CP property in update_pipe
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
update_pipe instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actually hdcp->value was ENABLED.
This caught with DP MST setup, when disabling HDCP on a connector
sets the crtc state need_modeset to true for all crtc driving
the other DP-MST topology connectors.
v2:
Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
state")
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..0d9e8d3b5603 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2221,6 +2221,11 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
mutex_unlock(&hdcp->mutex);
+
+ if (!desired_and_not_enabled &&
!content_protection_type_changed) {
+ drm_connector_get(&connector->base);
+ schedule_work(&hdcp->prop_work);
+ }
}
if (desired_and_not_enabled || content_protection_type_changed)
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 -
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a9b652c6e742..61252d4be3dd 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS))
{
drm_err(&dev_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector
*connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct
intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..21c6c9828cd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link
status
* @intel_dp: Intel DP struct
@@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
+
if (!handled)
break;
--
2.26.2
___
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24e0067c2e7c..dfb5be64e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 384e384cb9e2..a0c62e363c39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct
intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 41c6892d959a..9dd08e2636e9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1945,7 +1945,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h| 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index fbeffdfd1a0d..a46ba4e6a835 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder
*encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 59b8fc21e3e8..749c3a7e0b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1446,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 10770bf0e85e..207fa17129ae 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include
#include
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1031,7 +1032,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1060,7 +1062,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1087,7 +1090,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1112,7 +1116,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1138,7 +1143,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ stru
[Intel-gfx] [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index bf8730267cfd..fbeffdfd1a0d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder
*intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index c47124a679b6..59b8fc21e3e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..652d4645f255 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder
cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+ break;
+ case TRANSCODER_D:
+ stream_enc_mask = HDCP_STATUS_S
[Intel-gfx] [PATCH v3 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size. It is based upon the actual number of MST streams and size of wired_cmd_repeater_auth_stream_req_in. Excluding the size of hdcp_cmd_header. v2: hdcp_cmd_header size annotation nitpick. [Tomas] Cc: Tomas Winkler Cc: Ramalingam C Acked-by: Tomas Winkler Signed-off-by: Anshuman Gupta --- drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index 9ae9669e46ea..3506a3534294 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev, verify_mprime_in->header.api_version = HDCP_API_VERSION; verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ; verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS; - verify_mprime_in->header.buffer_len = - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN; + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header); verify_mprime_in->port.integrated_port_type = data->port_type; verify_mprime_in->port.physical_port = (u8)data->fw_ddi; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0d9e8d3b5603..42cf91cf4f20 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (content_protection_type_changed) {
mutex_lock(&hdcp->mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(&connector->base);
schedule_work(&hdcp->prop_work);
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 09811be08cfe..bf8730267cfd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..c47124a679b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -432,6 +432,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..16865b200062 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 42cf91cf4f20..a9b652c6e742 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8
content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc =
intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2231,7 +2238,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@
[Intel-gfx] [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++-
drivers/gpu/drm/i915/display/intel_hdcp.h| 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 652d4645f255..384e384cb9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
*dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 46c9bd588db1..10770bf0e85e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1985,12 +1985,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
-enum port port,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2063,14 +2064,15 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2080,7 +2082,7 @@ static void intel_hdcp2_init(struct intel_connector
*connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2091,7 +2093,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8
content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/in
[Intel-gfx] [PATCH v3 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++---
2 files changed, 93 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 749c3a7e0b45..24e0067c2e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1445,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 207fa17129ae..41c6892d959a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,64 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static int
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ bool enforce_type0 = false;
+ int k;
+
+ if (dig_port->port_auth)
+ return 0;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!enforce_type0 && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_id =
intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k
== 0))
+ return -EINVAL;
+
+ /*
+* Apply common protection level across all streams in DP MST Topology.
+* Use highest supported content type for all streams in DP MST
Topology.
+*/
+ for (k = 0; k < data->k; k++)
+ data->streams[k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1296,6 +1354,7 @@ static int hdcp2_authenticate_port(struct intel_connector
*connector)
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
+
mutex_unlock(&dev_priv->hdcp_comp_mutex);
return ret;
@@ -1477,13 +1536,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1493,15 +1553,18 @@ int _hdcp2_propagate_stream_management
[Intel-gfx] [PATCH v3 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support
This is v3 version to test with IGT https://patchwork.freedesktop.org/series/82987/ This has some fix for Type1 content igt test. It has been also tested manually with IGT above series. [PATCH v3 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len has an Ack from Tomas to merge it via drm-intel. [PATCH v3 11/16] drm/hdcp: Max MST content streams has an Ack from drm-misc maintainer to merge it via dm-intel. Test-with: 20201023100709.5211-2-karthik@intel.com Anshuman Gupta (16): drm/i915/hdcp: Update CP property in update_pipe drm/i915/hdcp: Get conn while content_type changed drm/i915/hotplug: Handle CP_IRQ for DP-MST drm/i915/hdcp: DP MST transcoder for link and stream drm/i915/hdcp: Move HDCP enc status timeout to header drm/i915/hdcp: HDCP stream encryption support drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support drm/i915/hdcp: Pass dig_port to intel_hdcp_init drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len drm/hdcp: Max MST content streams drm/i915/hdcp: MST streams support in hdcp port_data drm/i915/hdcp: Pass connector to check_2_2_link drm/i915/hdcp: Add HDCP 2.2 stream register drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks drm/i915/hdcp: Enable HDCP 2.2 MST support drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- .../drm/i915/display/intel_display_types.h| 20 +- drivers/gpu/drm/i915/display/intel_dp.c | 14 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 168 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 285 ++ drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/i915_reg.h | 31 ++ drivers/misc/mei/hdcp/mei_hdcp.c | 3 +- include/drm/drm_hdcp.h| 8 +- 12 files changed, 468 insertions(+), 120 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 11/16] drm/hdcp: Max MST content streams
Let's define Maximum MST content streams up to four generically which can be supported by modern display controllers. Cc: Sean Paul Cc: Ramalingam C Acked-by: Maarten Lankhorst Signed-off-by: Anshuman Gupta --- include/drm/drm_hdcp.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index fe58dbb46962..ac22c246542a 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -101,11 +101,11 @@ /* Following Macros take a byte at a time for bit(s) masking */ /* - * TODO: This has to be changed for DP MST, as multiple stream on - * same port is possible. - * For HDCP2.2 on HDMI and DP SST this value is always 1. + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual + * H/W MST streams capacity. + * This required to be moved out to platform specific header. */ -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4 #define HDCP_2_2_TXCAP_MASK_LEN2 #define HDCP_2_2_RXCAPS_LEN3 #define HDCP_2_2_RX_REPEATER(x)((x) & BIT(0)) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++---
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 16865b200062..f00e12fc83e8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -826,13 +826,9 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
- ret = intel_dp_init_hdcp(dig_port, intel_connector);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
+ ret = intel_dp_init_hdcp(dig_port, intel_connector);
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
/*
* Reuse the prop from the SST connector because we're
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 61252d4be3dd..46c9bd588db1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
return ret;
}
-/* Implements Part 1 of the HDCP authorization procedure */
+/*
+ * Implements Part 1 of the HDCP authorization procedure.
+ * Authentication Part 1 steps for Multi-stream DisplayPort.
+ * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
+ * Step 2. Enable encryption for each stream that requires encryption.
+ */
static int intel_hdcp_auth(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
return -ETIMEDOUT;
}
- /*
-* XXX: If we have MST-connected devices, we need to enable encryption
-* on those as well.
-*/
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -790,19 +801,26 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ /*
+* Step 1: Deselect HDCP Multiplestream Bit.
+* Step 2: poll for stream encryption status to be disable.
+*/
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4
stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream
encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
/*
-* If there are other connectors on this port using HDCP, don't disable
-* it. Instead, toggle the HDCP signalling off on that particular
-* connector/pipe and exit.
+* If there are other connectors on this port using HDCP, don't disable
it.
+* Repeat steps 1-2 for each stream that no longer requires encryption.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv,
[Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 86a9a5145e47..cb6ec2c241f2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9882,6 +9882,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9921,6 +9922,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+
_TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_STREAM_STATUS(trans) : \
+PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_AUTH_STREAM(trans) : \
+PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
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[Intel-gfx] [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 81 +--
2 files changed, 77 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index a0c62e363c39..d57ece74c300 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_strem_encryption(struct
intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,70 @@ bool intel_dp_mst_hdcp_check_link(struct
intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_strem_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ if (enable && !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
cpu_transcoder, port)) &
+ AUTH_STREAM_TYPE) != data->streams[0].stream_type) {
+ drm_err(&i915->drm, "Seurity f/w didn't set correct auth
strem_type\n");
+ }
+
+ ret = intel_dp_mst_toggle_select_hdcp_stream(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915,
cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption
%s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' is QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ int ret;
+
+ ret = intel_d
[Intel-gfx] [PATCH v3 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
Enable HDCP 2.2 over DP MST.
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 9dd08e2636e9..621c1a94c5ad 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1698,6 +1698,32 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2
stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -1836,7 +1862,7 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1851,6 +1877,8 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1896,11 +1924,23 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream
enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1924,6 +1964,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -2001,6 +2042,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
}
out:
+ mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
@@ -2182,7 +2224,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
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Re: [Intel-gfx] [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed
On 2020-10-27 at 11:04:17 +0530, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Anshuman Gupta
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: seanp...@chromium.org; Nikula, Jani ; C,
> > Ramalingam ; Li, Juston ;
> > Shankar, Uma ; Gupta, Anshuman
> >
> > Subject: [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed
> >
> > Get DRM connector reference count while scheduling a prop work to avoid any
> > possible destroy of DRM connector when it is in DRM_CONNECTOR_REGISTERED
> > state.
> >
> > Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
> > connectors")
> > Cc: Sean Paul
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 0d9e8d3b5603..42cf91cf4f20 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
> > *state,
> > if (content_protection_type_changed) {
> > mutex_lock(&hdcp->mutex);
> > hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> > + drm_connector_get(&connector->base);
>
> Where are releasing this ref.
Thanks Uma for review the releasing ref is present in prop work function.
intel_hdcp_prop_work().
As prop function releases the ref for connector somtimes it lead to destroy
the connector, if we schedule the prop work without taking any connector
reference.
Thanks,
Anshuman Gupta.
>
> > schedule_work(&hdcp->prop_work);
> > mutex_unlock(&hdcp->mutex);
> > }
> > --
> > 2.26.2
>
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Re: [Intel-gfx] [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support
On 2020-10-27 at 11:50:13 +0530, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Anshuman Gupta
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: seanp...@chromium.org; Nikula, Jani ; C,
> > Ramalingam ; Li, Juston ;
> > Shankar, Uma ; Gupta, Anshuman
> >
> > Subject: [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support
> >
> > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit in
> > TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP encryption over
> > DP MST Transport Link.
> >
> > HDCP 1.4 stream encryption requires to validate the stream encryption
> > status in
> > HDCP_STATUS_{TRANSCODER,PORT} register driving that link in order to
> > enable/disable the stream encryption.
> >
> > Both of above requirement are same for all Gen with respect to B.Spec
> > Documentation.
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > .../drm/i915/display/intel_display_types.h| 4 +
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 6 files changed, 90 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index bf8730267cfd..fbeffdfd1a0d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
> > intel_crtc_state *crtc_state
> > }
> > }
> >
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > -enum transcoder cpu_transcoder,
> > -bool enable)
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask)
> > {
> > struct drm_device *dev = intel_encoder->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev); @@ -1965,9 +1965,9
> > @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> >
> > tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > if (enable)
> > - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> > + tmp |= hdcp_mask;
> > else
> > - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> > + tmp &= ~hdcp_mask;
> > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> > intel_display_power_put(dev_priv, intel_encoder->power_domain,
> > wakeref);
> > return ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> > b/drivers/gpu/drm/i915/display/intel_ddi.h
> > index dcc711cfe4fe..a4dd815c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > u32 ddi_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state); -int
> > intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > -enum transcoder cpu_transcoder,
> > -bool enable);
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask);
> > void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> >
> > #endif /* __INTEL_DDI_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c47124a679b6..59b8fc21e3e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> > enum transcoder cpu_transcoder,
> > bool enable);
> >
> > + /* Enable/Disable stream encryption on DP MST Transport Li
Re: [Intel-gfx] [PATCH v3 01/16] drm/i915/hdcp: Update CP property in update_pipe
On 2020-10-27 at 11:02:26 +0530, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Anshuman Gupta
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: seanp...@chromium.org; Nikula, Jani ; C,
> > Ramalingam ; Li, Juston ;
> > Shankar, Uma ; Gupta, Anshuman
> >
> > Subject: [PATCH v3 01/16] drm/i915/hdcp: Update CP property in update_pipe
> >
> > When crtc state need_modeset is true it is not necessary it is going to be
> > a real
> > modeset, it can turns to be a update_pipe instead of modeset.
>
> I believe you refer fastest here. May be make this a bit clear.
>
> > This turns content protection property to be DESIRED and hdcp update_pipe
> > left
> > with property to be in DESIRED state but actually hdcp->value was ENABLED.
> > This caught with DP MST setup, when disabling HDCP on a connector sets the
> > crtc
> > state need_modeset to true for all crtc driving the other DP-MST topology
> > connectors.
>
> This is a bit ambiguous, you can mention it a bit more clearly. In case of DP
> MST, how this
> affects would help make it clearer.
>
> >
> > v2:
> > Fix WARN_ON(connector->base.registration_state ==
> > DRM_CONNECTOR_REGISTERED)
> >
> > Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
> > state")
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index b2a4bbcfdcd2..0d9e8d3b5603 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -2221,6 +2221,11 @@ void intel_hdcp_update_pipe(struct
> > intel_atomic_state *state,
> > desired_and_not_enabled =
> > hdcp->value !=
> > DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > mutex_unlock(&hdcp->mutex);
> >
>
> Please add a comment explaining the rationale here as well.
Sure i will fix all above comment.
>
> > + if (!desired_and_not_enabled &&
> > !content_protection_type_changed) {
> > + drm_connector_get(&connector->base);
>
> Where are we releasing this ref.
prop worker function releases the connector reference.
Thanks,
Anshuman Gupta.
>
> > + schedule_work(&hdcp->prop_work);
> > + }
> > }
> >
> > if (desired_and_not_enabled || content_protection_type_changed)
> > --
> > 2.26.2
>
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Re: [Intel-gfx] [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
On 2020-10-27 at 11:59:14 +0530, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Anshuman Gupta
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: seanp...@chromium.org; Nikula, Jani ; C,
> > Ramalingam ; Li, Juston ;
> > Shankar, Uma ; Gupta, Anshuman
> >
> > Subject: [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST
> > support
> >
> > Enable HDCP 1.4 over DP MST for Gen12.
> > This also enable the stream encryption support for older generations, which
> > was
> > missing earlier.
> >
> > v2:
> > - Added debug print for stream encryption.
> > - Disable the hdcp on port after disabling last stream
> > encryption.
>
> Don't see port disable here, Am I missing something.
Do u mean disbaling HDCP for a port ?
That is being done when dig_port->num_hdcp_streams are zero,
then it disbale the HDCP for entire port.
My earlier version of this patch was missing below hunk
if (dig_port->num_hdcp_streams > 0)
return ret;
I will fix the other cosmetics comment on this patch.
Thanks,
Anshuman Gupta.
>
> >
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++---
> > 2 files changed, 35 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 16865b200062..f00e12fc83e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -826,13 +826,9 @@ static struct drm_connector
> > *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> > intel_attach_force_audio_property(connector);
> > intel_attach_broadcast_rgb_property(connector);
> >
> > -
> > - /* TODO: Figure out how to make HDCP work on GEN12+ */
> > - if (INTEL_GEN(dev_priv) < 12) {
> > - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > - if (ret)
> > - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> > - }
> > + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > + if (ret)
> > + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
> >
> > /*
> > * Reuse the prop from the SST connector because we're diff --git
> > a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 61252d4be3dd..46c9bd588db1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
> > *connector)
> > return ret;
> > }
> >
> > -/* Implements Part 1 of the HDCP authorization procedure */
> > +/*
> > + * Implements Part 1 of the HDCP authorization procedure.
> > + * Authentication Part 1 steps for Multi-stream DisplayPort.
> > + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> > + * Step 2. Enable encryption for each stream that requires encryption.
> > + */
> > static int intel_hdcp_auth(struct intel_connector *connector) {
> > struct intel_digital_port *dig_port =
> > intel_attached_dig_port(connector);
> > @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
> > *connector)
> > return -ETIMEDOUT;
> > }
> >
> > - /*
> > -* XXX: If we have MST-connected devices, we need to enable encryption
> > -* on those as well.
> > -*/
> > + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> > + if (shim->stream_encryption) {
> > + ret = shim->stream_encryption(dig_port, true);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
> > stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
> > encrypted\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> >
> > if (repeater_present)
> > return intel_hdcp_auth_downstream(connector);
> > @@ -790,19 +801,26 @@ static int _intel_hdcp_disable(struct intel_connector
> > *connector)
> >
> > drm_dbg_kms(&dev
Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
On 2020-10-27 at 12:41:41 +0530, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Anshuman Gupta
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: seanp...@chromium.org; Nikula, Jani ; C,
> > Ramalingam ; Li, Juston ;
> > Shankar, Uma ; Gupta, Anshuman
> >
> > Subject: [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
> >
> > Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> > and HDCP2_AUTH_STREAM register in i915_reg header.
> >
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 30 ++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 86a9a5145e47..cb6ec2c241f2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9882,6 +9882,7 @@ enum skl_power_gate {
> > _PORTD_HDCP2_BASE, \
> > _PORTE_HDCP2_BASE, \
> > _PORTF_HDCP2_BASE) + (x))
> > +
> > #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
> > #define _TRANSA_HDCP2_AUTH 0x66498
> > #define _TRANSB_HDCP2_AUTH 0x66598
> > @@ -9921,6 +9922,35 @@ enum skl_power_gate {
> > TRANS_HDCP2_STATUS(trans) : \
> > PORT_HDCP2_STATUS(port))
> >
> > +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port,
> > 0xC0)
> > +#define _TRANSA_HDCP2_STREAM_STATUS0x664C0
> > +#define _TRANSB_HDCP2_STREAM_STATUS0x665C0
> > +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
> > +
> > _TRANSA_HDCP2_STREAM_STATUS, \
> > +
> > _TRANSB_HDCP2_STREAM_STATUS)
> > +#define STREAM_ENCRYPTION_STATUS BIT(31)
> > +#define STREAM_TYPE_STATUS BIT(30)
> > +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > +TRANS_HDCP2_STREAM_STATUS(trans) :
> > \
> > +PORT_HDCP2_STREAM_STATUS(port))
> > +
> > +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
> > +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
> > +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
> > +
> > _PORTA_HDCP2_AUTH_STREAM, \
> > +
> > _PORTB_HDCP2_AUTH_STREAM)
>
> Should it also not be defined as the other counterparts for pre Gen12.
It has already been defined with Gen12 and Pre Gen12 annotation below
HDCP2_AUTH_STREAM should TRANS_HDCP2_AUTH_STREAM for Gen12 and
PORT_HDCP2_AUTH_STREAM for pre Gen12.
Is it something else u find it is missing ?
Thanks,
Anshuman.
>
> > +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
> > +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
> > +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
> > +
> > _TRANSA_HDCP2_AUTH_STREAM, \
> > +
> > _TRANSB_HDCP2_AUTH_STREAM)
> > +#define AUTH_STREAM_TYPE BIT(31)
> > +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
> > + (INTEL_GEN(dev_priv) >= 12 ? \
> > +TRANS_HDCP2_AUTH_STREAM(trans) : \
> > +PORT_HDCP2_AUTH_STREAM(port))
> > +
> > /* Per-pipe DDI Function Control */
> > #define _TRANS_DDI_FUNC_CTL_A 0x60400
> > #define _TRANS_DDI_FUNC_CTL_B 0x61400
> > --
> > 2.26.2
>
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Re: [Intel-gfx] [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
On 2020-10-27 at 11:59:14 +0530, Shankar, Uma wrote:
>
>
> > -Original Message-
> > From: Anshuman Gupta
> > Sent: Friday, October 23, 2020 5:51 PM
> > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
> > Cc: seanp...@chromium.org; Nikula, Jani ; C,
> > Ramalingam ; Li, Juston ;
> > Shankar, Uma ; Gupta, Anshuman
> >
> > Subject: [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST
> > support
> >
> > Enable HDCP 1.4 over DP MST for Gen12.
> > This also enable the stream encryption support for older generations, which
> > was
> > missing earlier.
> >
> > v2:
> > - Added debug print for stream encryption.
> > - Disable the hdcp on port after disabling last stream
> > encryption.
>
> Don't see port disable here, Am I missing something.
>
> >
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++---
> > 2 files changed, 35 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 16865b200062..f00e12fc83e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -826,13 +826,9 @@ static struct drm_connector
> > *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> > intel_attach_force_audio_property(connector);
> > intel_attach_broadcast_rgb_property(connector);
> >
> > -
> > - /* TODO: Figure out how to make HDCP work on GEN12+ */
> > - if (INTEL_GEN(dev_priv) < 12) {
> > - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > - if (ret)
> > - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> > - }
> > + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > + if (ret)
> > + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
> >
> > /*
> > * Reuse the prop from the SST connector because we're diff --git
> > a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 61252d4be3dd..46c9bd588db1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
> > *connector)
> > return ret;
> > }
> >
> > -/* Implements Part 1 of the HDCP authorization procedure */
> > +/*
> > + * Implements Part 1 of the HDCP authorization procedure.
> > + * Authentication Part 1 steps for Multi-stream DisplayPort.
> > + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> > + * Step 2. Enable encryption for each stream that requires encryption.
> > + */
> > static int intel_hdcp_auth(struct intel_connector *connector) {
> > struct intel_digital_port *dig_port =
> > intel_attached_dig_port(connector);
> > @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
> > *connector)
> > return -ETIMEDOUT;
> > }
> >
> > - /*
> > -* XXX: If we have MST-connected devices, we need to enable encryption
> > -* on those as well.
> > -*/
> > + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> > + if (shim->stream_encryption) {
> > + ret = shim->stream_encryption(dig_port, true);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
> > stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
> > encrypted\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> >
> > if (repeater_present)
> > return intel_hdcp_auth_downstream(connector);
> > @@ -790,19 +801,26 @@ static int _intel_hdcp_disable(struct intel_connector
> > *connector)
> >
> > drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> > connector->base.name, connector->base.base.id);
> > + /*
> > +* Step 1: Deselect HDCP Multiplestream Bit.
> > +* Step 2: poll for stream encryption status to be disable.
> > +*/
>
> The above com
[Intel-gfx] [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index eee8263405b9..b9d8825e2bb1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (content_protection_type_changed) {
mutex_lock(&hdcp->mutex);
hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+ drm_connector_get(&connector->base);
schedule_work(&hdcp->prop_work);
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
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[Intel-gfx] [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..21c6c9828cd7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5657,6 +5657,17 @@ static void intel_dp_handle_test_request(struct intel_dp
*intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link
status
* @intel_dp: Intel DP struct
@@ -5701,7 +5712,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
+
if (!handled)
break;
--
2.26.2
___
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[Intel-gfx] [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")'
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 -
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index fc5de48456ad..0322a83c151d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS))
{
drm_err(&dev_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector
*connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct
intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 63380b166c25..9fce623e951e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..c47124a679b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -432,6 +432,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c8fcec4d0788..16865b200062 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state
*state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b9d8825e2bb1..fc5de48456ad 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8
content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc =
intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/displa
[Intel-gfx] [PATCH v4 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support
This is v4 version to test with IGT https://patchwork.freedesktop.org/series/82987/ This has addressed the review comments from Uma. It has been also tested manually with IGT above series. [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len has an Ack from Tomas to merge it via drm-intel. [PATCH v4 11/16] drm/hdcp: Max MST content streams has an Ack from drm-misc maintainer to merge it via dm-intel. Test-with: 20201023100709.5211-2-karthik@intel.com Anshuman Gupta (16): drm/i915/hdcp: Update CP property in update_pipe drm/i915/hdcp: Get conn while content_type changed drm/i915/hotplug: Handle CP_IRQ for DP-MST drm/i915/hdcp: DP MST transcoder for link and stream drm/i915/hdcp: Move HDCP enc status timeout to header drm/i915/hdcp: HDCP stream encryption support drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support drm/i915/hdcp: Pass dig_port to intel_hdcp_init drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len drm/hdcp: Max MST content streams drm/i915/hdcp: MST streams support in hdcp port_data drm/i915/hdcp: Pass connector to check_2_2_link drm/i915/hdcp: Add HDCP 2.2 stream register drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks drm/i915/hdcp: Enable HDCP 2.2 MST support drivers/gpu/drm/i915/display/intel_ddi.c | 14 +- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +- .../drm/i915/display/intel_display_types.h| 20 +- drivers/gpu/drm/i915/display/intel_dp.c | 14 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 167 -- drivers/gpu/drm/i915/display/intel_dp_mst.c | 12 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 285 ++ drivers/gpu/drm/i915/display/intel_hdcp.h | 8 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/i915_reg.h | 31 ++ drivers/misc/mei/hdcp/mei_hdcp.c | 3 +- include/drm/drm_hdcp.h| 8 +- 12 files changed, 466 insertions(+), 121 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This issue is caught with DP MST setup, where we have multiple
connector in same DP_MST topology. When disabling HDCP on one of
DP MST connector leads to set the crtc state need_modeset to true
for all other crtc driving the other DP-MST topology connectors.
This turns up other DP MST connectors CP property to be DESIRED
despite the actual hdcp->value is ENABLED.
Above scenario fails the DP MST HDCP IGT test, disabling HDCP on
one MST stream should not cause to disable HDCP on another MST
stream on same DP MST topology.
v2:
Fix WARN_ON(connector->base.registration_state == DRM_CONNECTOR_REGISTERED)
v3:
Commit log improvement. [Uma]
Added a comment before scheduling prop_work. [Uma]
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal
state")
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..eee8263405b9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2221,6 +2221,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
mutex_unlock(&hdcp->mutex);
+ /*
+* If HDCP already ENABLED and CP property is DESIRED, schedule
+* prop_work to update correct CP property to user space.
+*/
+ if (!desired_and_not_enabled &&
!content_protection_type_changed) {
+ drm_connector_get(&connector->base);
+ schedule_work(&hdcp->prop_work);
+ }
}
if (desired_and_not_enabled || content_protection_type_changed)
--
2.26.2
___
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[Intel-gfx] [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 24e0067c2e7c..dfb5be64e03a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 591b68e5de48..4be61e7fde4e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct
intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 1df6d4a23476..87f7aaf3a319 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port
*dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
___
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[Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic chnages. [Uma]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +--
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4be61e7fde4e..35c1543fe0e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct
intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
+bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ drm_WARN_ON(&i915->drm, enable &&
+ !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
cpu_transcoder, port))
+ & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915,
cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption
%s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+
[Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++-
drivers/gpu/drm/i915/display/intel_hdcp.h| 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 6dcbfaffd2c5..591b68e5de48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
*dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 937af4aeaac2..b0f47687bc59 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
-enum port port,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct drm_i915_private
*dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector
*connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8
content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/dr
[Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
v2:
Cosmetic changes function name, error msg print and
stream typo fixes. [Uma]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9fce623e951e..779603a38cfc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder
*intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
-enum transcoder cpu_transcoder,
-bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index c47124a679b6..59b8fc21e3e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..6dcbfaffd2c5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder
cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+
[Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
v3:
Cosmetic changes. [Uma]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++---
2 files changed, 92 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 749c3a7e0b45..24e0067c2e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1445,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a5ec4f72f50f..1df6d4a23476 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,64 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static int
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ bool enforce_type0 = false;
+ int k;
+
+ if (dig_port->port_auth)
+ return 0;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ if (!enforce_type0 && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_id =
intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k
== 0))
+ return -EINVAL;
+
+ /*
+* Apply common protection level across all streams in DP MST Topology.
+* Use highest supported content type for all streams in DP MST
Topology.
+*/
+ for (k = 0; k < data->k; k++)
+ data->streams[k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
DRM_MODE_HDCP_CONTENT_TYPE1;
+
+ return 0;
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1474,13 +1532,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1489,16 +1548,18 @@ int _hdcp2_propagate_stream_management_info(struct
intel_connector *connector)
msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE;
drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
- /* K no of streams is fixed as 1. Stored as big-endian. */
- msgs.stream_manage.k = cpu_to_be
[Intel-gfx] [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77461cde6549..c9678c77883d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9894,6 +9894,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9933,6 +9934,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+
_TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_STREAM_STATUS(trans) : \
+PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+TRANS_HDCP2_AUTH_STREAM(trans) : \
+PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size. It is based upon the actual number of MST streams and size of wired_cmd_repeater_auth_stream_req_in. Excluding the size of hdcp_cmd_header. v2: hdcp_cmd_header size annotation nitpick. [Tomas] Cc: Tomas Winkler Cc: Ramalingam C Acked-by: Tomas Winkler Reviewed-by: Uma Shankar Signed-off-by: Anshuman Gupta --- drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index 9ae9669e46ea..3506a3534294 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev, verify_mprime_in->header.api_version = HDCP_API_VERSION; verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ; verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS; - verify_mprime_in->header.buffer_len = - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN; + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header); verify_mprime_in->port.integrated_port_type = data->port_type; verify_mprime_in->port.physical_port = (u8)data->fw_ddi; -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 11/16] drm/hdcp: Max MST content streams
Let's define Maximum MST content streams up to four generically which can be supported by modern display controllers. Cc: Sean Paul Cc: Ramalingam C Acked-by: Maarten Lankhorst Reviewed-by: Uma Shankar Signed-off-by: Anshuman Gupta --- include/drm/drm_hdcp.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h index fe58dbb46962..ac22c246542a 100644 --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h @@ -101,11 +101,11 @@ /* Following Macros take a byte at a time for bit(s) masking */ /* - * TODO: This has to be changed for DP MST, as multiple stream on - * same port is possible. - * For HDCP2.2 on HDMI and DP SST this value is always 1. + * TODO: HDCP_2_2_MAX_CONTENT_STREAMS_CNT is based upon actual + * H/W MST streams capacity. + * This required to be moved out to platform specific header. */ -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4 #define HDCP_2_2_TXCAP_MASK_LEN2 #define HDCP_2_2_RXCAPS_LEN3 #define HDCP_2_2_RX_REPEATER(x)((x) & BIT(0)) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support
Enable HDCP 2.2 over DP MST.
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once all encrypted stream encryption is disabled,
disable the port HDCP encryption and deauthenticate the port.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 87f7aaf3a319..71fd01bf63a6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1693,6 +1693,32 @@ static int hdcp2_authenticate_sink(struct
intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder,
port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2
stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -1831,7 +1857,7 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1846,6 +1872,8 @@ static int hdcp2_authenticate_and_encrypt(struct
intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1891,11 +1919,23 @@ static int _intel_hdcp2_disable(struct intel_connector
*connector)
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream
enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1919,6 +1959,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -1996,6 +2037,7 @@ static int intel_hdcp2_check_link(struct intel_connector
*connector)
}
out:
+ mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
@@ -2177,7 +2219,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
v3:
- Cosmetic change, removed the value less comment. [Uma]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++---
2 files changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 16865b200062..f00e12fc83e8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -826,13 +826,9 @@ static struct drm_connector
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
- ret = intel_dp_init_hdcp(dig_port, intel_connector);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
+ ret = intel_dp_init_hdcp(dig_port, intel_connector);
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
/*
* Reuse the prop from the SST connector because we're
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0322a83c151d..937af4aeaac2 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
*connector)
return ret;
}
-/* Implements Part 1 of the HDCP authorization procedure */
+/*
+ * Implements Part 1 of the HDCP authorization procedure.
+ * Authentication Part 1 steps for Multi-stream DisplayPort.
+ * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
+ * Step 2. Enable encryption for each stream that requires encryption.
+ */
static int intel_hdcp_auth(struct intel_connector *connector)
{
struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
@@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
*connector)
return -ETIMEDOUT;
}
- /*
-* XXX: If we have MST-connected devices, we need to enable encryption
-* on those as well.
-*/
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector
*connector)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4
stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream
encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
+
/*
-* If there are other connectors on this port using HDCP, don't disable
-* it. Instead, toggle the HDCP signalling off on that particular
-* connector/pipe and exit.
+* If there are other connectors on this port using HDCP, don't disable
it.
+* Repeat steps 1-2 for each stream that no longer requires encryption.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
--
2.26.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +
.../drm/i915/display/intel_display_types.h| 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 56 +++
3 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 779603a38cfc..1bc6cf0b83ec 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4746,6 +4746,8 @@ static void intel_ddi_encoder_destroy(struct drm_encoder
*encoder)
intel_dp_encoder_flush_work(encoder);
drm_encoder_cleanup(encoder);
+ if (dig_port)
+ kfree(dig_port->port_data.streams);
kfree(dig_port);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 59b8fc21e3e8..749c3a7e0b45 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1446,10 +1445,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b0f47687bc59..a5ec4f72f50f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include
#include
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1028,7 +1029,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1057,7 +1059,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1084,7 +1087,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector
*connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1109,7 +1113,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1135,7 +1140,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &connector
Re: [Intel-gfx] [PATCH] drm/i915: Fix encoder lookup during PSR atomic check
On 2020-10-27 at 21:39:28 +0530, Imre Deak wrote: > The atomic check hooks must look up the encoder to be used with a > connector from the connector's atomic state, and not assume that it's > the connector's current attached encoder. The latter one can change > under the atomic check func, or can be unset yet as in the case of MST > connectors. I have also observed the similar crash while using DP-MST setup. Looks good to me. Reviewed-by: Anshuman Gupta > > This fixes > [7.940719] Oops: [#1] SMP NOPTI > [7.944407] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 5.6.0-1023-oem > #23-Ubuntu > [7.952102] Hardware name: Dell Inc. Latitude 7320/, BIOS 88.87.11 > 09/07/2020 > [7.959278] Workqueue: events output_poll_execute [drm_kms_helper] > [7.965511] RIP: 0010:intel_psr_atomic_check+0x37/0xa0 [i915] > [7.971327] Code: 80 2d 06 00 00 20 74 42 80 b8 34 71 00 00 00 74 39 48 8b > 72 08 48 85 f6 74 30 80 b8 f8 71 00 00 00 74 27 4c 8b 87 80 04 00 00 <41> 8b > 78 78 83 ff 08 77 19 31 c9 83 ff 05 77 19 48 81 c1 20 01 00 > [7.977541] input: PS/2 Generic Mouse as > /devices/platform/i8042/serio1/input/input5 > [7.990154] RSP: 0018:b864c073fac8 EFLAGS: 00010202 > [7.990155] RAX: 8c5d55ce RBX: 8c5d54519000 RCX: > > [7.990155] RDX: 8c5d55cb30c0 RSI: 8c5d89a0c800 RDI: > 8c5d55fcf800 > [7.990156] RBP: b864c073fac8 R08: R09: > 8c5d55d9f3a0 > [7.990156] R10: 8c5d55cb30c0 R11: 0009 R12: > 8c5d55fcf800 > [7.990156] R13: 8c5d55cb30c0 R14: 8c5d56989cc0 R15: > 8c5d56989cc0 > [7.990158] FS: () GS:8c5d8e48() > knlGS: > [8.047193] CS: 0010 DS: ES: CR0: 80050033 > [8.052970] CR2: 0078 CR3: 00085655 CR4: > 00760ee0 > [8.060137] PKRU: 5554 > [8.062867] Call Trace: > [8.065361] intel_digital_connector_atomic_check+0x53/0x130 [i915] > [8.071703] intel_dp_mst_atomic_check+0x5b/0x200 [i915] > [8.077074] drm_atomic_helper_check_modeset+0x1db/0x790 [drm_kms_helper] > [8.083942] intel_atomic_check+0x92/0xc50 [i915] > [8.088705] ? drm_plane_check_pixel_format+0x4f/0xb0 [drm] > [8.094345] ? drm_atomic_plane_check+0x7a/0x3a0 [drm] > [8.099548] drm_atomic_check_only+0x2b1/0x450 [drm] > [8.104573] drm_atomic_commit+0x18/0x50 [drm] > [8.109070] drm_client_modeset_commit_atomic+0x1c9/0x200 [drm] > [8.115056] drm_client_modeset_commit_force+0x55/0x160 [drm] > [8.120866] drm_fb_helper_restore_fbdev_mode_unlocked+0x54/0xb0 > [drm_kms_helper] > [8.128415] drm_fb_helper_set_par+0x34/0x50 [drm_kms_helper] > [8.134225] drm_fb_helper_hotplug_event.part.0+0xb4/0xe0 [drm_kms_helper] > [8.141150] drm_fb_helper_hotplug_event+0x1c/0x30 [drm_kms_helper] > [8.147481] intel_fbdev_output_poll_changed+0x6f/0xa0 [i915] > [8.153287] drm_kms_helper_hotplug_event+0x2c/0x40 [drm_kms_helper] > [8.159709] output_poll_execute+0x1aa/0x1c0 [drm_kms_helper] > [8.165506] process_one_work+0x1e8/0x3b0 > [8.169561] worker_thread+0x4d/0x400 > [8.173249] kthread+0x104/0x140 > [8.176515] ? process_one_work+0x3b0/0x3b0 > [8.180726] ? kthread_park+0x90/0x90 > [8.184416] ret_from_fork+0x1f/0x40 > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2361 > References: https://gitlab.freedesktop.org/drm/intel/-/issues/2486 > Reported-by: William Tseng > Reported-by: Cooper Chiou > Cc: > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/display/intel_psr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index b2544102e7b1..1576c3722d0b 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1884,7 +1884,7 @@ void intel_psr_atomic_check(struct drm_connector > *connector, > return; > > intel_connector = to_intel_connector(connector); > - dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector)); > + dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder)); > if (dev_priv->psr.dp != &dig_port->dp) > return; > > -- > 2.25.1 > > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] drm/i915: Acquire connector reference before prop_work
On 2020-10-27 at 16:03:35 +0530, Kamati Srinivas wrote:
> From: Srinivas Kamati
>
> "Content protection type change" igt test results in kernel
> taint. Everytime after prop_work is done we are also
> giving up connector reference, which is resulting in ref
> count underrun.
>
> Before scheduling prop_work acquire connector reference.
I has been alreayd taken care at
https://patchwork.freedesktop.org/patch/397215/?series=82998&rev=2
>
> Cc: Sean Paul
> Cc: Ramalingam C
> Signed-off-by: Srinivas Kamati
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b2a4bbcfdcd2..beedd672b21e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2210,6 +2210,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
> *state,
> if (content_protection_type_changed) {
> mutex_lock(&hdcp->mutex);
> hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
> + drm_connector_get(&connector->base);
> schedule_work(&hdcp->prop_work);
> mutex_unlock(&hdcp->mutex);
> }
> --
> 2.25.1
>
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
Hi Lakshmi,
Below HDCP over DP-MST patchwork series has unrelated failures from GEM and
display side as well.
Similar series i had sent earlier on tryboat it was passing
https://patchwork.freedesktop.org/series/82919/
Could you please let us know if below INCOMPLETE and DMESG-WARN are already
known issue
in case these are not known issue could we create bug and rerport the results.
All of the below igt@kms_frontbuffer_tracking are failing due to similar dmesg
warning.
igt@kms_big_fb is odd one out a kernel panic.
Rest of all are gem failures.
Thanks,
Anshuman Gupta.
On 2020-10-28 at 06:40:42 +, Patchwork wrote:
> == Series Details ==
>
> Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
> URL : https://patchwork.freedesktop.org/series/82998/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_18788_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_18788_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_18788_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@i915_selftest@live@evict:
> - shard-skl: [PASS][1] -> [INCOMPLETE][2] +1 similar issue
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-skl9/igt@i915_selftest@l...@evict.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-skl3/igt@i915_selftest@l...@evict.html
>
> * igt@kms_big_fb@linear-32bpp-rotate-180:
> - shard-glk: [PASS][3] -> [INCOMPLETE][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk8/igt@kms_big...@linear-32bpp-rotate-180.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk2/igt@kms_big...@linear-32bpp-rotate-180.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
> - shard-iclb: NOTRUN -> [INCOMPLETE][5] +2 similar issues
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt:
> - shard-tglb: NOTRUN -> [DMESG-WARN][6]
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb7/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
> - shard-iclb: NOTRUN -> [DMESG-WARN][7] +1 similar issue
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-iclb8/igt@kms_frontbuffer_track...@fbc-rgb565-draw-pwrite.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
> - shard-tglb: NOTRUN -> [INCOMPLETE][8] +11 similar issues
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-indfb-scaledprimary.html
>
> * igt@perf_pmu@busy-idle-no-semaphores@rcs0:
> - shard-hsw: [PASS][9] -> [FAIL][10]
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw4/igt@perf_pmu@busy-idle-no-semapho...@rcs0.html
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@perf_pmu@busy-idle-no-semapho...@rcs0.html
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_parallel@engines@userptr}:
> - shard-hsw: [PASS][11] -> [FAIL][12]
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engi...@userptr.html
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engi...@userptr.html
>
>
>
> ### Piglit changes ###
>
> Possible regressions
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][13] +2 similar issues
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functi...@gs-op-mult-dmat3-dmat3.html
>
>
> New tests
> -
&g
[Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms
From: Bob Paauwe
The WA specifies that we need to toggle a SDE chicken bit on and then
off as the final step in preparation for s0ix entry.
Bspec: 33450
Bspec: 8402
However, something is happening after we toggle the bit that causes
the WA to be invalidated. This makes dispcnlunit1_cp_xosc_clkreq
active being already in s0ix state i.e SLP_S0 counter incremented.
Tweaking the Wa_14010685332 by setting the bit on suspend and clearing
it on resume turns down the dispcnlunit1_cp_xosc_clkreq.
B.Spec has Documented this tweaked sequence of WA as an alternative.
Let keep this tweaked WA for Gen11 platforms and keep untweaked WA for
other platforms which never observed this issue.
v2 (MattR):
- Change the comment on the workaround to give PCH names rather than
platform names. Although the bspec is setup to list workarounds by
platform, the hardware team has confirmed that the actual issue being
worked around here is something that was introduced back in the
Cannon Lake PCH and carried forward to subsequent PCH's.
- Extend the untweaked version of the workaround to include PCH_CNP as
well. Note that since PCH_CNP is used to represent CMP, this will
apply on CML and some variants of RKL too.
- Cap the untweaked version of the workaround so that it won't apply to
"fake" PCH's (i.e., DG1). The issue we're working around really is
an issue in the PCH itself, not the South Display, so it shouldn't
apply when there isn't a real PCH.
Cc: Rodrigo Vivi
Signed-off-by: Bob Paauwe
Signed-off-by: Anshuman Gupta
Signed-off-by: Matt Roper
---
.../drm/i915/display/intel_display_power.c| 21 +--
drivers/gpu/drm/i915/i915_irq.c | 6 --
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 689922480661..d2a6518329d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5858,17 +5858,34 @@ static void intel_power_domains_verify_state(struct
drm_i915_private *i915)
void intel_display_power_suspend_late(struct drm_i915_private *i915)
{
- if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
+ u32 val;
+
+ if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
bxt_enable_dc9(i915);
- else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ /* Tweaked Wa_14010685332:icp,jsp,mcc */
+ if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
PCH_MCC) {
+ val = intel_de_read(i915, SOUTH_CHICKEN1);
+ val |= SBCLK_RUN_REFCLK_DIS;
+ intel_de_write(i915, SOUTH_CHICKEN1, val);
+ }
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_enable_pc8(i915);
+ }
}
void intel_display_power_resume_early(struct drm_i915_private *i915)
{
+ u32 val;
+
if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
gen9_sanitize_dc_state(i915);
bxt_disable_dc9(i915);
+ /* Tweaked Wa_14010685332:icp,jsp,mcc */
+ if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
PCH_MCC) {
+ val = intel_de_read(i915, SOUTH_CHICKEN1);
+ val &= ~SBCLK_RUN_REFCLK_DIS;
+ intel_de_write(i915, SOUTH_CHICKEN1, val);
+ }
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index dc33c96d741d..410c03624c6a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3055,8 +3055,10 @@ static void gen11_display_irq_reset(struct
drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ /* Wa_14010685332:cnp/cmp,tgp,adp */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
+INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
--
2.26.2
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
Hi Ram ,
Below series is reviewed by Uma and CI results are green.
New HDCP MST test are skipping since there is no HDCP and DP-MST coverage in CI.
But it have tested the new IGT test locally.
Could you please take a look at this in order to merge the series.
There is a typo require to fix in patch [v4,15/16] commit log, i will send
a patch for this.
"drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
-:13: WARNING:TYPO_SPELLING: 'chnages' may be misspelled - perhaps 'changes'?"
Thanks,
Anshuman Gupta.
On 2020-10-29 at 17:54:44 +, Patchwork wrote:
> == Series Details ==
>
> Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2)
> URL : https://patchwork.freedesktop.org/series/82998/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9206_full -> Patchwork_18788_full
>
>
> Summary
> ---
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_18788_full:
>
> ### IGT changes ###
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_parallel@engines@userptr}:
> - shard-hsw: [PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw6/igt@gem_exec_parallel@engi...@userptr.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_exec_parallel@engi...@userptr.html
>
>
>
> ### Piglit changes ###
>
> Possible regressions
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3 (NEW):
> - {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][3] +2 similar issues
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/pig-icl-1065g7/spec@glsl-4.00@execution@built-in-functi...@gs-op-mult-dmat3-dmat3.html
>
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_9206_full and
> Patchwork_18788_full:
>
> ### New CI tests (1) ###
>
> * boot:
> - Statuses : 200 pass(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New IGT tests (4) ###
>
> * igt@kms_content_protection@dp-mst-lic-type-0:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
> * igt@kms_content_protection@dp-mst-type-0:
> - Statuses : 6 skip(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@kms_content_protection@dp-mst-type-1:
> - Statuses : 5 skip(s)
> - Exec time: [0.0] s
>
>
>
>
> ### New Piglit tests (3) ###
>
> * spec@glsl-4.00@execution@built-in-functions@fs-op-mult-dmat4-dmat2x4:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat3-dmat3:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
> * spec@glsl-4.00@execution@built-in-functions@gs-op-mult-dmat4x3-double:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_18788_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@drm_read@empty-nonblock:
> - shard-glk: [PASS][4] -> [DMESG-WARN][5] ([i915#1982]) +2
> similar issues
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-glk7/igt@drm_r...@empty-nonblock.html
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-glk5/igt@drm_r...@empty-nonblock.html
>
> * igt@gem_exec_parallel@engines@contexts:
> - shard-snb: [PASS][6] -> [INCOMPLETE][7] ([i915#82])
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-snb5/igt@gem_exec_parallel@engi...@contexts.html
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-snb4/igt@gem_exec_parallel@engi...@contexts.html
>
> * igt@gem_userptr_blits@unsync-unmap-cycles:
> - shard-hsw: [PASS][8] -> [FAIL][9] ([i915#1888])
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9206/shard-hsw1/igt@gem_userptr_bl...@unsync-unmap-cycles.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18788/shard-hsw4/igt@gem_userptr_bl...@unsync-unmap-cycles.html
>
> * igt@i915_selftest@live@evict:
> - shard-skl: [PASS][10] -> [INC
[Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
Added a WARN_ON() instead of drm_err. [Uma]
Cosmetic changes. [Uma]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_types.h| 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +--
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index dfb5be64e03a..4cbb151ff3cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 4be61e7fde4e..35c1543fe0e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct
intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
+bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ drm_WARN_ON(&i915->drm, enable &&
+ !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915,
cpu_transcoder, port))
+ & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
+
+ ret = intel_dp_mst_toggle_hdcp_stream_select(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915,
cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption
%s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+
Re: [Intel-gfx] [PATCH] drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms
On 2020-11-03 at 17:06:42 -0500, Rodrigo Vivi wrote:
> On Fri, Oct 30, 2020 at 11:46:58AM +0530, Anshuman Gupta wrote:
> > From: Bob Paauwe
> >
> > The WA specifies that we need to toggle a SDE chicken bit on and then
> > off as the final step in preparation for s0ix entry.
> >
> > Bspec: 33450
> > Bspec: 8402
> >
> > However, something is happening after we toggle the bit that causes
> > the WA to be invalidated. This makes dispcnlunit1_cp_xosc_clkreq
> > active being already in s0ix state i.e SLP_S0 counter incremented.
> > Tweaking the Wa_14010685332 by setting the bit on suspend and clearing
> > it on resume turns down the dispcnlunit1_cp_xosc_clkreq.
> > B.Spec has Documented this tweaked sequence of WA as an alternative.
> > Let keep this tweaked WA for Gen11 platforms and keep untweaked WA for
> > other platforms which never observed this issue.
> >
> > v2 (MattR):
> > - Change the comment on the workaround to give PCH names rather than
> >platform names. Although the bspec is setup to list workarounds by
> >platform, the hardware team has confirmed that the actual issue being
> >worked around here is something that was introduced back in the
> >Cannon Lake PCH and carried forward to subsequent PCH's.
> > - Extend the untweaked version of the workaround to include PCH_CNP as
> >well. Note that since PCH_CNP is used to represent CMP, this will
> >apply on CML and some variants of RKL too.
> > - Cap the untweaked version of the workaround so that it won't apply to
> >"fake" PCH's (i.e., DG1). The issue we're working around really is
> >an issue in the PCH itself, not the South Display, so it shouldn't
> >apply when there isn't a real PCH.
> >
> > Cc: Rodrigo Vivi
> > Signed-off-by: Bob Paauwe
> > Signed-off-by: Anshuman Gupta
> > Signed-off-by: Matt Roper
> > ---
> > .../drm/i915/display/intel_display_power.c| 21 +--
> > drivers/gpu/drm/i915/i915_irq.c | 6 --
> > 2 files changed, 23 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 689922480661..d2a6518329d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -5858,17 +5858,34 @@ static void intel_power_domains_verify_state(struct
> > drm_i915_private *i915)
> >
> > void intel_display_power_suspend_late(struct drm_i915_private *i915)
> > {
> > - if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
> > + u32 val;
> > +
> > + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > bxt_enable_dc9(i915);
> > - else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> > + /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > + if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> > PCH_MCC) {
> > + val = intel_de_read(i915, SOUTH_CHICKEN1);
> > + val |= SBCLK_RUN_REFCLK_DIS;
> > + intel_de_write(i915, SOUTH_CHICKEN1, val);
>
> could we use intel_de_rmw here?
May be i had misunderstod it earlier, i thought it was your recommendation
to use manual read, modify write without using intel_uncore_rmw(),
Was the actual idea to use intel_de_rmw flavour of API instead of
intel_uncore_rmw?
Also would it require to use at original Wa in gen11_display_irq_reset as well?
Thanks,
Anshuman Gupta.
>
> > + }
> > + } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> > hsw_enable_pc8(i915);
> > + }
> > }
> >
> > void intel_display_power_resume_early(struct drm_i915_private *i915)
> > {
> > + u32 val;
> > +
> > if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > gen9_sanitize_dc_state(i915);
> > bxt_disable_dc9(i915);
> > + /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > + if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <=
> > PCH_MCC) {
> > + val = intel_de_read(i915, SOUTH_CHICKEN1);
> > + val &= ~SBCLK_RUN_REFCLK_DIS;
> > + intel_de_write(i915, SOUTH_CHICKEN1, val);
>
> and here?
>
> sorry for not having spotted that sooner.
>
> > + }
> > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> >
Re: [Intel-gfx] [PATCH 1/2] drm/i915/display/tgl: Disable FBC with PSR2
On 2020-11-05 at 01:26:03 +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..32c411414908 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -799,6 +799,12 @@ static bool intel_fbc_can_activate(struct intel_crtc
> *crtc)
> struct intel_fbc *fbc = &dev_priv->fbc;
> struct intel_fbc_state_cache *cache = &fbc->state_cache;
>
> + if (dev_priv->psr.sink_psr2_support &&
> + IS_TIGERLAKE(dev_priv)) {
IMHO we need to use state boolean crtc_state->has_psr2, we can have sink
supports PSR2
but it may not be enabled due to any reason.
Thanks,
Anshuman Gupta.
> + fbc->no_fbc_reason = "not supported with PSR2";
> + return false;
> + }
> +
> if (!intel_fbc_can_enable(dev_priv))
> return false;
>
> --
> 2.26.2
>
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Re: [Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
On 2020-11-05 at 22:09:12 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:00 +0530, Anshuman Gupta wrote:
> > Pass dig_port as an argument to intel_hdcp_init()
> > and intel_hdcp2_init().
> > This will be required for HDCP 2.2 stream encryption.
> >
> > Cc: Ramalingam C
> > Reviewed-by: Uma Shankar
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_hdcp.c| 12 +++-
> > drivers/gpu/drm/i915/display/intel_hdcp.h| 4 +++-
> > drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
> > 4 files changed, 13 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 6dcbfaffd2c5..591b68e5de48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
> > *dig_port,
> > return 0;
> >
> > if (intel_connector->mst_port)
> > - return intel_hdcp_init(intel_connector, port,
> > + return intel_hdcp_init(intel_connector, dig_port,
> cant we retrieve the dig_port from connector?
No, actually intel_hdcp_init get called for DP MST in atomic check phase,
in atomic check phase DP MST connector->encoder is not initialize yet,
it initialize with DP MST encoder in commit phase.
so using intel_attached_dig_port(connector) results in OOPS in
intel_hdcp_init().
Thanks,
Anshuman Gupta.
>
> -Ram
> >&intel_dp_mst_hdcp_shim);
> > else if (!intel_dp_is_edp(intel_dp))
> > - return intel_hdcp_init(intel_connector, port,
> > + return intel_hdcp_init(intel_connector, dig_port,
> >&intel_dp_hdcp_shim);
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 937af4aeaac2..b0f47687bc59 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1982,12 +1982,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
> > transcoder cpu_transcoder)
> > }
> >
> > static int initialize_hdcp_port_data(struct intel_connector *connector,
> > -enum port port,
> > +struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > struct hdcp_port_data *data = &hdcp->port_data;
> > + enum port port = dig_port->base.port;
> >
> > if (INTEL_GEN(dev_priv) < 12)
> > data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> > @@ -2060,14 +2061,15 @@ void intel_hdcp_component_init(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > -static void intel_hdcp2_init(struct intel_connector *connector, enum port
> > port,
> > +static void intel_hdcp2_init(struct intel_connector *connector,
> > +struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > struct intel_hdcp *hdcp = &connector->hdcp;
> > int ret;
> >
> > - ret = initialize_hdcp_port_data(connector, port, shim);
> > + ret = initialize_hdcp_port_data(connector, dig_port, shim);
> > if (ret) {
> > drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> > return;
> > @@ -2077,7 +2079,7 @@ static void intel_hdcp2_init(struct intel_connector
> > *connector, enum port port,
> > }
> >
> > int intel_hdcp_init(struct intel_connector *connector,
> > - enum port port,
> > + struct intel_digital_port *dig_port,
> > const struct intel_hdcp_shim *shim)
> > {
> > struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> > @@ -2088,7 +2090,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> > return -EINVAL;
> >
> > if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> > - intel_hdcp2_init(connector, port, shim);
>
Re: [Intel-gfx] [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link
On 2020-11-05 at 22:15:37 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:05 +0530, Anshuman Gupta wrote:
> > This requires for HDCP 2.2 MST check link.
> >
> > Cc: Ramalingam C
> > Reviewed-by: Uma Shankar
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> > 4 files changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 24e0067c2e7c..dfb5be64e03a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -375,7 +375,8 @@ struct intel_hdcp_shim {
> > bool is_repeater, u8 type);
> >
> > /* HDCP2.2 Link Integrity Check */
> > - int (*check_2_2_link)(struct intel_digital_port *dig_port);
> > + int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector);
> do we need both of them?
I have followed the HDCP 1.4 check_link signature.
https://patchwork.freedesktop.org/patch/386157/?series=78749&rev=3
We need connector for QSES check, we can't retrieve DP MST connector from
dig_port.
Thanks,
Anshuman
>
> -Ram.
> > };
> >
> > struct intel_hdcp {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 591b68e5de48..4be61e7fde4e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct
> > intel_digital_port *dig_port,
> > }
> >
> > static
> > -int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
> > +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > u8 rx_status;
> > int ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 1df6d4a23476..87f7aaf3a319 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -1940,7 +1940,7 @@ static int intel_hdcp2_check_link(struct
> > intel_connector *connector)
> > goto out;
> > }
> >
> > - ret = hdcp->shim->check_2_2_link(dig_port);
> > + ret = hdcp->shim->check_2_2_link(dig_port, connector);
> > if (ret == HDCP_LINK_PROTECTED) {
> > if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> > intel_hdcp_update_value(connector,
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > index 0788de04711b..bd0d91101464 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> > @@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct
> > intel_digital_port *dig_port,
> > }
> >
> > static
> > -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
> > +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
> > + struct intel_connector *connector)
> > {
> > u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
> > int ret;
> > --
> > 2.26.2
> >
___
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Re: [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support
On 2020-11-05 at 21:04:03 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:58 +0530, Anshuman Gupta wrote:
> > Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
> > in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
> > encryption over DP MST Transport Link.
> >
> > HDCP 1.4 stream encryption requires to validate the stream encryption
> > status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
> > in order to enable/disable the stream encryption.
> >
> > Both of above requirement are same for all Gen with respect to
> > B.Spec Documentation.
> >
> > v2:
> > Cosmetic changes function name, error msg print and
> > stream typo fixes. [Uma]
> >
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
> > drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
> > .../drm/i915/display/intel_display_types.h| 4 +
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ---
> > drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 6 files changed, 90 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 9fce623e951e..779603a38cfc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct
> > intel_crtc_state *crtc_state
> > }
> > }
> >
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > -enum transcoder cpu_transcoder,
> > -bool enable)
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask)
> > {
> > struct drm_device *dev = intel_encoder->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct
> > intel_encoder *intel_encoder,
> >
> > tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > if (enable)
> > - tmp |= TRANS_DDI_HDCP_SIGNALLING;
> > + tmp |= hdcp_mask;
> > else
> > - tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
> > + tmp &= ~hdcp_mask;
> > intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
> > intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
> > return ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h
> > b/drivers/gpu/drm/i915/display/intel_ddi.h
> > index dcc711cfe4fe..a4dd815c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> > @@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > u32 ddi_signal_levels(struct intel_dp *intel_dp,
> > const struct intel_crtc_state *crtc_state);
> > -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
> > -enum transcoder cpu_transcoder,
> > -bool enable);
> > +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
> > + enum transcoder cpu_transcoder,
> > + bool enable, u32 hdcp_mask);
> > void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> >
> > #endif /* __INTEL_DDI_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c47124a679b6..59b8fc21e3e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -339,6 +339,10 @@ struct intel_hdcp_shim {
> > enum transcoder cpu_transcoder,
> > bool enable);
> >
> > + /* Enable/Disable stream encryption on DP MST Transport Link */
> > + int (*stream_encryption)(struct intel_digital_port *dig_port,
> > +bool enable);
> > +
> > /* Ensures the link is still protected */
> > bool (*check_link)(struct intel_digit
Re: [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data
On 2020-11-05 at 22:04:15 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:12:04 +0530, Anshuman Gupta wrote:
> > Add support for multiple mst stream in hdcp port data
> > which will be used by RepeaterAuthStreamManage msg and
> > HDCP 2.2 security f/w for m' validation.
> >
> > v2:
> > Init the hdcp port data k for HDMI/DP SST strem.
> >
> > v3:
> > Cosmetic changes. [Uma]
> >
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > .../drm/i915/display/intel_display_types.h| 4 +-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 103 +++---
> > 2 files changed, 92 insertions(+), 15 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 749c3a7e0b45..24e0067c2e7c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1445,10 +1445,12 @@ struct intel_digital_port {
> > enum phy_fia tc_phy_fia;
> > u8 tc_phy_fia_idx;
> >
> > - /* protects num_hdcp_streams reference count, port_data */
> > + /* protects num_hdcp_streams reference count, port_data and port_auth */
> > struct mutex hdcp_mutex;
> > /* the number of pipes using HDCP signalling out of this port */
> > unsigned int num_hdcp_streams;
> > + /* port HDCP auth status */
> > + bool port_auth;
> > /* HDCP port data need to pass to security f/w */
> > struct hdcp_port_data port_data;
> since this is no more in hdcp related struct, it will be better to be named as
> hdcp_auth_status and hdcp_port_data !?
sure i will do this chnage.
Thanks,
Anshuman Gupta.
>
> -Ram
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index a5ec4f72f50f..1df6d4a23476 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -26,6 +26,64 @@
> > #define KEY_LOAD_TRIES 5
> > #define HDCP2_LC_RETRY_CNT 3
> >
> > +static int intel_conn_to_vcpi(struct intel_connector *connector)
> > +{
> > + /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
> > + return connector->port ? connector->port->vcpi.vcpi : 0;
> > +}
> > +
> > +static int
> > +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
> > +{
> > + struct drm_connector_list_iter conn_iter;
> > + struct intel_digital_port *conn_dig_port;
> > + struct intel_connector *connector;
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + struct hdcp_port_data *data = &dig_port->port_data;
> > + bool enforce_type0 = false;
> > + int k;
> > +
> > + if (dig_port->port_auth)
> > + return 0;
> > +
> > + drm_connector_list_iter_begin(&i915->drm, &conn_iter);
> > + for_each_intel_connector_iter(connector, &conn_iter) {
> > + if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
> > + continue;
> > +
> > + conn_dig_port = intel_attached_dig_port(connector);
> > + if (conn_dig_port != dig_port)
> > + continue;
> > +
> > + if (connector->base.status == connector_status_disconnected)
> > + continue;
> > +
> > + if (!enforce_type0 && !intel_hdcp2_capable(connector))
> > + enforce_type0 = true;
> > +
> > + data->streams[data->k].stream_id =
> > intel_conn_to_vcpi(connector);
> > + data->k++;
> > +
> > + /* if there is only one active stream */
> > + if (dig_port->dp.active_mst_links <= 1)
> > + break;
> > + }
> > + drm_connector_list_iter_end(&conn_iter);
> > +
> > + if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k
> > == 0))
> > + return -EINVAL;
> > +
> > + /*
> > +* Apply common protection level across all streams in DP MST Topology.
> > +* Use highest supported content type for all streams in DP MST
> > Topology.
> > +*/
> > + for (k = 0; k < data->k; k++)
> > + data->streams[k].stream_type =
> > + enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 :
> > DRM_MODE_HDC
Re: [Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
On 2020-11-05 at 21:11:52 +0530, Ramalingam C wrote:
> On 2020-10-27 at 22:11:59 +0530, Anshuman Gupta wrote:
> > Enable HDCP 1.4 over DP MST for Gen12.
> > This also enable the stream encryption support for
> > older generations, which was missing earlier.
> It will be nice to have them in separate patches.
Thanks for review comment.
Sure i will refactor a separate patch for this.
Thanks,
Anshuman Gupta
>
> -Ram
> >
> > v2:
> > - Added debug print for stream encryption.
> > - Disable the hdcp on port after disabling last stream
> > encryption.
> > v3:
> > - Cosmetic change, removed the value less comment. [Uma]
> >
> > Cc: Ramalingam C
> > Signed-off-by: Anshuman Gupta
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 43 ++---
> > 2 files changed, 32 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 16865b200062..f00e12fc83e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -826,13 +826,9 @@ static struct drm_connector
> > *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> > intel_attach_force_audio_property(connector);
> > intel_attach_broadcast_rgb_property(connector);
> >
> > -
> > - /* TODO: Figure out how to make HDCP work on GEN12+ */
> > - if (INTEL_GEN(dev_priv) < 12) {
> > - ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > - if (ret)
> > - DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> > - }
> > + ret = intel_dp_init_hdcp(dig_port, intel_connector);
> > + if (ret)
> > + drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
> >
> > /*
> > * Reuse the prop from the SST connector because we're
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 0322a83c151d..937af4aeaac2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector
> > *connector)
> > return ret;
> > }
> >
> > -/* Implements Part 1 of the HDCP authorization procedure */
> > +/*
> > + * Implements Part 1 of the HDCP authorization procedure.
> > + * Authentication Part 1 steps for Multi-stream DisplayPort.
> > + * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
> > + * Step 2. Enable encryption for each stream that requires encryption.
> > + */
> > static int intel_hdcp_auth(struct intel_connector *connector)
> > {
> > struct intel_digital_port *dig_port =
> > intel_attached_dig_port(connector);
> > @@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector
> > *connector)
> > return -ETIMEDOUT;
> > }
> >
> > - /*
> > -* XXX: If we have MST-connected devices, we need to enable encryption
> > -* on those as well.
> > -*/
> > + /* DP MST Auth Part 1 Step 2.a and Step 2.b */
> > + if (shim->stream_encryption) {
> > + ret = shim->stream_encryption(dig_port, true);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4
> > stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream
> > encrypted\n",
> > + transcoder_name(hdcp->stream_transcoder));
> > + }
> >
> > if (repeater_present)
> > return intel_hdcp_auth_downstream(connector);
> > @@ -791,18 +802,22 @@ static int _intel_hdcp_disable(struct intel_connector
> > *connector)
> > drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
> > connector->base.name, connector->base.base.id);
> >
> > + if (hdcp->shim->stream_encryption) {
> > + ret = hdcp->shim->stream_encryption(dig_port, false);
> > + if (ret) {
> > + drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4
> > stream enc\n");
> > + return ret;
> > + }
> > + drm_dbg_kms(&dev_pr
Re: [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
On 2020-11-06 at 16:42:21 +0530, Ramalingam C wrote:
> On 2020-11-06 at 14:57:25 +0530, Ramalingam C wrote:
> > On 2020-11-03 at 11:57:00 +0530, Anshuman Gupta wrote:
> > > Add support for HDCP 2.2 DP MST shim callback.
> > > This adds existing DP HDCP shim callback for Link Authentication
> > > and Encryption and HDCP 2.2 stream encryption
> > > callback.
> > >
> > > v2:
> > > Added a WARN_ON() instead of drm_err. [Uma]
> > > Cosmetic changes. [Uma]
> >
> > Reviewed-by: Ramalingam C
> I think we can improvise further here.
>
> > >
> > > Cc: Ramalingam C
> > > Reviewed-by: Uma Shankar
> > > Signed-off-by: Anshuman Gupta
> > > ---
> > > .../drm/i915/display/intel_display_types.h| 4 +
> > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 +--
> > > 2 files changed, 76 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index dfb5be64e03a..4cbb151ff3cf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -374,6 +374,10 @@ struct intel_hdcp_shim {
> > > int (*config_stream_type)(struct intel_digital_port *dig_port,
> > > bool is_repeater, u8 type);
> > >
> > > + /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
> > > + int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
> > > + bool enable);
> > > +
> > > /* HDCP2.2 Link Integrity Check */
> > > int (*check_2_2_link)(struct intel_digital_port *dig_port,
> > > struct intel_connector *connector);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > index 4be61e7fde4e..35c1543fe0e2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > > @@ -698,18 +698,14 @@ intel_dp_mst_hdcp_stream_encryption(struct
> > > intel_digital_port *dig_port,
> > > return 0;
> > > }
> > >
> > > -static
> > > -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > - struct intel_connector *connector)
> > > +static bool intel_dp_mst_get_qses_status(struct intel_digital_port
> > > *dig_port,
> > > + struct intel_connector *connector)
> > > {
> > > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > - struct intel_dp *intel_dp = &dig_port->dp;
> > > struct drm_dp_query_stream_enc_status_ack_reply reply;
> > > + struct intel_dp *intel_dp = &dig_port->dp;
> > > int ret;
> > >
> > > - if (!intel_dp_hdcp_check_link(dig_port, connector))
> > > - return false;
> > > -
> > > ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> > > connector->port, &reply);
> > > if (ret) {
> > > @@ -722,6 +718,69 @@ bool intel_dp_mst_hdcp_check_link(struct
> > > intel_digital_port *dig_port,
> > > return reply.auth_completed && reply.encryption_enabled;
> > > }
> > >
> > > +static
> > > +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
> > > + struct intel_connector *connector)
> > > +{
> > > + if (!intel_dp_hdcp_check_link(dig_port, connector))
> > > + return false;
> > > +
> > > + return intel_dp_mst_get_qses_status(dig_port, connector);
> > > +}
> > > +
> > > +static int
> > > +intel_dp_mst_hdcp2_stream_encryption(struct intel_digital_port *dig_port,
> > > + bool enable)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > > + struct hdcp_port_data *data = &dig_port->port_data;
> > > + struct intel_dp *dp = &dig_port->dp;
> > > + struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> > > + enum port port = dig_port->base.port;
> > > + /* HDCP2.x register uses stream transcoder */
> > > + enum transcoder cpu_transcoder = hdcp-&g
Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support
On 2020-05-05 at 19:09:54 +0300, Imre Deak wrote: > On Tue, May 05, 2020 at 07:39:04AM -0700, Matt Roper wrote: > > On Tue, May 05, 2020 at 10:20:58AM +0530, Anshuman Gupta wrote: > > > On 2020-05-04 at 15:52:13 -0700, Matt Roper wrote: > > > > RKL power wells are similar to TGL power wells, but have some important > > > > differences: > > > > > > > > * PG1 now has pipe A's VDSC (rather than sticking it in PG2) > > > > * PG2 no longer exists > > > > * DDI-C (aka TC-1) moves from PG1 -> PG3 > > > > * PG5 no longer exists due to the lack of a fourth pipe > > > > > > > > Also note that what we refer to as 'DDI-C' and 'DDI-D' need to actually > > > > be programmed as TC-1 and TC-2 even though this platform doesn't have TC > > > > outputs. Looks good to me. Reviewed-by: Anshuman Gupta > > > > > > > > Bspec: 49234 > > > > Cc: Imre Deak > > > > Cc: Lucas De Marchi > > > > Cc: Anshuman Gupta > > > > Signed-off-by: Matt Roper > > > > --- > > > > .../drm/i915/display/intel_display_power.c| 185 +- > > > > drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +- > > > > 2 files changed, 186 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c > > > > b/drivers/gpu/drm/i915/display/intel_display_power.c > > > > index 49998906cc61..71691919d101 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > > > > @@ -2913,6 +2913,53 @@ void intel_display_power_put(struct > > > > drm_i915_private *dev_priv, > > > > BIT_ULL(POWER_DOMAIN_AUX_I_TBT) | \ > > > > BIT_ULL(POWER_DOMAIN_TC_COLD_OFF)) > > > > > > > > +#define RKL_PW_4_POWER_DOMAINS ( \ > > > > + BIT_ULL(POWER_DOMAIN_PIPE_C) | \ > > > > + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ > > > > + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |\ > > > > + BIT_ULL(POWER_DOMAIN_INIT)) > > > > + > > > > +#define RKL_PW_3_POWER_DOMAINS ( \ > > > > + RKL_PW_4_POWER_DOMAINS |\ > > > > + BIT_ULL(POWER_DOMAIN_PIPE_B) | \ > > > > + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ > > > > + BIT_ULL(POWER_DOMAIN_AUDIO) | \ > > > > + BIT_ULL(POWER_DOMAIN_VGA) | \ > > > > + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |\ > > > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |\ > > > > + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |\ > > > > + BIT_ULL(POWER_DOMAIN_AUX_D) | \ > > > > + BIT_ULL(POWER_DOMAIN_AUX_E) | \ > > > > + BIT_ULL(POWER_DOMAIN_INIT)) > > > > + > > > > +/* > > > > + * There is no PW_2/PG_2 on RKL. > > > > + * > > > > + * RKL PW_1/PG_1 domains (under HW/DMC control): > > > > + * - DBUF function (note: registers are in PW0) > > > > + * - PIPE_A and its planes and VDSC/joining, except VGA > > > > + * - transcoder A > > > > + * - DDI_A and DDI_B > > > > + * - FBC > > > > + * > > > > + * RKL PW_0/PG_0 domains (under HW/DMC control): > > > > + * - PCI > > > > + * - clocks except port PLL > > > > + * - shared functions: > > > > + * * interrupts except pipe interrupts > > > > + * * MBus except PIPE_MBUS_DBOX_CTL > > > > + * * DBUF registers > > > > + * - central power except FBC > > > > + * - top-level GTC (DDI-level GTC is in the well associated with the > > > > DDI) > > > > + */ > > > > + > > > > +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ > > > > + RKL_PW_3_POWER_DOMAINS |\ > > > > + BIT_ULL(POWER_DOMAIN_MODESET) | \ > > > > + BIT_ULL(POWER_DOMAIN_AUX_A) | \ > > > > + BIT_ULL(POWER_DOMAIN_AUX_B) | \ > > > > + BIT_ULL(POWER_DOMAIN_INIT)) > > > > + &g
[Intel-gfx] [PATCH 1/2] drm/i915/hdcp: Add update_pipe early return
Currently intel_hdcp_update_pipe() is also getting called for non-hdcp connectors and got though its conditional code flow, which is completely unnecessary for non-hdcp connectors, therefore it make sense to have an early return. No functional change. Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..d0a2bee9035a 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2079,11 +2079,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_hdcp *hdcp = &connector->hdcp; - bool content_protection_type_changed = + bool content_protection_type_changed; + + if (!connector->hdcp.shim) + return; + + content_protection_type_changed = (conn_state->hdcp_content_type != hdcp->content_type && conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED); - /* * During the HDCP encryption session if Type change is requested, * disable the HDCP and reenable it with new TYPE value. -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/2] HDCP minor refactoring
No functional change. Anshuman Gupta (2): drm/i915/hdcp: Add update_pipe early return drm/i915/hdcp: No direct access to power_well desc drivers/gpu/drm/i915/display/intel_hdcp.c | 24 ++- 1 file changed, 10 insertions(+), 14 deletions(-) -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/hdcp: No direct access to power_well desc
HDCP code doesn't require to access power_well internal stuff,
instead it should use the intel_display_power_well_is_enabled()
to get the status of desired power_well.
No functional change.
Cc: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d0a2bee9035a..409bd5d98a81 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -148,9 +148,8 @@ static int intel_hdcp_poll_ksv_fifo(struct
intel_digital_port *intel_dig_port,
static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
- struct i915_power_well *power_well;
enum i915_power_well_id id;
+ intel_wakeref_t wakeref;
bool enabled = false;
/*
@@ -162,17 +161,10 @@ static bool hdcp_key_loadable(struct drm_i915_private
*dev_priv)
else
id = SKL_DISP_PW_1;
- mutex_lock(&power_domains->lock);
-
/* PG1 (power well #1) needs to be enabled */
- for_each_power_well(dev_priv, power_well) {
- if (power_well->desc->id == id) {
- enabled = power_well->desc->ops->is_enabled(dev_priv,
- power_well);
- break;
- }
- }
- mutex_unlock(&power_domains->lock);
+ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+ enabled = intel_display_power_well_is_enabled(dev_priv, id);
+ intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
/*
* Another req for hdcp key loadability is enabled state of pll for
--
2.26.0
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[Intel-gfx] [PATCH v2] drm/i915/hdcp: Update CP as per the kernel internal state
Content Protection property should be updated as per the kernel
internal state. Let's say if Content protection is disabled
by userspace, CP property should be set to UNDESIRED so that
reauthentication will not happen until userspace request it again,
but when kernel disables the HDCP due to any DDI disabling sequences
like modeset/DPMS operation, kernel should set the property to
DESIRED, so that when opportunity arises, kernel will start the
HDCP authentication on its own.
Somewhere in the line, state machine to set content protection to
DESIRED from kernel was broken and IGT coverage was missing for it.
This patch fixes it.
v2:
- Fixing hdcp CP state in intel_hdcp_atomic_check(), that will
require to check hdcp->value in intel_hdcp_update_pipe() in order
to avoid enabling hdcp, if it was already enabled.
Cc: Ramalingam C
Cc: Maarten Lankhorst
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1
Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 2cbc4619b4ce..f90f48819838 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2083,6 +2083,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
(conn_state->hdcp_content_type != hdcp->content_type &&
conn_state->content_protection !=
DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
+ bool desired_and_not_enabled = false;
/*
* During the HDCP encryption session if Type change is requested,
@@ -2105,8 +2106,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
}
if (conn_state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_DESIRED ||
- content_protection_type_changed)
+ DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+ mutex_lock(&hdcp->mutex);
+ /* Avoid enabling hdcp, if it already ENABLED */
+ desired_and_not_enabled =
+ hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ mutex_unlock(&hdcp->mutex);
+ }
+
+ if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
crtc_state->cpu_transcoder,
(u8)conn_state->hdcp_content_type);
@@ -2155,6 +2163,19 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
return;
}
+ crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
+ new_state->crtc);
+ /*
+* Fix the HDCP uapi content protection state in case of modeset.
+* FIXME: As per HDCP content protection property uapi doc, an uevent()
+* need to be sent if there is transition from ENABLED->DESIRED.
+*/
+ if (drm_atomic_crtc_needs_modeset(crtc_state) &&
+ (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+ new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
+ new_state->content_protection =
+ DRM_MODE_CONTENT_PROTECTION_DESIRED;
+
/*
* Nothing to do if the state didn't change, or HDCP was activated since
* the last commit. And also no change in hdcp content type.
@@ -2167,8 +2188,6 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
return;
}
- crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
- new_state->crtc);
crtc_state->mode_changed = true;
}
--
2.26.0
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Re: [Intel-gfx] [PATCH v2] drm/i915/hdcp: Update CP as per the kernel internal state
On 2020-05-15 at 07:56:25 +0100, Chris Wilson wrote: > Quoting Anshuman Gupta (2020-05-15 07:10:29) > > Somewhere in the line, state machine to set content protection to > > DESIRED from kernel was broken and IGT coverage was missing for it. > > This patch fixes it. > > It's strange that you mention IGT, since what tests being run by CI > never pass and have not been fixed for several months. As well as the Actually IGT fix for the coverge was worked upon after discovering this issue. https://patchwork.freedesktop.org/patch/349542/?series=72264&rev=1 above patch requires to merge after kernel patch. > sporadic HDCP failures affecting unrelated tests, which have not > appeared to have received any attention either. This bug was not failing any igt subtest, as igt test coverage was missing, content protection igt test were passing. Thanks, Anshuman. > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drm/i915/hdcp: Update CP as per the kernel internal state
On 2020-05-15 at 11:40:29 +0530, Anshuman Gupta wrote:
> Content Protection property should be updated as per the kernel
> internal state. Let's say if Content protection is disabled
> by userspace, CP property should be set to UNDESIRED so that
> reauthentication will not happen until userspace request it again,
> but when kernel disables the HDCP due to any DDI disabling sequences
> like modeset/DPMS operation, kernel should set the property to
> DESIRED, so that when opportunity arises, kernel will start the
> HDCP authentication on its own.
>
> Somewhere in the line, state machine to set content protection to
> DESIRED from kernel was broken and IGT coverage was missing for it.
> This patch fixes it.
>
> v2:
> - Fixing hdcp CP state in intel_hdcp_atomic_check(), that will
> require to check hdcp->value in intel_hdcp_update_pipe() in order
> to avoid enabling hdcp, if it was already enabled.
>
> Cc: Ramalingam C
> Cc: Maarten Lankhorst
> Reviewed-by: Uma Shankar
> Signed-off-by: Anshuman Gupta
> Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1
> Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2
Ram, Daniel, Jani,
Above patch fixes HDCP uapi broken state.
Could you please provide your inputs , is it ok to merges this patch in current
form.
Thanks,
Anshuman Gupta.
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++
> 1 file changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2cbc4619b4ce..f90f48819838 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2083,6 +2083,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
> *state,
> (conn_state->hdcp_content_type != hdcp->content_type &&
>conn_state->content_protection !=
>DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
> + bool desired_and_not_enabled = false;
>
> /*
>* During the HDCP encryption session if Type change is requested,
> @@ -2105,8 +2106,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
> *state,
> }
>
> if (conn_state->content_protection ==
> - DRM_MODE_CONTENT_PROTECTION_DESIRED ||
> - content_protection_type_changed)
> + DRM_MODE_CONTENT_PROTECTION_DESIRED) {
> + mutex_lock(&hdcp->mutex);
> + /* Avoid enabling hdcp, if it already ENABLED */
> + desired_and_not_enabled =
> + hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
> + mutex_unlock(&hdcp->mutex);
> + }
> +
> + if (desired_and_not_enabled || content_protection_type_changed)
> intel_hdcp_enable(connector,
> crtc_state->cpu_transcoder,
> (u8)conn_state->hdcp_content_type);
> @@ -2155,6 +2163,19 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
> return;
> }
>
> + crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
> +new_state->crtc);
> + /*
> + * Fix the HDCP uapi content protection state in case of modeset.
> + * FIXME: As per HDCP content protection property uapi doc, an uevent()
> + * need to be sent if there is transition from ENABLED->DESIRED.
> + */
> + if (drm_atomic_crtc_needs_modeset(crtc_state) &&
> + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
> + new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
> + new_state->content_protection =
> + DRM_MODE_CONTENT_PROTECTION_DESIRED;
> +
> /*
>* Nothing to do if the state didn't change, or HDCP was activated since
>* the last commit. And also no change in hdcp content type.
> @@ -2167,8 +2188,6 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
> return;
> }
>
> - crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
> -new_state->crtc);
> crtc_state->mode_changed = true;
> }
>
> --
> 2.26.0
>
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[Intel-gfx] [PATCH v2 1/2] drm/i915/hdcp: Add update_pipe early return
Currently intel_hdcp_update_pipe() is also getting called for non-hdcp connectors and get through its conditional code flow, which is completely unnecessary for non-hdcp connectors, therefore it make sense to have an early return. No functional change. Reviewed-by: Uma Shankar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 2cbc4619b4ce..d0a2bee9035a 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2079,11 +2079,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_hdcp *hdcp = &connector->hdcp; - bool content_protection_type_changed = + bool content_protection_type_changed; + + if (!connector->hdcp.shim) + return; + + content_protection_type_changed = (conn_state->hdcp_content_type != hdcp->content_type && conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED); - /* * During the HDCP encryption session if Type change is requested, * disable the HDCP and reenable it with new TYPE value. -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 0/2] HDCP minor refactoring
No functional change. Anshuman Gupta (2): drm/i915/hdcp: Add update_pipe early return drm/i915/hdcp: No direct access to power_well desc drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) -- 2.26.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915/hdcp: No direct access to power_well desc
HDCP code doesn't require to access power_well internal stuff,
instead it should use the intel_display_power_well_is_enabled()
to get the status of desired power_well.
No functional change.
v2:
- used with_intel_runtime_pm instead of get/put. [Jani]
Cc: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d0a2bee9035a..77436a22361b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -148,9 +148,8 @@ static int intel_hdcp_poll_ksv_fifo(struct
intel_digital_port *intel_dig_port,
static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
- struct i915_power_well *power_well;
enum i915_power_well_id id;
+ intel_wakeref_t wakeref;
bool enabled = false;
/*
@@ -162,17 +161,9 @@ static bool hdcp_key_loadable(struct drm_i915_private
*dev_priv)
else
id = SKL_DISP_PW_1;
- mutex_lock(&power_domains->lock);
-
/* PG1 (power well #1) needs to be enabled */
- for_each_power_well(dev_priv, power_well) {
- if (power_well->desc->id == id) {
- enabled = power_well->desc->ops->is_enabled(dev_priv,
- power_well);
- break;
- }
- }
- mutex_unlock(&power_domains->lock);
+ with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
+ enabled = intel_display_power_well_is_enabled(dev_priv, id);
/*
* Another req for hdcp key loadability is enabled state of pll for
--
2.26.0
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Re: [Intel-gfx] [PATCH] drm/i915/hdcp: Avoid duplicate HDCP enables
On 2020-05-21 at 10:27:21 +0530, Ramalingam C wrote:
> On 2020-05-20 at 15:47:44 -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > If userspace sets the CP property to DESIRED while it's already ENABLED,
> > the driver will try to re-enable HDCP. On some displays, this will
> > result in R0' mismatches. I'm guessing this is because the display is
> > still sending back Ri instead of re-authenticating.
> >
> > At any rate, we can fix this inefficiency easily enough by just nooping
> > the DESIRED property set if HDCP is already ENABLED.
AFAIU may below patch also solves above issue implicitly.
https://patchwork.freedesktop.org/patch/365758/?series=72251&rev=4
Besides that +1 for below Ram comment, it would be better if such type of
duplicate
enable request should filter by drm_atomic_connector_set_property().
Thanks,
Anshuman Gupta.
> Sean,
>
> This will skip the hdcp enable.
>
> But at present too we will be getting below WARN_ON from intel_hdcp_enable,
> to indicate userspace is going wrong with request.
> drm_WARN_ON(&dev_priv->drm,
> hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
>
> And if we need to filter this out, could we validate the incoming hdcp
> request at
> drm_atomic_connector_set_property() itself? No point in going into the
> atomic commit without a valid request. something like
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index a1e5e262bae2..d98b2eeae78d 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -746,6 +746,12 @@ static int drm_atomic_connector_set_property(struct
> drm_connector *connector,
> DRM_DEBUG_KMS("only drivers can set CP Enabled\n");
> return -EINVAL;
> }
> + if (config->content_protection_property ==
> + DRM_MODE_CONTENT_PROTECTION_ENABLED &&
> + val == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
> + DRM_DEBUG_KMS("Redundant req for content
> protection\n");
> + return -EINVAL;
> + }
> state->content_protection = val;
> } else if (property == config->hdcp_content_type_property) {
> state->hdcp_content_type = val;
>
> -Ram
>
> >
> > Signed-off-by: Sean Paul
> > ---
> >
> > I suspect this is the actual root cause I was chasing with
> > "drm/i915/hdcp: Add additional R0' wait". I was able to reproduce the
> > R0` messages by marking HDCP desired while it was already enabled. This
> > _should_ work, but it seems like some displays handle it more graciously
> > than others.
> >
> >
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 10 +++---
> > 1 file changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index 2cbc4619b4ce..f770fe0c5595 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -2156,12 +2156,16 @@ void intel_hdcp_atomic_check(struct drm_connector
> > *connector,
> > }
> >
> > /*
> > -* Nothing to do if the state didn't change, or HDCP was activated since
> > -* the last commit. And also no change in hdcp content type.
> > +* Nothing to do if content type is unchanged and one of:
> > +* - state didn't change
> > +* - HDCP was activated since the last commit
> > +* - attempting to set to desired while already enabled
> > */
> > if (old_cp == new_cp ||
> > (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
> > -new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) {
> > +new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) ||
> > + (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
> > +new_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED)) {
> > if (old_state->hdcp_content_type ==
> > new_state->hdcp_content_type)
> > return;
> > --
> > Sean Paul, Software Engineer, Google / Chromium OS
> >
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[Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs
Gen12 hw are failing to enable lpsp configuration due to PG3 was left on due to valid usgae count of POWER_DOMAIN_AUDIO. It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling a crtc, it should be always i915_audio_component request to get/put AUDIO_POWER_DOMAIN. Cc: sta...@vger.kernel.org Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_display.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 6c3b11de2daf..f31a579d7a52 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) mask |= BIT_ULL(intel_encoder->power_domain); } - if (HAS_DDI(dev_priv) && crtc_state->has_audio) + /* +* Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to +* enable AUDIO power in order to enable a crtc. +*/ + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && crtc_state->has_audio) mask |= BIT_ULL(POWER_DOMAIN_AUDIO); if (crtc_state->shared_dpll) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs
On 2020-06-01 at 18:19:44 +0530, Shankar, Uma wrote: > > > > -Original Message- > > From: Intel-gfx On Behalf Of > > Anshuman Gupta > > Sent: Monday, June 1, 2020 3:45 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: sta...@vger.kernel.org > > Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs > > > > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on > > due to > > valid usgae count of POWER_DOMAIN_AUDIO. > > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling a crtc, > > it should be always i915_audio_component request to get/put > > AUDIO_POWER_DOMAIN. > > > > Cc: sta...@vger.kernel.org > > Cc: Ville Syrjälä > > Cc: Maarten Lankhorst > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 6 +- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 6c3b11de2daf..f31a579d7a52 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct > > intel_crtc_state *crtc_state) > > mask |= BIT_ULL(intel_encoder->power_domain); > > } > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > + /* > > +* Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > > +* enable AUDIO power in order to enable a crtc. > > +*/ > > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && > > +crtc_state->has_audio) > > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > As part of ddi_get_config we determine has_audio using power well enabled: > pipe_config->has_audio = > intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); IMO AUDIO power will also be requested by i915_audio_component get request, we can always use HDMI display without audio playback, AUDIO power should be enabled when audio driver request for it. if we get AUDIO_POWER_DOMAIN while enabling crtc PG3 will always kept on till CRTC is disabled, that is the issue required to be addressed here. This is just RFC to initiate a discussion around it. Thanks, Anshuman Gupta. > > If audio power domain is not enabled, we may end up with this as false. > Later this may get checked in intel_enable_ddi_hdmi to call audio codec enable > > if (crtc_state->has_audio) > intel_audio_codec_enable(encoder, crtc_state, conn_state); > > This may cause detection to fail. Please verify this usecase once and confirm. > > Regards, > Uma Shankar > > > if (crtc_state->shared_dpll) > > -- > > 2.26.2 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs
On 2020-06-01 at 17:11:32 +0300, Ville Syrjälä wrote: > On Mon, Jun 01, 2020 at 03:45:16PM +0530, Anshuman Gupta wrote: > > Gen12 hw are failing to enable lpsp configuration due to PG3 was left on > > due to valid usgae count of POWER_DOMAIN_AUDIO. > > It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling > > a crtc, it should be always i915_audio_component request to get/put > > AUDIO_POWER_DOMAIN. > > > > Cc: sta...@vger.kernel.org > > Cc: Ville Syrjälä > > Cc: Maarten Lankhorst > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 6 +- > > 1 file changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 6c3b11de2daf..f31a579d7a52 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7356,7 +7356,11 @@ static u64 get_crtc_power_domains(struct > > intel_crtc_state *crtc_state) > > mask |= BIT_ULL(intel_encoder->power_domain); > > } > > > > - if (HAS_DDI(dev_priv) && crtc_state->has_audio) > > + /* > > +* Gen12 can drive lpsp on hdmi/dp outpus, it doesn't require to > > +* enable AUDIO power in order to enable a crtc > > Nothing requires audio power to enable a crtc. What this is saying is > that if we want audio then we must enable the audio power. If you > didn't want audio then you wouldn't have .has_audio set. IMO i915_audio_component_get_power also enables audio power, and i915_audio_component_put_power releases the usage count based upon audio runtime idleness but here get_crtc_power_domains() gets the POWER_DOMAIN_AUDIO usages count, which will be released only when this crtc get disbaled. It may enable AUDIO power despite of fact that audio driver has released the usage count. Please correct me if i am wrong here. > > That said, looks like audio is moving into the always on well, but not > yet in tgl. Still some of audio functional stuff lies in PG3, not completely removed from PG3. Thanks, Anshuman Gupta. > > . > > +*/ > > + if (INTEL_GEN(dev_priv) < 12 && HAS_DDI(dev_priv) && > > crtc_state->has_audio) > > mask |= BIT_ULL(POWER_DOMAIN_AUDIO); > > > > if (crtc_state->shared_dpll) > > -- > > 2.26.2 > > -- > Ville Syrjälä > Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add support for considering HDCP ver requested via debugfs
On 2020-06-08 at 15:31:02 +0530, Ankit Nautiyal wrote:
> For testing and debugging each HDCP version separately, a debugfs
> entry for requesting a specific version is required. The version
> requested via debugfs needs to be stored in hdcp structure. This can
> then be considered while enabling HDCP, provided the platform and the
> display supports the requested version.
>
> This patch adds the support for storing the version requested as a 32bit
> flag. It also adds a helper function to check if a version is requested.
>
> If a specific HDCP version is requested through the debugfs, the driver
> chooses that version, instead of policy of choosing the highest HDCP
> version supported.
>
> v2: Initialize debugfs_ver_request flag with 0. (Jani Nikula)
>
> Signed-off-by: Ankit Nautiyal
> ---
> .../gpu/drm/i915/display/intel_display_types.h | 10 ++
> drivers/gpu/drm/i915/display/intel_hdcp.c| 16 ++--
> 2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9488449e4b94..cfa641c70717 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -408,6 +408,16 @@ struct intel_hdcp {
>* Hence caching the transcoder here.
>*/
> enum transcoder cpu_transcoder;
> +
> + /*
> + * HDCP version requested from debugfs i915_hdcp_ver_request.
> + * Kernel will read these bits and entertain the request, as per
> + * the HDCP capability of the panel and platform.
> + */
> +#define HDCP_VERSION_1_4 0x01
> +#define HDCP_VERSION_2_2 0x02
> +#define HDCP_VERSION_MASK0x03
> + u32 debugfs_ver_request;
> };
>
> struct intel_connector {
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 2cbc4619b4ce..a21ea9c2e9a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1977,6 +1977,8 @@ int intel_hdcp_init(struct intel_connector *connector,
> if (!shim)
> return -EINVAL;
>
> + hdcp->debugfs_ver_request = 0;
> +
> if (is_hdcp2_supported(dev_priv))
> intel_hdcp2_init(connector, shim);
>
> @@ -1998,6 +2000,14 @@ int intel_hdcp_init(struct intel_connector *connector,
> return 0;
> }
>
> +static bool hdcp_debugfs_requested(struct intel_hdcp *hdcp, u32 hdcp_version)
> +{
> + if (!hdcp->debugfs_ver_request)
> + return true;
> +
> + return hdcp->debugfs_ver_request & hdcp_version ? true : false;
> +}
> +
> int intel_hdcp_enable(struct intel_connector *connector,
> enum transcoder cpu_transcoder, u8 content_type)
> {
> @@ -2023,7 +2033,8 @@ int intel_hdcp_enable(struct intel_connector *connector,
>* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
>* is capable of HDCP2.2, it is preferred to use HDCP2.2.
>*/
> - if (intel_hdcp2_capable(connector)) {
> + if (hdcp_debugfs_requested(hdcp, HDCP_VERSION_2_2) &&
> + intel_hdcp2_capable(connector)) {
> ret = _intel_hdcp2_enable(connector);
> if (!ret)
> check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS;
> @@ -2033,7 +2044,8 @@ int intel_hdcp_enable(struct intel_connector *connector,
>* When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will
>* be attempted.
>*/
> - if (ret && intel_hdcp_capable(connector) &&
> + if (ret && hdcp_debugfs_requested(hdcp, HDCP_VERSION_1_4) &&
IMHO there is no case when both version HDCP 2.2 and HDCP 1.4 version
will be set, i believe for IGT if HDCP 2.2 fails and version is HDCP 2.2
it should have returen from above, no need to check a ret value and
HDCP 1.4 version. Could we simplify conditions here.
Thanks,
Anshuman Gupta.
> + intel_hdcp_capable(connector) &&
> hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) {
> ret = _intel_hdcp_enable(connector);
> }
> --
> 2.17.1
>
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add a new debugfs to request HDCP version
On 2020-06-08 at 15:31:03 +0530, Ankit Nautiyal wrote:
> As per the current HDCP design, the driver selects the highest
> version of HDCP that can be used to satisfy the content-protection
> requirements of the user. Due to this, the content-protection
> tests cannot test a lower version of HDCP, if the platform and the
> display panel, both support higher HDCP version.
>
> To provide some support for testing and debugging, a per-connector
> debugfs is required to set the HDCP version via debugfs that the
> kernel can consider, while enabling HDCP.
>
> This patch adds a new debugfs entry for each connector that supports
> HDCP. For enforcing a particular HDCP version for a connector, the user
> can write into the debugfs for that connector.
IMHO this doesn't feel like a debugfs per connector, even if it is a
global singleton resource for all connectors, i don't see any problem in
that, may be a global debugfs would make sense here ?
>
> v2: As suggested by Jani Nikula:
> -used kstrtouint_from_user() to directly read as uint from user buffer.
> -used 32 bit flag instead of 64 bit for hdcp_ver flag.
> -removed unnecessary prints and fixed other minor formatting issues.
>
> Signed-off-by: Ankit Nautiyal
> ---
> .../drm/i915/display/intel_display_debugfs.c | 68 +++
> 1 file changed, 68 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 70525623bcdf..c01653d412e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2185,6 +2185,72 @@ static const struct file_operations
> i915_dsc_fec_support_fops = {
> .write = i915_dsc_fec_support_write
> };
>
> +static int i915_hdcp_ver_request_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct intel_connector *intel_connector = to_intel_connector(connector);
> + u32 hdcp_ver_flag;
> +
> + if (connector->status != connector_status_connected)
> + return -ENODEV;
> +
> + /* HDCP is supported by connector */
> + if (!intel_connector->hdcp.shim)
> + return -EINVAL;
> +
> + hdcp_ver_flag = intel_connector->hdcp.debugfs_ver_request;
> + seq_printf(m, "HDCP_VER_FLAGS: %u\n", hdcp_ver_flag);
> +
> + return 0;
> +}
> +
> +static int i915_hdcp_ver_request_open(struct inode *inode,
> + struct file *file)
> +{
> + return single_open(file, i915_hdcp_ver_request_show,
> +inode->i_private);
> +}
> +
> +static ssize_t i915_hdcp_ver_request_write(struct file *file,
> +const char __user *ubuf,
> +size_t len, loff_t *offp)
> +{
> + unsigned int hdcp_ver = 0;
> + int ret;
> + struct drm_connector *connector =
> + ((struct seq_file *)file->private_data)->private;
> + struct intel_connector *intel_connector = to_intel_connector(connector);
> + struct intel_hdcp *hdcp = &intel_connector->hdcp;
> +
> + if (!hdcp->shim)
> + return -EINVAL;
> +
> + if (len == 0)
> + return 0;
> +
> + ret = kstrtouint_from_user(ubuf, len, 0, &hdcp_ver);
> + if (ret < 0)
> + return ret;
> +
> + if (hdcp_ver > HDCP_VERSION_MASK)
> + return -EINVAL;
> +
> + hdcp->debugfs_ver_request = hdcp_ver;
A lockless assignment, this would probably not scale.
Could u please add some comment here for current IGT need this is ok,
but for any concurrent usgaes proper locking is required.
Thanks,
Anshuman
> +
> + *offp += len;
> +
> + return len;
> +}
> +
> +static const struct file_operations i915_hdcp_ver_request_fops = {
> + .owner = THIS_MODULE,
> + .open = i915_hdcp_ver_request_open,
> + .read = seq_read,
> + .llseek = seq_lseek,
> + .release = single_release,
> + .write = i915_hdcp_ver_request_write
> +};
> +
> /**
> * intel_connector_debugfs_add - add i915 specific connector debugfs files
> * @connector: pointer to a registered drm_connector
> @@ -2215,6 +2281,8 @@ int intel_connector_debugfs_add(struct drm_connector
> *connector)
> connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
> debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root,
> connector, &i915_hdcp_sink_capability_fops);
> + debugfs_create_file("i915_hdcp_version_request", 0444, root,
> + connector, &i915_hdcp_ver_request_fops);
> }
>
> if (INTEL_GEN(dev_priv) >= 10 &&
> --
> 2.17.1
>
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[Intel-gfx] [PATCH] drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs
Debug print for power domain audio get/put.
This will help to deubg the CI s2idle incomplete
failures.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_audio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index ad4aa66fd676..145afd2f1d4a 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -1012,6 +1012,7 @@ static unsigned long
i915_audio_component_get_power(struct device *kdev)
/* Catch potential impedance mismatches before they occur! */
BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
+ drm_dbg_kms(&dev_priv->drm, "get audio power domian power\n");
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
if (dev_priv->audio_power_refcount++ == 0) {
@@ -1045,6 +1046,7 @@ static void i915_audio_component_put_power(struct device
*kdev,
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, false);
+ drm_dbg_kms(&dev_priv->drm, "put audio power domian power\n");
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);
}
--
2.26.2
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Re: [Intel-gfx] [PATCH] drm/i915: POWER_DOMAIN_AUDIO ref-count debug logs
On 2020-06-17 at 11:12:12 +0100, Chris Wilson wrote: > Quoting Anshuman Gupta (2020-06-17 10:50:01) > > Debug print for power domain audio get/put. > > This will help to deubg the CI s2idle incomplete > > failures. > > Do we not already print the mismatching pm, and who we are unable to > find a corresponding release for? Thanks Chris for review comment, Yes it is there, but POWER_DOMAIN_AUDIO get/put request initiated by snd_audio along with i915. So in order to confirm if it is a bug from snd_audio module we would require to track the get/put resuest from snd_audio. Thanks, Anshuman Gupta. > -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state
Content Protection property should be updated as per the kernel
internal state. Let's say if Content protection is disabled
by userspace, CP property should be set to UNDESIRED so that
reauthentication will not happen until userspace request it again,
but when kernel disables the HDCP due to any DDI disabling sequences
like modeset/DPMS operation, kernel should set the property to
DESIRED, so that when opportunity arises, kernel will start the
HDCP authentication on its own.
Somewhere in the line, state machine to set content protection to
DESIRED from kernel was broken and IGT coverage was missing for it.
This patch fixes it.
v2:
- Fixing hdcp CP state in connector atomic check function
intel_hdcp_atomic_check(). [Maarten]
This will require to check hdcp->value in intel_hdcp_update_pipe()
in order to avoid enabling hdcp, if it was already enabled.
v3:
- Rebased.
Cc: Ramalingam C
Cc: Maarten Lankhorst
Reviewed-by: Uma Shankar
Signed-off-by: Anshuman Gupta
Link: https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2 #v1
Link: https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3 #v2
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 27 +++
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 815b054bb167..0d410652e194 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2086,6 +2086,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
(conn_state->hdcp_content_type != hdcp->content_type &&
conn_state->content_protection !=
DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
+ bool desired_and_not_enabled = false;
/*
* During the HDCP encryption session if Type change is requested,
@@ -2108,8 +2109,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state
*state,
}
if (conn_state->content_protection ==
- DRM_MODE_CONTENT_PROTECTION_DESIRED ||
- content_protection_type_changed)
+ DRM_MODE_CONTENT_PROTECTION_DESIRED) {
+ mutex_lock(&hdcp->mutex);
+ /* Avoid enabling hdcp, if it already ENABLED */
+ desired_and_not_enabled =
+ hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
+ mutex_unlock(&hdcp->mutex);
+ }
+
+ if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
crtc_state->cpu_transcoder,
(u8)conn_state->hdcp_content_type);
@@ -2158,6 +2166,19 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
return;
}
+ crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
+ new_state->crtc);
+ /*
+* Fix the HDCP uapi content protection state in case of modeset.
+* FIXME: As per HDCP content protection property uapi doc, an uevent()
+* need to be sent if there is transition from ENABLED->DESIRED.
+*/
+ if (drm_atomic_crtc_needs_modeset(crtc_state) &&
+ (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
+ new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED))
+ new_state->content_protection =
+ DRM_MODE_CONTENT_PROTECTION_DESIRED;
+
/*
* Nothing to do if the state didn't change, or HDCP was activated since
* the last commit. And also no change in hdcp content type.
@@ -2170,8 +2191,6 @@ void intel_hdcp_atomic_check(struct drm_connector
*connector,
return;
}
- crtc_state = drm_atomic_get_new_crtc_state(new_state->state,
- new_state->crtc);
crtc_state->mode_changed = true;
}
--
2.26.2
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Re: [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message
On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote:
Hi Sean,
I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a.
I have looked the entire series, i will take up this opportunity to review
the series from HDCP over DP MST POV.
I think theoretically this series should work or Gen12 as well, as DP MST
streams
are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg
(generating Stream State Signature L’).
I will test this on Gen12 H/W with DP MST support and will provide my inputs.
Meanwhile while going through DP MST v1.2a specs(Page 262) came to know about
a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h),
Bit 2 : STREAM_STATUS_CHANGED.
When this bit set to ‘1’ indicates the source must re-check the Stream Status
with the QUERY_STREAM_ENCRYPTION_STATUS message.
Currently i feel this irq support is missing, do we require to support
above IRQ vector for DP MST stream encryption.
Thanks,
Anshuman Gupta.
> From: Sean Paul
>
> Used to query whether an MST stream is encrypted or not.
>
> Signed-off-by: Sean Paul
>
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run
> #v4
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-s...@poorly.run
> #v5
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-s...@poorly.run
> #v6
>
> Changes in v4:
> -Added to the set
> Changes in v5:
> -None
> Changes in v6:
> -Use FIELD_PREP to generate request buffer bitfields (Lyude)
> -Add mst selftest and dump/decode_sideband_req for QSES (Lyude)
> Changes in v7:
> -None
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++
> .../drm/selftests/test-drm_dp_mst_helper.c| 17 +++
> include/drm/drm_dp_helper.h | 3 +
> include/drm/drm_dp_mst_helper.h | 44 ++
> 4 files changed, 206 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index b2f5a84b4cfb..fc68478eaeb4 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -20,11 +20,13 @@
> * OF THIS SOFTWARE.
> */
>
> +#include
> #include
> #include
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct
> drm_dp_sideband_msg_req_body *req,
> memcpy(&buf[idx], req->u.i2c_write.bytes,
> req->u.i2c_write.num_bytes);
> idx += req->u.i2c_write.num_bytes;
> break;
> + case DP_QUERY_STREAM_ENC_STATUS: {
> + const struct drm_dp_query_stream_enc_status *msg;
> +
> + msg = &req->u.enc_status;
> + buf[idx] = msg->stream_id;
> + idx++;
> + memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id));
> + idx += sizeof(msg->client_id);
> + buf[idx] = 0;
> + buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);
> + buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
> + buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);
> + buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
> + idx++;
> + }
> + break;
> }
> raw->cur_len = idx;
> }
> @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct
> drm_dp_sideband_msg_tx *raw,
> return -ENOMEM;
> }
> break;
> + case DP_QUERY_STREAM_ENC_STATUS:
> + req->u.enc_status.stream_id = buf[idx++];
> + for (i = 0; i < sizeof(req->u.enc_status.client_id); i++)
> + req->u.enc_status.client_id[i] = buf[idx++];
> +
> + req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),
> +buf[idx]);
> + req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2),
> + buf[idx]);
> + req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),
> + buf[idx]);
> + req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5),
> + buf[idx]);
> + break;
> }
>
> return 0;
> @@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct
> drm_dp_sideband_msg_req_body *req
> req->u.i2c_write.num_bytes,
Re: [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message
On 2020-06-30 at 12:48:34 -0400, Sean Paul wrote:
> On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta
> wrote:
> >
> > On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote:
> > Hi Sean,
> > I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a.
> > I have looked the entire series, i will take up this opportunity to review
> > the series from HDCP over DP MST POV.
> > I think theoretically this series should work or Gen12 as well, as DP MST
> > streams
> > are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg
> > (generating Stream State Signature L’).
> > I will test this on Gen12 H/W with DP MST support and will provide my
> > inputs.
> >
> > Meanwhile while going through DP MST v1.2a specs(Page 262) came to know
> > about
> > a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h),
> > Bit 2 : STREAM_STATUS_CHANGED.
> > When this bit set to ‘1’ indicates the source must re-check the Stream
> > Status
> > with the QUERY_STREAM_ENCRYPTION_STATUS message.
> > Currently i feel this irq support is missing, do we require to support
> > above IRQ vector for DP MST stream encryption.
> >
>
> Hi Anshuman,
> Thank you for your comments.
>
> QUERY_STREAM_ENCRYPTION_STATUS is not necessary for HDCP 1.x, I added
> this as a safety check to ensure that the streams were being
> encrypted. As such, the existing integrity checks in place for DP are
> sufficient to satisfy spec. When HDCP 2.2 support is added for MST,
> handling QSES will need to be addressed to meet spec. Note also that
> we're not validating the QSES signature for the same reason.
Thanks sean for the explanation,
overall patch looks good to me but i have couple of doubt see below.
>
> Sean
>
>
> > Thanks,
> > Anshuman Gupta.
> >
> > > From: Sean Paul
> > >
> > > Used to query whether an MST stream is encrypted or not.
> > >
> > > Signed-off-by: Sean Paul
> > >
> > > Link:
> > > https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run
> > > #v4
> > > Link:
> > > https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-s...@poorly.run
> > > #v5
> > > Link:
> > > https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-s...@poorly.run
> > > #v6
> > >
> > > Changes in v4:
> > > -Added to the set
> > > Changes in v5:
> > > -None
> > > Changes in v6:
> > > -Use FIELD_PREP to generate request buffer bitfields (Lyude)
> > > -Add mst selftest and dump/decode_sideband_req for QSES (Lyude)
> > > Changes in v7:
> > > -None
> > > ---
> > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++
> > > .../drm/selftests/test-drm_dp_mst_helper.c| 17 +++
> > > include/drm/drm_dp_helper.h | 3 +
> > > include/drm/drm_dp_mst_helper.h | 44 ++
> > > 4 files changed, 206 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> > > b/drivers/gpu/drm/drm_dp_mst_topology.c
> > > index b2f5a84b4cfb..fc68478eaeb4 100644
> > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> > > @@ -20,11 +20,13 @@
> > > * OF THIS SOFTWARE.
> > > */
> > >
> > > +#include
> > > #include
> > > #include
> > > #include
> > > #include
> > > #include
> > > +#include
> > > #include
> > > #include
> > > #include
> > > @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct
> > > drm_dp_sideband_msg_req_body *req,
> > > memcpy(&buf[idx], req->u.i2c_write.bytes,
> > > req->u.i2c_write.num_bytes);
> > > idx += req->u.i2c_write.num_bytes;
> > > break;
> > > + case DP_QUERY_STREAM_ENC_STATUS: {
> > > + const struct drm_dp_query_stream_enc_status *msg;
> > > +
> > > + msg = &req->u.enc_status;
> > > + buf[idx] = msg->stream_id;
> > > + idx++;
> > > + memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id));
> > > + idx += sizeof(msg->client_id);
> > > + buf[idx] = 0;
> > > + buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);
> > > + buf[idx] |= msg-&
Re: [Intel-gfx] [PATCH v7 14/17] drm/i915: Add connector to hdcp_shim->check_link()
On 2020-06-23 at 21:29:04 +0530, Sean Paul wrote:
> From: Sean Paul
>
> Currently we derive the connector from digital port in check_link(). For
> MST, this isn't sufficient since the digital port passed into the
> function can have multiple connectors downstream. This patch adds
> connector to the check_link() arguments so we have it when we need it.
>
> Signed-off-by: Sean Paul
Looks good to me, this require a rebase on latest drm-tip
Reviewed-by: Anshuman Gupta
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-13-s...@poorly.run
> #v4
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-14-s...@poorly.run
> #v5
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-14-s...@poorly.run
> #v6
>
> Changes in v4:
> -Added to the set
> Changes in v5:
> -None
> Changes in v6:
> -None
> Changes in v7:
> -None
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++---
> 4 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 811085ef3fba..94211b8fc159 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -318,7 +318,8 @@ struct intel_hdcp_shim {
>bool enable);
>
> /* Ensures the link is still protected */
> - bool (*check_link)(struct intel_digital_port *intel_dig_port);
> + bool (*check_link)(struct intel_digital_port *intel_dig_port,
> +struct intel_connector *connector);
>
> /* Detects panel's hdcp capability. This is optional for HDMI. */
> int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index e26a45f880cb..43446a6cae8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -223,7 +223,8 @@ int intel_dp_hdcp_toggle_signalling(struct
> intel_digital_port *intel_dig_port,
> }
>
> static
> -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> +bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> ssize_t ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index d79d4142aea7..6bd0e4616ee1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -953,7 +953,7 @@ static int intel_hdcp_check_link(struct intel_connector
> *connector)
> goto out;
> }
>
> - if (hdcp->shim->check_link(intel_dig_port)) {
> + if (hdcp->shim->check_link(intel_dig_port, connector)) {
> if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> intel_hdcp_update_value(connector,
> DRM_MODE_CONTENT_PROTECTION_ENABLED, true);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index ca71ee3dd1c7..b12f1af0611d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1546,11 +1546,10 @@ int intel_hdmi_hdcp_toggle_signalling(struct
> intel_digital_port *intel_dig_port,
> }
>
> static
> -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
> +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port,
> + struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> - struct intel_connector *connector =
> - intel_dig_port->hdmi.attached_connector;
> enum port port = intel_dig_port->base.port;
> enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
> int ret;
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: [Intel-gfx] [PATCH v7 13/17] drm/i915: Plumb port through hdcp init
On 2020-06-23 at 21:29:03 +0530, Sean Paul wrote:
> From: Sean Paul
>
> This patch plumbs port through hdcp init instead of relying on
> intel_attached_encoder() to return a non-NULL encoder which won't work
> for MST connectors.
Looks good to me,
Reviewed-by: Anshuman Gupta
>
> Cc: Ville Syrjälä
> Signed-off-by: Sean Paul
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-13-s...@poorly.run
> #v5
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-13-s...@poorly.run
> #v6
>
> Changes in v5:
> -Added to the set
> Changes in v6:
> -None
> Changes in v7:
> -None
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.c| 11 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.h| 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
> 4 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 0e06a1066d61..e26a45f880cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -630,7 +630,8 @@ int intel_dp_init_hdcp(struct intel_digital_port
> *intel_dig_port,
> return 0;
>
> if (!intel_dp_is_edp(intel_dp))
> - return intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
> + return intel_hdcp_init(intel_connector, port,
> +&intel_dp_hdcp_shim);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 5679877c6b4c..d79d4142aea7 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1955,6 +1955,7 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum
> transcoder cpu_transcoder)
> }
>
> static int initialize_hdcp_port_data(struct intel_connector *connector,
> + enum port port,
>const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> @@ -1962,8 +1963,7 @@ static int initialize_hdcp_port_data(struct
> intel_connector *connector,
> struct hdcp_port_data *data = &hdcp->port_data;
>
> if (INTEL_GEN(dev_priv) < 12)
> - data->fw_ddi =
> -
> intel_get_mei_fw_ddi_index(intel_attached_encoder(connector)->port);
> + data->fw_ddi = intel_get_mei_fw_ddi_index(port);
> else
> /*
>* As per ME FW API expectation, for GEN 12+, fw_ddi is filled
> @@ -2033,14 +2033,14 @@ void intel_hdcp_component_init(struct
> drm_i915_private *dev_priv)
> }
> }
>
> -static void intel_hdcp2_init(struct intel_connector *connector,
> +static void intel_hdcp2_init(struct intel_connector *connector, enum port
> port,
>const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> - ret = initialize_hdcp_port_data(connector, shim);
> + ret = initialize_hdcp_port_data(connector, port, shim);
> if (ret) {
> drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
> return;
> @@ -2050,6 +2050,7 @@ static void intel_hdcp2_init(struct intel_connector
> *connector,
> }
>
> int intel_hdcp_init(struct intel_connector *connector,
> + enum port port,
> const struct intel_hdcp_shim *shim)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> @@ -2060,7 +2061,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> return -EINVAL;
>
> if (is_hdcp2_supported(dev_priv))
> - intel_hdcp2_init(connector, shim);
> + intel_hdcp2_init(connector, port, shim);
>
> ret =
> drm_connector_attach_content_protection_property(&connector->base,
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h
> b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 86bbaec120cc..1bbf5b67ed0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -22,7 +22,7 @@ enum transcoder;
> void intel_hdcp_atomic_check(struct drm_connector *connector,
>struct drm_connector_state *old_state,
>struct drm_connecto
Re: [Intel-gfx] [PATCH v7 17/17] drm/i915: Add HDCP 1.4 support for MST connectors
+ .repeater_present = intel_dp_hdcp_repeater_present,
> + .read_ri_prime = intel_dp_hdcp_read_ri_prime,
> + .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
> + .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
> + .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
> + .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
> + .check_link = intel_dp_mst_hdcp_check_link,
> + .hdcp_capable = intel_dp_hdcp_capable,
> +
> + .protocol = HDCP_PROTOCOL_DP,
> +};
> +
> int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port,
> struct intel_connector *intel_connector)
> {
> @@ -630,7 +691,10 @@ int intel_dp_init_hdcp(struct intel_digital_port
> *intel_dig_port,
> if (!is_hdcp_supported(dev_priv, port))
> return 0;
>
> - if (!intel_dp_is_edp(intel_dp))
> + if (intel_connector->mst_port)
> + return intel_hdcp_init(intel_connector, port,
> +&intel_dp_mst_hdcp_shim);
> + else if (!intel_dp_is_edp(intel_dp))
> return intel_hdcp_init(intel_connector, port,
> &intel_dp_hdcp_shim);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 0675825dcc20..abaaeeb963d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -37,6 +37,7 @@
> #include "intel_dp.h"
> #include "intel_dp_mst.h"
> #include "intel_dpio_phy.h"
> +#include "intel_hdcp.h"
>
> static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> @@ -352,6 +353,8 @@ static void intel_mst_disable_dp(struct
> intel_atomic_state *state,
> drm_dbg_kms(&i915->drm, "active links %d\n",
> intel_dp->active_mst_links);
>
> + intel_hdcp_disable(intel_mst->connector);
> +
> drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);
>
> ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
> @@ -548,6 +551,13 @@ static void intel_mst_enable_dp(struct
> intel_atomic_state *state,
>
> if (pipe_config->has_audio)
> intel_audio_codec_enable(encoder, pipe_config, conn_state);
> +
> + /* Enable hdcp if it's desired */
> + if (conn_state->content_protection ==
> + DRM_MODE_CONTENT_PROTECTION_DESIRED)
> + intel_hdcp_enable(to_intel_connector(conn_state->connector),
> + pipe_config->cpu_transcoder,
> + (u8)conn_state->hdcp_content_type);
I am not sure about that, do we need to enable HDCP for every
DP-MST connector here, it should be only immediate downstream connector
we should authenticate as repeater, after that it should be repeater
responsibility to authenticate further downstream connectors.
Tested this entire series on Gen12 H/W after removing the Gen12 restriction
condition with daisy-chain of two DP MST display.
Master DP MST connector has failed the repeater downstream authentication
due to error "KSV list failed to become ready" ETIMEDOUT.
Slave DP MST connector passes the authentication stage but failed to
enable the encryption.
Thanks,
Anshuman Gupta.
> }
>
> static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
> @@ -770,6 +780,14 @@ static struct drm_connector
> *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
> intel_attach_force_audio_property(connector);
> intel_attach_broadcast_rgb_property(connector);
>
> +
> + /* TODO: Figure out how to make HDCP work on GEN12+ */
> + if (INTEL_GEN(dev_priv) < 12) {
> + ret = intel_dp_init_hdcp(intel_dig_port, intel_connector);
> + if (ret)
> + DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
> + }
> +
> /*
>* Reuse the prop from the SST connector because we're
>* not allowed to create new props after device registration.
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 6bd0e4616ee1..ddc9db8de2bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2060,7 +2060,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> if (!shim)
> return -EINVAL;
>
> - if (is_hdcp2_supported(dev_priv))
> + if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
> intel_hdcp2_init(connector, port, shim);
>
> ret =
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v7 08/17] drm/i915: Clean up intel_hdcp_disable
On 2020-06-23 at 21:28:58 +0530, Sean Paul wrote:
> From: Sean Paul
>
> Add an out label and un-indent hdcp disable in preparation for
> hdcp_mutex. No functional changes
LGTM
Reviewed-by: Anshuman Gupta
>
> Signed-off-by: Sean Paul
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-9-s...@poorly.run
> #v6
>
> Changes in v7:
> -Split into separate patch (Ramalingam)
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 19 ++-
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 62cab3aea745..16bf0fbe5f17 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2113,16 +2113,17 @@ int intel_hdcp_disable(struct intel_connector
> *connector)
>
> mutex_lock(&hdcp->mutex);
>
> - if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
> - intel_hdcp_update_value(connector,
> - DRM_MODE_CONTENT_PROTECTION_UNDESIRED,
> - false);
> - if (hdcp->hdcp2_encrypted)
> - ret = _intel_hdcp2_disable(connector);
> - else if (hdcp->hdcp_encrypted)
> - ret = _intel_hdcp_disable(connector);
> - }
> + if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)
> + goto out;
>
> + intel_hdcp_update_value(connector,
> + DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false);
> + if (hdcp->hdcp2_encrypted)
> + ret = _intel_hdcp2_disable(connector);
> + else if (hdcp->hdcp_encrypted)
> + ret = _intel_hdcp_disable(connector);
> +
> +out:
> mutex_unlock(&hdcp->mutex);
> cancel_delayed_work_sync(&hdcp->check_work);
> return ret;
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v7 17/17] drm/i915: Add HDCP 1.4 support for MST connectors
On 2020-07-03 at 16:48:27 +0530, Anshuman Gupta wrote:
> On 2020-06-23 at 21:29:07 +0530, Sean Paul wrote:
> > From: Sean Paul
> >
> > Now that all the groundwork has been laid, we can turn on HDCP 1.4 over
> > MST. Everything except for toggling the HDCP signalling and HDCP 2.2
> > support is the same as the DP case, so we'll re-use those callbacks
> >
> > Cc: Juston Li
> > Signed-off-by: Sean Paul
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-12-s...@poorly.run
> > #v1
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-13-s...@poorly.run
> > #v2
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-13-s...@poorly.run
> > #v3
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-15-s...@poorly.run
> > #v4
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-17-s...@poorly.run
> > #v5
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-17-s...@poorly.run
> > #v6
> >
> > Changes in v2:
> > -Toggle HDCP from encoder disable/enable
> > -Don't disable HDCP on MST connector destroy, leave that for encoder
> > disable, just ensure the check_work routine isn't running any longer
> > Changes in v3:
> > -Place the shim in the new intel_dp_hdcp.c file (Ville)
> > Changes in v4:
> > -Actually use the mst shim for mst connections (Juston)
> > -Use QUERY_STREAM_ENC_STATUS MST message to verify channel is encrypted
> > Changes in v5:
> > -Add sleep on disable signalling to match hdmi delay
> > Changes in v6:
> > -Disable HDCP over MST on GEN12+ since I'm unsure how it should work and I
> > don't have hardware to test it
> > Changes in v7:
> > -Remove hdcp2 shims for MST in favor of skipping hdcp2 init (Ramalingam)
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 66 +++-
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++
> > drivers/gpu/drm/i915/display/intel_hdcp.c| 2 +-
> > 3 files changed, 84 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 43446a6cae8d..3f67bd27fc3c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -7,10 +7,12 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> >
> > #include "intel_display_types.h"
> > +#include "intel_ddi.h"
> > #include "intel_dp.h"
> > #include "intel_hdcp.h"
> >
> > @@ -618,6 +620,65 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim
> > = {
> > .protocol = HDCP_PROTOCOL_DP,
> > };
> >
> > +static int
> > +intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port
> > *intel_dig_port,
> > + enum transcoder cpu_transcoder,
> > + bool enable)
> > +{
> > + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> > + int ret;
> > +
> > + if (!enable)
> > + usleep_range(6, 60); /* Bspec says >= 6us */
> > +
> > + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base,
> > + cpu_transcoder, enable);
> > + if (ret)
> > + drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> > + enable ? "Enable" : "Disable", ret);
> > + return ret;
> > +}
> > +
> > +static
> > +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port
> > *intel_dig_port,
> > + struct intel_connector *connector)
> > +{
> > + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> > + struct intel_dp *intel_dp = &intel_dig_port->dp;
> > + struct drm_dp_query_stream_enc_status_ack_reply reply;
> > + int ret;
> > +
> > + if (!intel_dp_hdcp_check_link(intel_dig_port, connector))
> > + return false;
> > +
> > + ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
> > + connector->port, &reply);
> > + if (ret) {
> > + drm_dbg
Re: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per the kernel internal state
On 2020-07-01 at 13:31:18 +0530, Shankar, Uma wrote:
> > > -Original Message-
> > > From: Jani Nikula
> > > Sent: Tuesday, June 30, 2020 3:30 PM
> > > To: Gupta, Anshuman ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: Shankar, Uma
> > > Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/hdcp: Update CP as per
> > > the kernel internal state
> > >
> > >
> > > Uma, is the R-b still valid? It's been a while.
> >
> > Yeah Jani, the changes look good. Will need a rebase and fresh CI results
> > though.
>
> Seems the CI results are already out and we are clean.
Hi Ram ,
CI results are clean for this rebase patch,
Could you please help with merging,
I belive your RB's are valid either-way wrt to your comment.
Thanks,
Anshuman Gupta.
>
> > Regards,
> > Uma Shankar
> >
> > > BR,
> > > Jani.
> > >
> > >
> > > On Tue, 30 Jun 2020, Anshuman Gupta wrote:
> > > > Content Protection property should be updated as per the kernel
> > > > internal state. Let's say if Content protection is disabled by
> > > > userspace, CP property should be set to UNDESIRED so that
> > > > reauthentication will not happen until userspace request it again,
> > > > but when kernel disables the HDCP due to any DDI disabling sequences
> > > > like modeset/DPMS operation, kernel should set the property to
> > > > DESIRED, so that when opportunity arises, kernel will start the HDCP
> > > > authentication on its own.
> > > >
> > > > Somewhere in the line, state machine to set content protection to
> > > > DESIRED from kernel was broken and IGT coverage was missing for it.
> > > > This patch fixes it.
> > > >
> > > > v2:
> > > > - Fixing hdcp CP state in connector atomic check function
> > > > intel_hdcp_atomic_check(). [Maarten]
> > > > This will require to check hdcp->value in intel_hdcp_update_pipe()
> > > > in order to avoid enabling hdcp, if it was already enabled.
> > > >
> > > > v3:
> > > > - Rebased.
> > > >
> > > > Cc: Ramalingam C
> > > > Cc: Maarten Lankhorst
> > > > Reviewed-by: Uma Shankar
> > > > Signed-off-by: Anshuman Gupta
> > > > Link:
> > > > https://patchwork.freedesktop.org/patch/350962/?series=72664&rev=2
> > > > #v1
> > > > Link:
> > > > https://patchwork.freedesktop.org/patch/359396/?series=72251&rev=3
> > > > #v2
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_hdcp.c | 27
> > > > +++
> > > > 1 file changed, 23 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > > index 815b054bb167..0d410652e194 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > > > @@ -2086,6 +2086,7 @@ void intel_hdcp_update_pipe(struct
> > > intel_atomic_state *state,
> > > > (conn_state->hdcp_content_type != hdcp->content_type &&
> > > > conn_state->content_protection !=
> > > > DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
> > > > + bool desired_and_not_enabled = false;
> > > >
> > > > /*
> > > > * During the HDCP encryption session if Type change is
> > > > requested,
> > > > @@ -2108,8 +2109,15 @@ void intel_hdcp_update_pipe(struct
> > > intel_atomic_state *state,
> > > > }
> > > >
> > > > if (conn_state->content_protection ==
> > > > - DRM_MODE_CONTENT_PROTECTION_DESIRED ||
> > > > - content_protection_type_changed)
> > > > + DRM_MODE_CONTENT_PROTECTION_DESIRED) {
> > > > + mutex_lock(&hdcp->mutex);
> > > > + /* Avoid enabling hdcp, if it already ENABLED */
> > > > + desired_and_not_enabled =
> > > > + hdcp->value !=
> > > DRM_MODE_CONTENT_PROTECTION_ENABLED;
> > > > + mutex_unlock(&hdcp->mutex);
> > > > + }
> > > > +
> > > > + if (desired_and
Re: [Intel-gfx] [PATCH v7 17/17] drm/i915: Add HDCP 1.4 support for MST connectors
On 2020-07-09 at 16:07:12 +0530, Ramalingam C wrote:
> On 2020-06-23 at 11:59:07 -0400, Sean Paul wrote:
> > From: Sean Paul
> >
> > Now that all the groundwork has been laid, we can turn on HDCP 1.4 over
> > MST. Everything except for toggling the HDCP signalling and HDCP 2.2
> > support is the same as the DP case, so we'll re-use those callbacks
> >
> > Cc: Juston Li
> > Signed-off-by: Sean Paul
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-12-s...@poorly.run
> > #v1
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-13-s...@poorly.run
> > #v2
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-13-s...@poorly.run
> > #v3
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-15-s...@poorly.run
> > #v4
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-17-s...@poorly.run
> > #v5
> > Link:
> > https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-17-s...@poorly.run
> > #v6
> >
> > Changes in v2:
> > -Toggle HDCP from encoder disable/enable
> > -Don't disable HDCP on MST connector destroy, leave that for encoder
> > disable, just ensure the check_work routine isn't running any longer
> > Changes in v3:
> > -Place the shim in the new intel_dp_hdcp.c file (Ville)
> > Changes in v4:
> > -Actually use the mst shim for mst connections (Juston)
> > -Use QUERY_STREAM_ENC_STATUS MST message to verify channel is encrypted
> > Changes in v5:
> > -Add sleep on disable signalling to match hdmi delay
> > Changes in v6:
> > -Disable HDCP over MST on GEN12+ since I'm unsure how it should work and I
> > don't have hardware to test it
> > Changes in v7:
> > -Remove hdcp2 shims for MST in favor of skipping hdcp2 init (Ramalingam)
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 66 +++-
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++
> > drivers/gpu/drm/i915/display/intel_hdcp.c| 2 +-
> > 3 files changed, 84 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > index 43446a6cae8d..3f67bd27fc3c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> > @@ -7,10 +7,12 @@
> > */
> >
> > #include
> > +#include
> > #include
> > #include
> >
> > #include "intel_display_types.h"
> > +#include "intel_ddi.h"
> > #include "intel_dp.h"
> > #include "intel_hdcp.h"
> >
> > @@ -618,6 +620,65 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim
> > = {
> > .protocol = HDCP_PROTOCOL_DP,
> > };
> >
> > +static int
> > +intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port
> > *intel_dig_port,
> > + enum transcoder cpu_transcoder,
> > + bool enable)
> > +{
> > + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev);
> > + int ret;
> > +
> > + if (!enable)
> > + usleep_range(6, 60); /* Bspec says >= 6us */
> > +
> > + ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base,
> > + cpu_transcoder, enable);
> Sean,
>
> This function toggles the TRANS_DDI_HDCP_SIGNALLING (9th)bit of
> TRANS_DDI_FUNC_CTL(tran)
> But in the hw specification this bit is mentioned to be ignored for non
> HDMI/DVI modes of the TRANS DDI.
>
> Any reason why we need this? Did you try with out this function?
>
> Apart from that Patch looks good to me.
IMHO it seems we are still missing to enable the Multistream HDCP Select
bit (5) in TRANS_DDI_FUNC_CTL register which is required to enable the
stream encryption.
Thanks,
Anshuman Gupta.
>
> -Ram
>
> > + if (ret)
> > + drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
> > + enable ? "Enable" : "Disable", ret);
> > + return ret;
> > +}
> > +
> > +static
> > +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port
> > *intel_dig_port,
> > + struct intel_connector *connector)
> > +{
> > + struct drm_i915_private *i915 = to_i9
Re: [Intel-gfx] [PATCH v7 15/17] drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband message
On 2020-07-02 at 20:07:36 +0530, Anshuman Gupta wrote: > On 2020-06-30 at 12:48:34 -0400, Sean Paul wrote: > > On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta > > wrote: > > > > > > On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote: > > > Hi Sean, > > > I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a. > > > I have looked the entire series, i will take up this opportunity to review > > > the series from HDCP over DP MST POV. > > > I think theoretically this series should work or Gen12 as well, as DP MST > > > streams > > > are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction > > > msg > > > (generating Stream State Signature L’). > > > I will test this on Gen12 H/W with DP MST support and will provide my > > > inputs. > > > > > > Meanwhile while going through DP MST v1.2a specs(Page 262) came to know > > > about > > > a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h), > > > Bit 2 : STREAM_STATUS_CHANGED. > > > When this bit set to ‘1’ indicates the source must re-check the Stream > > > Status > > > with the QUERY_STREAM_ENCRYPTION_STATUS message. > > > Currently i feel this irq support is missing, do we require to support > > > above IRQ vector for DP MST stream encryption. > > > > > > > Hi Anshuman, > > Thank you for your comments. > > > > QUERY_STREAM_ENCRYPTION_STATUS is not necessary for HDCP 1.x, I added > > this as a safety check to ensure that the streams were being > > encrypted. As such, the existing integrity checks in place for DP are > > sufficient to satisfy spec. When HDCP 2.2 support is added for MST, > > handling QSES will need to be addressed to meet spec. Note also that > > we're not validating the QSES signature for the same reason. > Thanks sean for the explanation, > overall patch looks good to me but i have couple of doubt see below. > > > > Sean > > > > > > > Thanks, > > > Anshuman Gupta. > > > > > > > From: Sean Paul > > > > > > > > Used to query whether an MST stream is encrypted or not. > > > > > > > > Signed-off-by: Sean Paul > > > > > > > > Link: > > > > https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-s...@poorly.run > > > > #v4 > > > > Link: > > > > https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-s...@poorly.run > > > > #v5 > > > > Link: > > > > https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-s...@poorly.run > > > > #v6 > > > > > > > > Changes in v4: > > > > -Added to the set > > > > Changes in v5: > > > > -None > > > > Changes in v6: > > > > -Use FIELD_PREP to generate request buffer bitfields (Lyude) > > > > -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) > > > > Changes in v7: > > > > -None > > > > --- > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++ > > > > .../drm/selftests/test-drm_dp_mst_helper.c| 17 +++ > > > > include/drm/drm_dp_helper.h | 3 + > > > > include/drm/drm_dp_mst_helper.h | 44 ++ > > > > 4 files changed, 206 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c > > > > b/drivers/gpu/drm/drm_dp_mst_topology.c > > > > index b2f5a84b4cfb..fc68478eaeb4 100644 > > > > --- a/drivers/gpu/drm/drm_dp_mst_topology.c > > > > +++ b/drivers/gpu/drm/drm_dp_mst_topology.c > > > > @@ -20,11 +20,13 @@ > > > > * OF THIS SOFTWARE. > > > > */ > > > > > > > > +#include > > > > #include > > > > #include > > > > #include > > > > #include > > > > #include > > > > +#include > > > > #include > > > > #include > > > > #include > > > > @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct > > > > drm_dp_sideband_msg_req_body *req, > > > > memcpy(&buf[idx], req->u.i2c_write.bytes, > > > > req->u.i2c_write.num_bytes); > > > > idx += req->u.i2c_write.num_bytes; > > > > break; > > > > + case DP_QUERY_STREAM_ENC_
[Intel-gfx] [RFC] drm/i915: Disable connector polling at runtime suspend
While i915 device is in runtime suspend, DRM connector polling causing device to wakeup from runtime suspend. This harm overall cpu idle statistics, therefore disabling polling while in runtime suspend. Cc: Imre Deak Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_drv.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5fd5af4bc855..1229c72f19c9 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1595,6 +1595,8 @@ static int intel_runtime_suspend(struct device *kdev) disable_rpm_wakeref_asserts(rpm); + drm_kms_helper_poll_disable(&dev_priv->drm); + /* * We are safe here against re-faults, since the fault handler takes * an RPM reference. @@ -1699,6 +1701,8 @@ static int intel_runtime_resume(struct device *kdev) */ intel_gt_runtime_resume(&dev_priv->gt); + drm_kms_helper_poll_enable(&dev_priv->drm); + /* * On VLV/CHV display interrupts are part of the display * power well, so hpd is reinitialized from there. For -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] drm/i915: Disable connector polling at runtime suspend
On 2020-07-21 at 16:32:17 +0300, Imre Deak wrote: > On Fri, Jul 17, 2020 at 05:34:25PM +0530, Anshuman Gupta wrote: > > While i915 device is in runtime suspend, DRM connector polling > > causing device to wakeup from runtime suspend. > > This harm overall cpu idle statistics, therefore > > disabling polling while in runtime suspend. > > Before disabling polling we would need to enable hotplug interrupts > during the runtime suspended state. Also I haven't seen yet stats where IMHO whilst it is deepest display C state, HOTPLUG interrupt will be disabled. > polling (which has a 10 sec period) have a significant effect on > idle residencies. IMHO it can still affect the runtime s0ix. Thanks, Anshuman Gupta. > > > Cc: Imre Deak > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/i915_drv.c | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > > b/drivers/gpu/drm/i915/i915_drv.c > > index 5fd5af4bc855..1229c72f19c9 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.c > > +++ b/drivers/gpu/drm/i915/i915_drv.c > > @@ -1595,6 +1595,8 @@ static int intel_runtime_suspend(struct device *kdev) > > > > disable_rpm_wakeref_asserts(rpm); > > > > + drm_kms_helper_poll_disable(&dev_priv->drm); > > + > > /* > > * We are safe here against re-faults, since the fault handler takes > > * an RPM reference. > > @@ -1699,6 +1701,8 @@ static int intel_runtime_resume(struct device *kdev) > > */ > > intel_gt_runtime_resume(&dev_priv->gt); > > > > + drm_kms_helper_poll_enable(&dev_priv->drm); > > + > > /* > > * On VLV/CHV display interrupts are part of the display > > * power well, so hpd is reinitialized from there. For > > -- > > 2.26.2 > > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Avoid modeset when content protection changes
On 2020-07-14 at 21:36:27 +0530, Sean Paul wrote:
> From: Sean Paul
>
> Instead of doing a full modeset to enable/disable content protection,
> simply go through the update_pipe flow which was introduced in the
> related patch below. This avoids flashing the screen every time the user
> starts viewing protected content.
>
> Related: 634852d1f468 ("drm/i915: HDCP state handling in ddi_update_pipe")
> Cc: Ramalingam C
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Sean Paul
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 89a4d294822d..839ce1715253 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2191,7 +2191,7 @@ void intel_hdcp_atomic_check(struct drm_connector
> *connector,
> return;
> }
>
> - crtc_state->mode_changed = true;
> + to_intel_crtc_state(crtc_state)->update_pipe = true;
IMHO intel_crtc_check_fastset() make sure that every crtc_state->mode_changed
will not turn up to a modeset. It seems it is already being taken care.
Thanks,
Anshuman Gupta.
> }
>
> /* Handles the CP_IRQ raised from the DP HDCP sink */
> --
> Sean Paul, Software Engineer, Google / Chromium OS
>
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Re: [Intel-gfx] [PATCH] drm/i915/display: Check for an LPSP encoder before dereferencing
On 2020-07-29 at 14:09:12 +0100, Chris Wilson wrote:
> Avoid a GPF at
>
> <1>[ 20.177320] BUG: kernel NULL pointer dereference, address:
> 007c
> <1>[ 20.177322] #PF: supervisor read access in kernel mode
> <1>[ 20.177323] #PF: error_code(0x) - not-present page
> <6>[ 20.177324] PGD 0 P4D 0
> <4>[ 20.177327] Oops: [#1] PREEMPT SMP PTI
> <4>[ 20.177328] CPU: 1 PID: 944 Comm: debugfs_test Not tainted
> 5.8.0-rc7-CI-CI_DRM_8814+ #1
> <4>[ 20.177330] Hardware name: Dell Inc. XPS 13 9360/0823VW, BIOS 2.9.0
> 07/09/2018
> <4>[ 20.177372] RIP: 0010:i915_lpsp_capability_show+0x44/0xc0 [i915]
> <4>[ 20.177374] Code: 0f b6 81 ca 0d 00 00 3c 0b 74 77 76 19 3c 0c 75 44 83
> 7e 7c 01 7e 2f 48 c7 c6 d7 b9 47 a0 e8 43 df 06 e1 31 c0 c3 3c 09 72 2b <8b>
> 46 7c 85 c0 75 e6 8b 82 e4 00 00 00 89 c2 83 e2 fb 83 fa 0a 74
> <4>[ 20.177376] RSP: 0018:c9cebe38 EFLAGS: 00010246
> <4>[ 20.177377] RAX: 0009 RBX: 888267fe6a58 RCX:
> 888252d1
> <4>[ 20.177378] RDX: 88824a9a4000 RSI: RDI:
> 888267fe6a30
> <4>[ 20.177379] RBP: R08: R09:
> 0001
> <4>[ 20.177380] R10: 0001 R11: R12:
> c9cebf08
> <4>[ 20.177381] R13: R14: 0001 R15:
> 888267fe6a30
> <4>[ 20.177383] FS: 7f6f9c6b5e40() GS:88827648()
> knlGS:
> <4>[ 20.177384] CS: 0010 DS: ES: CR0: 80050033
> <4>[ 20.177385] CR2: 007c CR3: 000255f04006 CR4:
> 003606e0
> <4>[ 20.177386] Call Trace:
> <4>[ 20.177390] seq_read+0xcb/0x420
>
> which is presumably from having no encoder attached at that time.
>
> Fixes: 8806211fe7b3 ("drm/i915: Add i915_lpsp_capability debugfs")
> Signed-off-by: Chris Wilson
> Cc: Animesh Manna
> Cc: Anshuman Gupta
> Cc: Uma Shankar
> Cc: "Ville Syrjälä"
Reviewed-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3644752cc5ec..5a5cfe25085b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2044,9 +2044,12 @@ DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
> static int i915_lpsp_capability_show(struct seq_file *m, void *data)
> {
> struct drm_connector *connector = m->private;
> - struct intel_encoder *encoder =
> - intel_attached_encoder(to_intel_connector(connector));
> struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct intel_encoder *encoder;
> +
> + encoder = intel_attached_encoder(to_intel_connector(connector));
> + if (!encoder)
> + return -ENODEV;
>
> if (connector->status != connector_status_connected)
> return -ENODEV;
> --
> 2.20.1
>
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[Intel-gfx] [PATCH v3 0/2] HDCP minor refactoring
No functional change. Anshuman Gupta (2): drm/i915/hdcp: Add update_pipe early return drm/i915/hdcp: No direct access to power_well desc drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +-- 1 file changed, 9 insertions(+), 14 deletions(-) -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drm/i915/hdcp: No direct access to power_well desc
HDCP code doesn't require to access power_well internal stuff,
instead it should use the intel_display_power_well_is_enabled()
to get the status of desired power_well.
No functional change.
v2:
- used with_intel_runtime_pm instead of get/put. [Jani]
v3:
- rebased.
Cc: Jani Nikula
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a1e0d518e529..e76b049618db 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -148,9 +148,8 @@ static int intel_hdcp_poll_ksv_fifo(struct
intel_digital_port *dig_port,
static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
- struct i915_power_well *power_well;
enum i915_power_well_id id;
+ intel_wakeref_t wakeref;
bool enabled = false;
/*
@@ -162,17 +161,9 @@ static bool hdcp_key_loadable(struct drm_i915_private
*dev_priv)
else
id = SKL_DISP_PW_1;
- mutex_lock(&power_domains->lock);
-
/* PG1 (power well #1) needs to be enabled */
- for_each_power_well(dev_priv, power_well) {
- if (power_well->desc->id == id) {
- enabled = power_well->desc->ops->is_enabled(dev_priv,
- power_well);
- break;
- }
- }
- mutex_unlock(&power_domains->lock);
+ with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
+ enabled = intel_display_power_well_is_enabled(dev_priv, id);
/*
* Another req for hdcp key loadability is enabled state of pll for
--
2.26.2
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[Intel-gfx] [PATCH v3 1/2] drm/i915/hdcp: Add update_pipe early return
Currently intel_hdcp_update_pipe() is also getting called for non-hdcp connectors and get through its conditional code flow, which is completely unnecessary for non-hdcp connectors, therefore it make sense to have an early return. No functional change. v2: - rebased. Reviewed-by: Uma Shankar Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/display/intel_hdcp.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 89a4d294822d..a1e0d518e529 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2082,11 +2082,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_hdcp *hdcp = &connector->hdcp; - bool content_protection_type_changed = + bool content_protection_type_changed, desired_and_not_enabled = false; + + if (!connector->hdcp.shim) + return; + + content_protection_type_changed = (conn_state->hdcp_content_type != hdcp->content_type && conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED); - bool desired_and_not_enabled = false; /* * During the HDCP encryption session if Type change is requested, -- 2.26.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > From: Anshuman Gupta <
> > anshuman.gu...@intel.com
> > >
> >
> > DGFX devices have different DMC_DEBUG* counter MMIO address
> > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > counter and handle i915_dmc_info accordingly.
> >
> > Cc: Uma Shankar <
> > uma.shan...@intel.com
> > >
> > Signed-off-by: Anshuman Gupta <
> > anshuman.gu...@intel.com
> > >
> > Signed-off-by: Lucas De Marchi <
> > lucas.demar...@intel.com
> > >
> > ---
> > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > 2 files changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 3644752cc5ec..e3536edcb394 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void
> > *unused)
> >CSR_VERSION_MINOR(csr->version));
> >
> > if (INTEL_GEN(dev_priv) >= 12) {
> > - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > + if (IS_DG1(dev_priv)) {
> > + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > + } else {
> > + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > + }
> > +
> > /*
> > * NOTE: DMC_DEBUG3 is a general purpose reg.
> > * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 4e95312eba24..78bdce67da08 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7549,6 +7549,8 @@ enum {
> > #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> > #define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
> > #define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
> > +#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154)
> > +#define DG1_DMC_DEBUG_DC6_COUNT_MMIO(0x134158)
>
> DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> Removing it:
DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
igfx platforms, considering name consistency it has been kept with name DG1_*
inline to B.Spec Index:49787.
Thanks,
Anshuman Gupta.
>
> Reviewed-by: José Roberto de Souza
>
>
> >
> > #define DMC_DEBUG3 _MMIO(0x101090)
> >
> >
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:
> On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> > On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > > From: Anshuman Gupta <
> > > > anshuman.gu...@intel.com
> > > >
> > > >
> > > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > > counter and handle i915_dmc_info accordingly.
> > > >
> > > > Cc: Uma Shankar <
> > > > uma.shan...@intel.com
> > > >
> > > >
> > > > Signed-off-by: Anshuman Gupta <
> > > > anshuman.gu...@intel.com
> > > >
> > > >
> > > > Signed-off-by: Lucas De Marchi <
> > > > lucas.demar...@intel.com
> > > >
> > > >
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++--
> > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > > > 2 files changed, 9 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > index 3644752cc5ec..e3536edcb394 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void
> > > > *unused)
> > > >CSR_VERSION_MINOR(csr->version));
> > > >
> > > > if (INTEL_GEN(dev_priv) >= 12) {
> > > > - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > + if (IS_DG1(dev_priv)) {
> > > > + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > > + } else {
> > > > + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > + }
> > > > +
> > > > /*
> > > > * NOTE: DMC_DEBUG3 is a general purpose reg.
> > > > * According to B.Specs:49196 DMC f/w reuses DC5/6
> > > > counter
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 4e95312eba24..78bdce67da08 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7549,6 +7549,8 @@ enum {
> > > > #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
> > > > #define TGL_DMC_DEBUG_DC5_COUNT_MMIO(0x101084)
> > > > #define TGL_DMC_DEBUG_DC6_COUNT_MMIO(0x101088)
> > > > +#define DG1_DMC_DEBUG_DC5_COUNT_MMIO(0x134154)
> > > > +#define DG1_DMC_DEBUG_DC6_COUNT_MMIO(0x134158)
> > >
> > > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > > Removing it:
> >
> > DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> > igfx platforms, considering name consistency it has been kept with name
> > DG1_*
> > inline to B.Spec Index:49787.
>
> A discrete graphics card will never be able to reach DC6 as it is a SOC power
> saving feature.
Is it documented some where, AFAIK DC6 is still diplay C state where it power
off its innermost power well,
with involvment of some non display third party f/w.
IMHO if any discrete-gfx would support DC6, it would be useful in the use cases
where driver is yet to request runtime suspend (DC9)
but display is already being powered off.
Thanks,
Anshuman Gupta.
>
> >
> > Thanks,
> > Anshuman Gupta.
> > > Reviewed-by: José Roberto de Souza <
> > > jose.so...@intel.com
> > > >
> > >
> > >
> > > >
> > > > #define DMC_DEBUG3 _MMIO(0x101090)
> > > >
> > > >
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > >
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
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