Re: [Intel-gfx] [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
On Fri, 15 Mar 2019 10:01:51 -0700 Rodrigo Vivi wrote: > On Fri, Mar 15, 2019 at 09:55:47AM -0700, Bob Paauwe wrote: > > On Fri, 15 Mar 2019 09:09:11 + > > Chris Wilson wrote: > > > > > Quoting Rodrigo Vivi (2019-03-14 22:53:44) > > > > On Thu, Mar 14, 2019 at 10:38:39PM +, Chris Wilson wrote: > > > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and > > > > > gen8, > > > > > so refactor that into a common routine. > > > > > > > > > > Signed-off-by: Chris Wilson > > > > > Cc: Bob Paauwe > > > > > Cc: Matthew Auld > > > > > Cc: Joonas Lahtinen > > > > > > > > Reviewed-by: Rodrigo Vivi > > > > > > I've pushed this series so that 36 bits should be a nice and simple drop > > > in. > > > > > > Thank you Bob for preparing these, sorry for not being clear enough on > > > the direction I felt the patches should take. > > > -Chris > > > > Thanks Chris, > > Thanks a lot Chris. > > > > > It was helpful to see how you organized and re-wrote the series. This > > was not code I was familiar with when I started so you're guidance > > helped a lot. > > > > Now I get to fix the EHL patches to take advantage of this. > > cool, so I will split the series into rv-b ones and probably > push soon just leaving the ppgt_size one for you to rebase > on top... > > thoughts? Would it make more sense to drop Patch 8, drm/i915/ehl: ehl has only 36bit extended ppgtt support and update patch 1 with the size added to the device_info? Otherwise, patch 8 becomes just adding the size into the device_info. Either way works for me. > > > > > Bob > > > ___ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > -- > > Bob Paauwe > > bob.j.paa...@intel.com > > IOTG / PED Software Organization > > Intel Corp. Folsom, CA > > (916) 356-6193 > > > > ___ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- -- Bob Paauwe bob.j.paa...@intel.com IOTG / PED Software Organization Intel Corp. Folsom, CA (916) 356-6193 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915/gtt: Refactor common ppgtt initialisation
On Fri, 15 Mar 2019 09:09:11 + Chris Wilson wrote: > Quoting Rodrigo Vivi (2019-03-14 22:53:44) > > On Thu, Mar 14, 2019 at 10:38:39PM +, Chris Wilson wrote: > > > The basic setup of the i915_hw_ppgtt is the same between gen6 and gen8, > > > so refactor that into a common routine. > > > > > > Signed-off-by: Chris Wilson > > > Cc: Bob Paauwe > > > Cc: Matthew Auld > > > Cc: Joonas Lahtinen > > > > Reviewed-by: Rodrigo Vivi > > I've pushed this series so that 36 bits should be a nice and simple drop > in. > > Thank you Bob for preparing these, sorry for not being clear enough on > the direction I felt the patches should take. > -Chris Thanks Chris, It was helpful to see how you organized and re-wrote the series. This was not code I was familiar with when I started so you're guidance helped a lot. Now I get to fix the EHL patches to take advantage of this. Bob > ___ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- -- Bob Paauwe bob.j.paa...@intel.com IOTG / PED Software Organization Intel Corp. Folsom, CA (916) 356-6193 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v3)
Chris, Any thoughts on how I can best address your comment on this patch? Bob On Thu, 7 Feb 2019 11:13:15 -0800 Bob Paauwe wrote: > On Thu, 7 Feb 2019 16:41:58 + > Chris Wilson wrote: > > > Quoting Bob Paauwe (2019-02-07 16:29:53) > > > With the address range being specified for each platform, we can use > > > that instead of the .ppgtt enum to handle the differences between > > > 3 level and 4 level PPGTT. In most cases, we really only care if the > > > platform supports PPGTT or not. Because of this, we can now remove > > > the HAS_FULL_PPGTT macro and the device info ppgtt field. > > > > > > Aliasing PPGTT used by GEN 6 is a bit of an exception. For those cases, > > > it makes just as much sense to check if we're running on GEN 6 as it > > > does to check a device info flag. > > > > > > v2: Reword the commit message to make it correct wrt aliasing ppgtt > > > (Chris) > > > v3: Rebase on current drm-tip > > > > The point of adding the type into the device_info was that it was > > included in the error state so that I didn't have to remember which w/a > > applied to which gen. gen6 has full-ppgtt, we can't enabled it as no one > > has solved how to make it work. > > -Chris > > OK, I had assumed that the point was to control the code flow so I'm > not sure how best to proceed. > > This patch doesn't really change any program logic so we can drop it > and keep both the ppgtt type and size in device info. > > Alternately, I could add the ppgtt size to error state output. But I'm > not sure that really provides what you're looking for wrt gen6. > > If you have a better idea or something specific you'd like to see me do > with this, I could use some direction. > > Thanks, > Bob > -- Bob Paauwe bob.j.paa...@intel.com IOTG / PED Software Organization Intel Corp. Folsom, CA (916) 356-6193 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [CI 6/6] drm/i915/ehl: Add Support for DMC on EHL
On Fri, 15 Mar 2019 10:57:11 -0700
Rodrigo Vivi wrote:
> From: Anusha Srivatsa
>
> EHL uses the same firmware as ICL.
Reviewed-by: Bob Paauwe
>
> Cc: Bob Paauwe
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Rodrigo Vivi
> Reviewed-by: Lucas De Marchi
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20190313211144.4842-9-rodrigo.v...@intel.com
> ---
> drivers/gpu/drm/i915/intel_csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index e8ac04c33e29..862a8f686ef5 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -486,7 +486,7 @@ void intel_csr_ucode_init(struct drm_i915_private
> *dev_priv)
> if (INTEL_GEN(dev_priv) >= 12) {
> /* Allow to load fw via parameter using the last known size */
> csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> - } else if (IS_ICELAKE(dev_priv)) {
> + } else if (IS_GEN(dev_priv, 11)) {
> csr->fw_path = ICL_CSR_PATH;
> csr->required_version = ICL_CSR_VERSION_REQUIRED;
> csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
--
--
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/ehl: Add EHL platform info and PCI IDs
On Fri, 15 Mar 2019 12:32:22 -0700
"Souza, Jose" wrote:
> On Fri, 2019-03-15 at 12:19 -0700, Rodrigo Vivi wrote:
> > From: James Ausmus
> >
> > Add known EHL PCI IDs.
> >
> > v2 (Rodrigo): Removed x86 early quirk. To be sent in a separated
> > patch cc'ing the appropriated list and maintainers for
> > proper ack.
> > v3: (Rodrigo): - Removed .num_pipes = 3 that is coming since
> > GEN&_FEATURES.
> >- Added ppgtt type and size after rework from Bob and
> > Chris
> >
> > Cc: Bob Paauwe
> > Cc: Chris Wilson
> > Cc: José Roberto de Souza
> > Signed-off-by: James Ausmus
> > Signed-off-by: Rodrigo Vivi
> > ---
> > drivers/gpu/drm/i915/i915_pci.c | 10 ++
> > include/drm/i915_pciids.h | 7 +++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index ef7410c492fd..aa26a2e9a466 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -730,6 +730,15 @@ static const struct intel_device_info
> > intel_icelake_11_info = {
> > BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) |
> > BIT(VCS2),
> > };
> >
> > +static const struct intel_device_info intel_elkhartlake_info = {
> > + GEN11_FEATURES,
> > + PLATFORM(INTEL_ICELAKE),
> > + .is_alpha_support = 1,
> > + .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
> > + .ppgtt_type = INTEL_PPGTT_FULL,
>
> Nit: You don't need to ppgtt_type it will come from GEN8.
I agree that this isn't needed
>
> Other than that:
> Reviewed-by: José Roberto de Souza
And
Reviewed-by: Bob Paauwe
>
> > + .ppgtt_size = 36,
> > +};
> > +
> > #undef GEN
> > #undef PLATFORM
> >
> > @@ -797,6 +806,7 @@ static const struct pci_device_id pciidlist[] = {
> > INTEL_WHL_U_GT3_IDS(_coffeelake_gt3_info),
> > INTEL_CNL_IDS(_cannonlake_info),
> > INTEL_ICL_11_IDS(_icelake_11_info),
> > + INTEL_EHL_IDS(_elkhartlake_info),
> > {0, 0, 0}
> > };
> > MODULE_DEVICE_TABLE(pci, pciidlist);
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index d20feeaa..a0e409e9e70d 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -472,4 +472,11 @@
> > INTEL_VGA_DEVICE(0x8A70, info), \
> > INTEL_VGA_DEVICE(0x8A53, info)
> >
> > +/* EHL */
> > +#define INTEL_EHL_IDS(info) \
> > + INTEL_VGA_DEVICE(0x4500, info), \
> > + INTEL_VGA_DEVICE(0x4571, info), \
> > + INTEL_VGA_DEVICE(0x4551, info), \
> > + INTEL_VGA_DEVICE(0x4541, info)
> > +
> > #endif /* _I915_PCIIDS_H */
--
--
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[Intel-gfx] [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2)
Unlike ICL, all of the output ports are combo phys so just return
true in intel_port_is_combophy for all EHL ports to indicate that.
v2: Return false in intel_port_is_tc since no EHL ports are TC. (Jose)
Cc: Jose Souza
Signed-off-by: Bob Paauwe
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 2b25098d47a9..094456843c4a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6170,6 +6170,9 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
if (port == PORT_NONE)
return false;
+ if (IS_ELKHARTLAKE(dev_priv))
+ return port <= PORT_C;
+
if (INTEL_GEN(dev_priv) >= 11)
return port <= PORT_B;
@@ -6178,7 +6181,7 @@ bool intel_port_is_combophy(struct drm_i915_private
*dev_priv, enum port port)
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
return port >= PORT_C && port <= PORT_F;
return false;
--
2.19.2
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[Intel-gfx] [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v3)
With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and the device info ppgtt field.
Aliasing PPGTT used by GEN 6 is a bit of an exception. For those cases,
it makes just as much sense to check if we're running on GEN 6 as it
does to check a device info flag.
v2: Reword the commit message to make it correct wrt aliasing ppgtt (Chris)
v3: Rebase on current drm-tip
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 7 ++-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 --
drivers/gpu/drm/i915/intel_device_info.c| 2 +-
drivers/gpu/drm/i915/intel_device_info.h| 7 ---
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 2 +-
10 files changed, 18 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2a7bd202f7d8..aab84baac8bc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -346,7 +346,12 @@ static int i915_getparam_ioctl(struct drm_device *dev,
void *data,
value = HAS_WT(dev_priv);
break;
case I915_PARAM_HAS_ALIASING_PPGTT:
- value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
+ if (INTEL_GEN(dev_priv) < 6)
+ value = I915_GEM_PPGTT_NONE;
+ else if (INTEL_GEN(dev_priv) == 6)
+ value = I915_GEM_PPGTT_ALIASING;
+ else
+ value = I915_GEM_PPGTT_FULL;
break;
case I915_PARAM_HAS_SEMAPHORES:
value = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 641b4ced3725..9255b2e3375f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2449,11 +2449,13 @@ static inline unsigned int i915_sg_segment_size(void)
#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
-#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt)
+#define INTEL_PPGTT_BITS(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_bits)
#define HAS_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
+ (INTEL_PPGTT_BITS(dev_priv) != 0)
+/*
#define HAS_FULL_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+ (INTEL_PPGTT_BITS(dev_priv) >= 31)
+*/
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 42e1248a90da..ea71a5a7a483 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -437,7 +437,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
if (IS_ERR(ctx))
return ctx;
- if (HAS_FULL_PPGTT(dev_priv)) {
+ if (INTEL_GEN(dev_priv) > 6) {
struct i915_hw_ppgtt *ppgtt;
ppgtt = i915_ppgtt_create(dev_priv, file_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f2b634e6cf9d..fa59b7992d80 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2754,7 +2754,7 @@ int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
/* And finally clear the reserved guard page */
ggtt->vm.clear_range(>vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
- if (INTEL_PPGTT(dev_priv) == INTEL_PPGTT_ALIASING) {
+ if (INTEL_GEN(dev_priv) == 6) {
ret = i915_gem_init_aliasing_ppgtt(dev_priv);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f18929637bd5..bd8cd790e1b1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -288,7 +288,6 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_ALIASING, \
.ppgtt_bits = 31, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
@@ -334,7 +333,6 @@ static const struct intel_device_info
intel_sandybridge_m_gt2_info = {
.has_llc = 1, \
.has_rc6 = 1, \
.has_rc6p = 1, \
- .ppgtt = INTEL_PPGTT_FULL, \
.ppgtt_bits = 31, \
GEN_DEFAULT_PIPEOFFSETS, \
GEN_DEFAULT_PAGE_SIZES, \
@@ -388,7 +3
[Intel-gfx] [PATCH 1/3] drm/i915: Make 48bit full ppgtt configuration generic (v11)
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that specifies the number of
bits to prepare for cases where the range is not 32 or 48 bits.
Also rename other functions and comments from 48bit to 4-level.
Making use of the device info address range for gen6 highlights
simularities in the gen6 and gen8 code paths so move the common
code in to a common function.
v2: Keep HAS_FULL_PPGTT() unchanged (Chris)
v3: Simplify condition in gen8_ppgtt_create() (Chris)
Remove unnecessary line coninuations (Bob)
Rename functions/defines/comments from 48bit to 4lvl (Rodrigo/Bob)
v4: Rename FULL_4LVL_PPGTT to simply 4LVL_PPGTT (Rodrigo)
Be explised in setting vm.total to 1ULL << 32 (Rodrigo)
Gen 7 is 31 bits, not 32 (Chris)
v5: Mock device is 64b(63b) not 48b (Chris)
v6: Rebase to latest drm-tip (Bob)
v7: Combine common code for gen6/gen8 ppgtt create (Chris)
Improve comment on device info field (Chris)
v8: gvt is actually full ppgtt (both 3-lvl and 4-lvl) so name cap
define appropriately (Chris)
v9: rebase on latest
v10: fix missed vgpu change of FULL_48BIT to FULL in CAPS define (Bob)
v11: rebase on current drm-tip
Signed-off-by: Bob Paauwe
CC: Rodrigo Vivi
CC: Michel Thierry
CC: Chris Wilson
---
drivers/gpu/drm/i915/gvt/scheduler.c | 4 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 130 --
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +
drivers/gpu/drm/i915/i915_pvinfo.h| 2 +-
drivers/gpu/drm/i915/i915_vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_vgpu.h | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 8 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 2 +
15 files changed, 85 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
b/drivers/gpu/drm/i915/gvt/scheduler.c
index 1bb8f936fdaa..5bcb3fa9e612 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1102,7 +1102,7 @@ i915_context_ppgtt_root_restore(struct
intel_vgpu_submission *s)
struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
int i;
- if (i915_vm_is_48bit(_ppgtt->vm))
+ if (i915_vm_is_4lvl(_ppgtt->vm))
px_dma(_ppgtt->pml4) = s->i915_context_pml4;
else {
for (i = 0; i < GEN8_3LVL_PDPES; i++)
@@ -1155,7 +1155,7 @@ i915_context_ppgtt_root_save(struct intel_vgpu_submission
*s)
struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt;
int i;
- if (i915_vm_is_48bit(_ppgtt->vm))
+ if (i915_vm_is_4lvl(_ppgtt->vm))
s->i915_context_pml4 = px_dma(_ppgtt->pml4);
else {
for (i = 0; i < GEN8_3LVL_PDPES; i++)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 720e2b10adaa..314e40121e47 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -44,7 +44,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
- vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
+ vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7de90701f6f1..2a7bd202f7d8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1379,7 +1379,7 @@ static int i915_driver_init_hw(struct drm_i915_private
*dev_priv)
if (HAS_PPGTT(dev_priv)) {
if (intel_vgpu_active(dev_priv) &&
- !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
+ !intel_vgpu_has_4lvl_ppgtt(dev_priv)) {
i915_report_error(dev_priv,
"incompatible vGPU found, support for
isolated ppGTT required\n");
return -ENXIO;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2293152cb6a..46bbbed14efd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu
[Intel-gfx] [PATCH 2/3] drm/i915: Remove HAS_4LVL_PPGTT
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
CC: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/intel_device_info.h| 1 -
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
4 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 46bbbed14efd..641b4ced3725 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2454,8 +2454,6 @@ static inline unsigned int i915_sg_segment_size(void)
(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
#define HAS_FULL_PPGTT(dev_priv) \
(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
-#define HAS_4LVL_PPGTT(dev_priv) \
- (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL_4LVL)
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
GEM_BUG_ON((sizes) == 0); \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 216ed2b1f6aa..f18929637bd5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -436,7 +436,7 @@ static const struct intel_device_info
intel_haswell_gt3_info = {
.page_sizes = I915_GTT_PAGE_SIZE_4K | \
I915_GTT_PAGE_SIZE_2M, \
.has_logical_ring_contexts = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt = INTEL_PPGTT_FULL, \
.ppgtt_bits = 48, \
.has_64bit_reloc = 1, \
.has_reset_engine = 1
@@ -557,7 +557,7 @@ static const struct intel_device_info
intel_skylake_gt4_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_guc = 1, \
- .ppgtt = INTEL_PPGTT_FULL_4LVL, \
+ .ppgtt = INTEL_PPGTT_FULL, \
.ppgtt_bits = 48, \
.has_reset_engine = 1, \
.has_snoop = true, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 504530fce673..f6a4ce0f9cb5 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -80,7 +80,6 @@ enum intel_ppgtt {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
- INTEL_PPGTT_FULL_4LVL,
};
#define DEV_INFO_FOR_EACH_FLAG(func) \
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c
b/drivers/gpu/drm/i915/selftests/huge_pages.c
index c79be88d68b7..9f90179df185 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -1709,7 +1709,7 @@ int i915_gem_huge_page_mock_selftests(void)
return -ENOMEM;
/* Pretend to be a device which supports the 48b PPGTT */
- mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL_4LVL;
+ mkwrite_device_info(dev_priv)->ppgtt = INTEL_PPGTT_FULL;
mutex_lock(_priv->drm.struct_mutex);
ppgtt = i915_ppgtt_create(dev_priv, ERR_PTR(-ENODEV));
--
2.19.2
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Re: [Intel-gfx] [PATCH 3/3] drm/i915: Remove HAS_FULL_PPGTT and device_info.ppgtt enum (v3)
On Thu, 7 Feb 2019 16:41:58 + Chris Wilson wrote: > Quoting Bob Paauwe (2019-02-07 16:29:53) > > With the address range being specified for each platform, we can use > > that instead of the .ppgtt enum to handle the differences between > > 3 level and 4 level PPGTT. In most cases, we really only care if the > > platform supports PPGTT or not. Because of this, we can now remove > > the HAS_FULL_PPGTT macro and the device info ppgtt field. > > > > Aliasing PPGTT used by GEN 6 is a bit of an exception. For those cases, > > it makes just as much sense to check if we're running on GEN 6 as it > > does to check a device info flag. > > > > v2: Reword the commit message to make it correct wrt aliasing ppgtt (Chris) > > v3: Rebase on current drm-tip > > The point of adding the type into the device_info was that it was > included in the error state so that I didn't have to remember which w/a > applied to which gen. gen6 has full-ppgtt, we can't enabled it as no one > has solved how to make it work. > -Chris OK, I had assumed that the point was to control the code flow so I'm not sure how best to proceed. This patch doesn't really change any program logic so we can drop it and keep both the ppgtt type and size in device info. Alternately, I could add the ppgtt size to error state output. But I'm not sure that really provides what you're looking for wrt gen6. If you have a better idea or something specific you'd like to see me do with this, I could use some direction. Thanks, Bob -- -- Bob Paauwe bob.j.paa...@intel.com IOTG / PED Software Organization Intel Corp. Folsom, CA (916) 356-6193 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Configurable GT idle frequency
There are real-time use cases where having deterministic CPU processes
can be more important than GPU power/performance. Parking the GPU at a
specific freqency by setting idle, min and max prohibits the normal
dynamic GPU frequency switching which can introduce significant PCI-E
latency. This adds the ability to configure the GPU "idle" frequecy
using the same method that already exists for minimum and maximum
frequencies.
In addition, parking the idle frequency may reduce spool up latencies
on GPU workloads.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_sysfs.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 41313005af42..62612c23d514 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -454,11 +454,69 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
return ret ?: count;
}
+static ssize_t gt_idle_freq_mhz_show(struct device *kdev, struct
device_attribute *attr, char *buf)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->gt_pm.rps.idle_freq));
+}
+
+static ssize_t gt_idle_freq_mhz_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
+ struct intel_rps *rps = _priv->gt_pm.rps;
+ intel_wakeref_t wakeref;
+ u32 val;
+ ssize_t ret;
+
+ ret = kstrtou32(buf, 0, );
+ if (ret)
+ return ret;
+
+ wakeref = intel_runtime_pm_get(dev_priv);
+
+ mutex_lock(_priv->pcu_lock);
+
+ val = intel_freq_opcode(dev_priv, val);
+
+ if (val < rps->min_freq ||
+ val > rps->max_freq ||
+ val > rps->max_freq_softlimit) {
+ mutex_unlock(_priv->pcu_lock);
+ intel_runtime_pm_put(dev_priv, wakeref);
+ return -EINVAL;
+ }
+
+ rps->idle_freq = val;
+
+ val = clamp_t(int, rps->cur_freq,
+ rps->idle_freq,
+ rps->max_freq_softlimit);
+
+ /*
+* If the current freq is at the old idle freq we should
+* ajust it to the new idle. Calling *_set_rps will also
+* update the interrupt limits and PMINTRMSK if ncessary.
+*/
+ ret = intel_set_rps(dev_priv, val);
+
+ mutex_unlock(_priv->pcu_lock);
+
+ intel_runtime_pm_put(dev_priv, wakeref);
+
+ return ret ?: count;
+}
+
static DEVICE_ATTR_RO(gt_act_freq_mhz);
static DEVICE_ATTR_RO(gt_cur_freq_mhz);
static DEVICE_ATTR_RW(gt_boost_freq_mhz);
static DEVICE_ATTR_RW(gt_max_freq_mhz);
static DEVICE_ATTR_RW(gt_min_freq_mhz);
+static DEVICE_ATTR_RW(gt_idle_freq_mhz);
static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
@@ -492,6 +550,7 @@ static const struct attribute * const gen6_attrs[] = {
_attr_gt_boost_freq_mhz.attr,
_attr_gt_max_freq_mhz.attr,
_attr_gt_min_freq_mhz.attr,
+ _attr_gt_idle_freq_mhz.attr,
_attr_gt_RP0_freq_mhz.attr,
_attr_gt_RP1_freq_mhz.attr,
_attr_gt_RPn_freq_mhz.attr,
@@ -504,6 +563,7 @@ static const struct attribute * const vlv_attrs[] = {
_attr_gt_boost_freq_mhz.attr,
_attr_gt_max_freq_mhz.attr,
_attr_gt_min_freq_mhz.attr,
+ _attr_gt_idle_freq_mhz.attr,
_attr_gt_RP0_freq_mhz.attr,
_attr_gt_RP1_freq_mhz.attr,
_attr_gt_RPn_freq_mhz.attr,
--
2.19.2
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Re: [Intel-gfx] [PATCH] drm/i915: Configurable GT idle frequency
On Mon, 15 Apr 2019 17:33:30 -0700
Vanshidhar Konda wrote:
> On Mon, Apr 15, 2019 at 04:05:26PM -0700, Bob Paauwe wrote:
> >There are real-time use cases where having deterministic CPU processes
> >can be more important than GPU power/performance. Parking the GPU at a
> >specific freqency by setting idle, min and max prohibits the normal
> >dynamic GPU frequency switching which can introduce significant PCI-E
> >latency. This adds the ability to configure the GPU "idle" frequecy
> >using the same method that already exists for minimum and maximum
> >frequencies.
> >
> >In addition, parking the idle frequency may reduce spool up latencies
> >on GPU workloads.
> >
> >Signed-off-by: Bob Paauwe
> >---
> > drivers/gpu/drm/i915/i915_sysfs.c | 60 +++
> > 1 file changed, 60 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
> >b/drivers/gpu/drm/i915/i915_sysfs.c
> >index 41313005af42..62612c23d514 100644
> >--- a/drivers/gpu/drm/i915/i915_sysfs.c
> >+++ b/drivers/gpu/drm/i915/i915_sysfs.c
> >@@ -454,11 +454,69 @@ static ssize_t gt_min_freq_mhz_store(struct device
> >*kdev,
> > return ret ?: count;
> > }
> >
> >+static ssize_t gt_idle_freq_mhz_show(struct device *kdev, struct
> >device_attribute *attr, char *buf)
> >+{
> >+struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> >+
> >+return snprintf(buf, PAGE_SIZE, "%d\n",
> >+intel_gpu_freq(dev_priv,
> >+ dev_priv->gt_pm.rps.idle_freq));
> >+}
> >+
> >+static ssize_t gt_idle_freq_mhz_store(struct device *kdev,
> >+ struct device_attribute *attr,
> >+ const char *buf, size_t count)
> >+{
> >+struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> >+struct intel_rps *rps = _priv->gt_pm.rps;
> >+intel_wakeref_t wakeref;
> >+u32 val;
>
> val can probably just be u8. max_freq, min_freq, etc. are only u8 in
> struct intel_rps *rps.
Using u32 is consistent with all the other _store functions in the file
and changing it would also mean changing the kstrtou32 call below. I'd
rather this function stay consistent with the min/max/boost frequency
functions. Changing to u8 would be a separate change and should be
applied to all the similar functions.
>
> >+ssize_t ret;
> >+
> >+ret = kstrtou32(buf, 0, );
> >+if (ret)
> >+return ret;
> >+
> >+wakeref = intel_runtime_pm_get(dev_priv);
> >+
> >+mutex_lock(_priv->pcu_lock);
> >+
> >+val = intel_freq_opcode(dev_priv, val);
> >+
> >+if (val < rps->min_freq ||
> >+val > rps->max_freq ||
> >+val > rps->max_freq_softlimit) {
> >+mutex_unlock(_priv->pcu_lock);
> >+intel_runtime_pm_put(dev_priv, wakeref);
> >+return -EINVAL;
> >+}
> >+
> >+rps->idle_freq = val;
> >+
> >+val = clamp_t(int, rps->cur_freq,
> >+ rps->idle_freq,
> >+ rps->max_freq_softlimit);
>
> This should probably be clamped to u8 instead of int.
Similar to above, this is consistent with the other similar functions.
>
> Vanshi
>
> >+
> >+/*
> >+ * If the current freq is at the old idle freq we should
> >+ * ajust it to the new idle. Calling *_set_rps will also
> >+ * update the interrupt limits and PMINTRMSK if ncessary.
> >+ */
> >+ret = intel_set_rps(dev_priv, val);
> >+
> >+mutex_unlock(_priv->pcu_lock);
> >+
> >+intel_runtime_pm_put(dev_priv, wakeref);
> >+
> >+return ret ?: count;
> >+}
> >+
> > static DEVICE_ATTR_RO(gt_act_freq_mhz);
> > static DEVICE_ATTR_RO(gt_cur_freq_mhz);
> > static DEVICE_ATTR_RW(gt_boost_freq_mhz);
> > static DEVICE_ATTR_RW(gt_max_freq_mhz);
> > static DEVICE_ATTR_RW(gt_min_freq_mhz);
> >+static DEVICE_ATTR_RW(gt_idle_freq_mhz);
> >
> > static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
> >
> >@@ -492,6 +550,7 @@ static const struct attribute * const gen6_attrs[] = {
> > _attr_gt_boost_freq_mhz.attr,
> > _attr_gt_max_freq_mhz.attr,
> > _attr_gt_min_freq_mhz.attr,
> >+_attr_gt_idle_freq_mhz.attr,
> > _attr_gt_RP0_freq_mhz.attr,
> > _attr_gt_RP1_freq_mhz.attr,
> > _attr_gt_RPn_freq_mhz.attr,
> >@@ -504,6 +563,7 @@ static const str
Re: [Intel-gfx] [PATCH] drm/i915/ehl: inherit icl cdclk init/uninit
On Tue, 16 Apr 2019 11:28:52 +0300
Jani Nikula wrote:
> The cdclk init/uninit code was changed by commit 93a643f29bcb
> ("drm/i915/cdclk: have only one init/uninit function") between the
> versions of commit 39564ae86d51 ("drm/i915/ehl: Inherit Ice Lake
> conditional code"). What got merged fails to do cdclk init/uninit on
> ehl.
Good catch!
Reviewed-by: Bob Paauwe
>
> Fixes: 39564ae86d51 ("drm/i915/ehl: Inherit Ice Lake conditional code")
> Cc: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: Bob Paauwe
> Cc: Rodrigo Vivi
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 7f060ea..ae40a86 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -2034,7 +2034,7 @@ static void cnl_uninit_cdclk(struct drm_i915_private
> *dev_priv)
> */
> void intel_cdclk_init(struct drm_i915_private *i915)
> {
> - if (IS_ICELAKE(i915))
> + if (INTEL_GEN(i915) >= 11)
> icl_init_cdclk(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_init_cdclk(i915);
> @@ -2053,7 +2053,7 @@ void intel_cdclk_init(struct drm_i915_private *i915)
> */
> void intel_cdclk_uninit(struct drm_i915_private *i915)
> {
> - if (IS_ICELAKE(i915))
> + if (INTEL_GEN(i915) >= 11)
> icl_uninit_cdclk(i915);
> else if (IS_CANNONLAKE(i915))
> cnl_uninit_cdclk(i915);
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
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Re: [Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v4)
On Thu, 11 Apr 2019 16:36:00 -0700
Vivek Kasireddy wrote:
> This patch adds support for DPLL4 on EHL that include the
> following restrictions:
>
> - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> DPLL4 can be used with other DDIs, including DDID
> (combo port A external usage).
>
> - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
>
> - The DPLL4 enable, lock, power enabled, and power state are connected
> to the MGPLL1_ENABLE register.
>
> v2: (suggestions from Bob Paauwe)
> - Rework ehl_get_dpll() function to call intel_find_shared_dpll() and
> iterate twice: once for Combo plls and once for MG plls.
>
> - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> mg_pll_enable to include the restrictions for EHL.
>
> v3: Fix compilation error
>
> v4: (suggestions from Lucas and Ville)
> - Treat DPLL4 as a combo phy PLL and not as MG PLL
> - Disable DC states when this DPLL is being enabled
> - Reuse icl_get_dpll instead of creating a separate one for EHL
>
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
> Cc: Bob Paauwe
> Signed-off-by: Vivek Kasireddy
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 35
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 4
> 2 files changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e01c057ce50b..207af4af4978 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2825,6 +2825,12 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
> if (intel_port_is_combophy(dev_priv, port)) {
> min = DPLL_ID_ICL_DPLL0;
> max = DPLL_ID_ICL_DPLL1;
> +
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + max = DPLL_ID_EHL_DPLL4;
> + }
> +
> ret = icl_calc_dpll_state(crtc_state, encoder);
> } else if (intel_port_is_tc(dev_priv, port)) {
> if (encoder->type == INTEL_OUTPUT_DP_MST) {
> @@ -2964,8 +2970,14 @@ static bool combo_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll,
> struct intel_dpll_hw_state *hw_state)
> {
> - return icl_pll_get_hw_state(dev_priv, pll, hw_state,
> - CNL_DPLL_ENABLE(pll->info->id));
> + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> +
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> + }
> +
> + return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
> }
>
> static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
> @@ -3076,6 +3088,14 @@ static void combo_pll_enable(struct drm_i915_private
> *dev_priv,
> {
> i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
>
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> +
> + /* Need to disable DC states when this DPLL is enabled. */
> + bxt_disable_dc9(dev_priv);
> + }
> +
> icl_pll_power_enable(dev_priv, pll, enable_reg);
>
> icl_dpll_write(dev_priv, pll);
> @@ -3171,7 +3191,15 @@ static void icl_pll_disable(struct drm_i915_private
> *dev_priv,
> static void combo_pll_disable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
> + i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
> +
> + if (IS_ELKHARTLAKE(dev_priv) &&
> + pll->info->id == DPLL_ID_EHL_DPLL4) {
> + enable_reg = MG_PLL_ENABLE(0);
> + bxt_enable_dc9(dev_priv);
dc9 is disabled before the DPLL is enabled and here, you're also
enabling before the DPLL has been disabled. Is that OK?
If the order here is fine then
Reviewed-by: Bob Paauwe
> + }
> +
> + icl_pll_disable(dev_priv, pll, enable_reg);
> }
>
> static void tbt_pll_disable(struct drm_i915_private *dev_priv,
> @@ -3249,6 +3277,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = {
> static const struct dpll_info ehl_plls[] = {
> { "DPLL 0", _pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
> { "DPLL 1", _pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
> + { &quo
Re: [Intel-gfx] [PATCH] drm/i915: Configurable GT idle frequency
On Tue, 16 Apr 2019 16:56:26 +0100 Chris Wilson wrote: > Quoting Bob Paauwe (2019-04-16 00:05:26) > > There are real-time use cases where having deterministic CPU processes > > can be more important than GPU power/performance. Parking the GPU at a > > specific freqency by setting idle, min and max prohibits the normal > > dynamic GPU frequency switching which can introduce significant PCI-E > > latency. This adds the ability to configure the GPU "idle" frequecy > > using the same method that already exists for minimum and maximum > > frequencies. > > What exactly is the problem? We never use idle frequency while active, > always restarting at max(cur, rpe). So for the simple minded among us, > where is the igt demonstrating the issue? > -Chris To follow up and close this. When I requested more details on the use case and data for this request, I was informed that a different solution is being pursued and this patch is no longer needed. Thanks for the reviews and comments. Bob -- -- Bob Paauwe bob.j.paa...@intel.com IOTG / PED Software Organization Intel Corp. Folsom, CA (916) 356-6193 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 12bb8f951edf..7b9fb9e7893d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2978,6 +2978,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -3988,6 +3990,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -5581,6 +5585,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7a7078d0ba23..b30809b28e17 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2015,6 +2015,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2031,6 +2032,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2273,6 +2275,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..20cdffc23a95 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6656,7 +6656,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
--
2.21.0
___
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[Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
This has been updated to support GEN11 along with rebasing it to
the latest drm-tip. A patch to igt has also been posted that gives
igt the ability to test this format.
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 9dce2e9e5376..2018e2714c78 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2996,6 +2996,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4070,6 +4072,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -5669,6 +5673,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index edc41fc40726..a0e6e7717a65 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2412,6 +2412,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2430,6 +2431,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2497,6 +2499,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2526,6 +2529,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2676,6 +2680,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fb33b164ce55..88cfb22df3dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6687,7 +6687,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 <<
[Intel-gfx] [PATCH] lib/color_encoding: Fix up support for XYUV format.
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib/igt_color_encoding.c
index 7de6d5ab..a7bd2b22 100644
--- a/lib/igt_color_encoding.c
+++ b/lib/igt_color_encoding.c
@@ -160,6 +160,7 @@ static const struct color_encoding_format {
{ DRM_FORMAT_XVYU2101010, 1023.f, 64.f, 940.f, 64.f, 512.f, 960.f },
{ DRM_FORMAT_XVYU12_16161616, 65520.f, 4096.f, 60160.f, 4096.f,
32768.f, 61440.f },
{ DRM_FORMAT_XVYU16161616, 65535.f, 4096.f, 60160.f, 4096.f, 32768.f,
61440.f },
+ { DRM_FORMAT_XYUV, 255.f, 16.f, 235.f, 16.f, 128.f, 240.f },
};
static const struct color_encoding_format *lookup_fourcc(uint32_t fourcc)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 4adca967..fe5fa74b 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2423,9 +2423,9 @@ static void get_yuv_parameters(struct igt_fb *fb, struct
yuv_parameters *params)
break;
case DRM_FORMAT_XYUV:
- params->y_offset = fb->offsets[0] + 1;
- params->u_offset = fb->offsets[0] + 2;
- params->v_offset = fb->offsets[0] + 3;
+ params->y_offset = fb->offsets[0] + 2;
+ params->u_offset = fb->offsets[0] + 1;
+ params->v_offset = fb->offsets[0] + 0;
break;
}
}
--
2.21.0
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Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Adding YUV444 packed format support for skl+ (rev4)
sues [91]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb5/igt@perf_...@busy-no-semaphores-vcs1.html
> [92]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-iclb4/igt@perf_...@busy-no-semaphores-vcs1.html
>
>
> Warnings
>
> * igt@gem_ctx_isolation@vcs1-nonpriv:
> - shard-iclb: [SKIP][93] ([fdo#112080]) -> [FAIL][94]
> ([IGT#28]) [93]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-iclb8/igt@gem_ctx_isolat...@vcs1-nonpriv.html
> [94]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-iclb1/igt@gem_ctx_isolat...@vcs1-nonpriv.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-tglb: [SKIP][95] ([i915#468]) -> [FAIL][96]
> ([i915#454]) [95]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-tglb2/igt@i915_pm...@dc6-psr.html
> [96]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-tglb8/igt@i915_pm...@dc6-psr.html
>
> * igt@kms_flip@flip-vs-expired-vblank:
> - shard-skl: [FAIL][97] ([i915#46]) -> [FAIL][98]
> ([i915#79]) [97]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8023/shard-skl10/igt@kms_f...@flip-vs-expired-vblank.html
> [98]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/shard-skl6/igt@kms_f...@flip-vs-expired-vblank.html
>
>
> {name}: This element is suppressed. This means it is ignored when
> computing the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
> [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
> [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
> [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
> [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
> [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
> [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
> [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197
> [i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239
> [i915#1333]: https://gitlab.freedesktop.org/drm/intel/issues/1333
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
> [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
> [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
> [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
> [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
> [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
> [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
> [i915#836]: https://gitlab.freedesktop.org/drm/intel/issues/836
> [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
>
>
> Participating hosts (10 -> 10)
> --
>
> No changes in participating hosts
>
>
> Build changes
> -
>
> * CI: CI-20190529 -> None
> * IGT: IGT_5474 -> IGTPW_4011
> * Linux: CI_DRM_8023 -> Patchwork_16744
>
> CI-20190529: 20190529
> CI_DRM_8023: fa9a02bbdfd6553ee633171f23183a115d0da577 @
> git://anongit.freedesktop.org/gfx-ci/linux IGTPW_4011:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4011/index.html
> IGT_5474: 1be610f852de155cd915e7cda65cb2737adf04d4 @
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_16744: 8e8ab83649cddfd4640699468df891986565b31b @
> git://anongit.freedesktop.org/gfx-ci/linux piglit_4509:
> fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16744/index.html
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
___
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[Intel-gfx] [PATCH 0/1] Adding YUV444 packed format support for skl+
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com Stanislav Lisovskiy (1): drm/i915: Adding YUV444 packed format support for skl+ (V15) drivers/gpu/drm/i915/display/intel_display.c | 5 + drivers/gpu/drm/i915/display/intel_sprite.c | 8 drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 14 insertions(+), 1 deletion(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V15)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
V14: Added format to TGL format lists.
Rebased.
V15: Added format to glk_planar_formats[] and icl_sdr_y_plane_formats[] (Ville)
Placed XYUV before XXVYU2101010 to be more consistent (Ville)
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 61ba1f2256a0..919270b7e240 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3331,6 +3331,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4570,6 +4572,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6186,6 +6190,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7abeefe8dce5..18f6e0363cc0 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2483,6 +2483,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2501,6 +2502,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2519,6 +2521,7 @@ static const u32 glk_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_P010,
DRM_FORMAT_P012,
DRM_FORMAT_P016,
@@ -2542,6 +2545,7 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_Y210,
DRM_FORMAT_Y212,
DRM_FORMAT_Y216,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
@@ -2569,6 +2573,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_Y210,
DRM_FORMAT_Y212,
DRM_FORMAT_Y216,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
@@ -2600,6 +2605,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_Y210,
DRM_FORMAT_Y212,
DRM_FORMAT_Y216,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
@@ -2770,6 +2776,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
@@ -2834,6 +2841,7 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane
[Intel-gfx] [PATCH i-g-t] lib/color_encoding: Fix up support for XYUV format
Add XYUV to the list of DRM Formats to test.
Also fix the byte order for the format.
Signed-off-by: Bob Paauwe
Reviewed-by: Uma Shankar
---
lib/igt_color_encoding.c | 1 +
lib/igt_fb.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/lib/igt_color_encoding.c b/lib/igt_color_encoding.c
index 7de6d5ab..a7bd2b22 100644
--- a/lib/igt_color_encoding.c
+++ b/lib/igt_color_encoding.c
@@ -160,6 +160,7 @@ static const struct color_encoding_format {
{ DRM_FORMAT_XVYU2101010, 1023.f, 64.f, 940.f, 64.f, 512.f, 960.f },
{ DRM_FORMAT_XVYU12_16161616, 65520.f, 4096.f, 60160.f, 4096.f,
32768.f, 61440.f },
{ DRM_FORMAT_XVYU16161616, 65535.f, 4096.f, 60160.f, 4096.f, 32768.f,
61440.f },
+ { DRM_FORMAT_XYUV, 255.f, 16.f, 235.f, 16.f, 128.f, 240.f },
};
static const struct color_encoding_format *lookup_fourcc(uint32_t fourcc)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index c81b9de8..7409e6b3 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -2634,9 +2634,9 @@ static void get_yuv_parameters(struct igt_fb *fb, struct
yuv_parameters *params)
break;
case DRM_FORMAT_XYUV:
- params->y_offset = fb->offsets[0] + 1;
- params->u_offset = fb->offsets[0] + 2;
- params->v_offset = fb->offsets[0] + 3;
+ params->y_offset = fb->offsets[0] + 2;
+ params->u_offset = fb->offsets[0] + 1;
+ params->v_offset = fb->offsets[0] + 0;
break;
}
}
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Adding YUV444 packed format support for skl+ (V13)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 5 +
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7f94d5ca4207..b9f993769a4a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3328,6 +3328,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4538,6 +4540,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6147,6 +6151,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2f277d1fc6f1..aafe04b29a61 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2470,6 +2470,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2488,6 +2489,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2559,6 +2561,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2590,6 +2593,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2757,6 +2761,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b93c4c18f05c..b3848e73de29 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6764,7 +6764,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV(8 << 24)
+#define PLANE_CTL_FORMAT_XYUV(8 << 24)
#define PLANE_CTL_FORMAT_INDEXED (12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 (14 << 24)
#define ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
--
2.21.0
___
Intel-gfx ma
[Intel-gfx] [PATCH 0/1] Adding YUV444 packed format support for skl+
Test-with: 20200127192859.20029-1-bob.j.paa...@intel.com Stanislav Lisovskiy (1): drm/i915: Adding YUV444 packed format support for skl+ (V14) drivers/gpu/drm/i915/display/intel_display.c | 5 + drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++ drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 12 insertions(+), 1 deletion(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V14)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
V14: Added format to TGL format lists.
Rebased.
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 61ba1f2256a0..919270b7e240 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3331,6 +3331,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4570,6 +4572,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6186,6 +6190,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7abeefe8dce5..8a95a1e7448a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2483,6 +2483,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2501,6 +2502,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2572,6 +2574,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u32 icl_hdr_plane_formats[] = {
@@ -2603,6 +2606,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
+ DRM_FORMAT_XYUV,
};
static const u64 skl_plane_format_modifiers_noccs[] = {
@@ -2770,6 +2774,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
@@ -2834,6 +2839,7 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..17e6453d31d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6768,7 +6768,7 @@ enum {
#define PLANE_CTL_FORMAT_P012(5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F (6 << 24)
#define PLANE_CTL_FORMAT_P016(7 << 24)
-#define PLANE_CTL_FORMAT_AYUV
[Intel-gfx] [PATCH 1/1] drm/i915: Adding YUV444 packed format support for skl+ (V15)
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
v4: Yet again fixed fallthrough logic, to reuse code from other case
labels.
v5: Started to use XYUV instead of AYUV, as we don't use alpha.
v6: Removed unneeded initializer for new XYUV format.
v7: Added scaling support for DRM_FORMAT_XYUV
v8: Edited commit message to be more clear about skl+, renamed
PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
doesn't support per-pixel alpha. Fixed minor code issues.
v9: Moved DRM format check to proper place in intel_framebuffer_init.
v10: Added missing XYUV format to sprite planes for skl+.
v11: Changed DRM_FORMAT_XYUV to be DRM_FORMAT_XYUV.
v12: Fixed rebase conflicts
V13: Rebased.
Added format to ICL format lists.
V14: Added format to TGL format lists.
Rebased.
V15: Added format to glk_planar_formats[] and icl_sdr_y_plane_formats[] (Ville)
Placed XYUV before XXVYU2101010 to be more consistent (Ville)
v12:
Reviewed-by: Ville Syrjälä
Reviewed-by: Matt Roper
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
drivers/gpu/drm/i915/display/intel_sprite.c | 8
drivers/gpu/drm/i915/i915_reg.h | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 70ec301fe6e3..3654262570b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3342,6 +3342,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool
alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_XYUV:
+ return DRM_FORMAT_XYUV;
case PLANE_CTL_FORMAT_P010:
return DRM_FORMAT_P010;
case PLANE_CTL_FORMAT_P012:
@@ -4586,6 +4588,8 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XRGB16161616F:
case DRM_FORMAT_ARGB16161616F:
return PLANE_CTL_FORMAT_XRGB_16161616F;
+ case DRM_FORMAT_XYUV:
+ return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
case DRM_FORMAT_YVYU:
@@ -6175,6 +6179,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index deda351719db..1a4377c988f5 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2503,6 +2503,7 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
+ DRM_FORMAT_XYUV,
};
static const u32 skl_planar_formats[] = {
@@ -2521,6 +2522,7 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
};
static const u32 glk_planar_formats[] = {
@@ -2539,6 +2541,7 @@ static const u32 glk_planar_formats[] = {
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_NV12,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_P010,
DRM_FORMAT_P012,
DRM_FORMAT_P016,
@@ -2562,6 +2565,7 @@ static const u32 icl_sdr_y_plane_formats[] = {
DRM_FORMAT_Y210,
DRM_FORMAT_Y212,
DRM_FORMAT_Y216,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
@@ -2589,6 +2593,7 @@ static const u32 icl_sdr_uv_plane_formats[] = {
DRM_FORMAT_Y210,
DRM_FORMAT_Y212,
DRM_FORMAT_Y216,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
@@ -2620,6 +2625,7 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_Y210,
DRM_FORMAT_Y212,
DRM_FORMAT_Y216,
+ DRM_FORMAT_XYUV,
DRM_FORMAT_XVYU2101010,
DRM_FORMAT_XVYU12_16161616,
DRM_FORMAT_XVYU16161616,
@@ -2790,6 +2796,7 @@ static bool skl_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_XYUV:
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
@@ -2854,6 +2861,7 @@ static bool gen12_plane_format_mod_supported(struct
drm_plane
[Intel-gfx] [PATCH 0/1] Adding YUV444 packed format support for skl+
Test-with: <20200407215146.5331-1-bob.j.paa...@intel.com> Stanislav Lisovskiy (1): drm/i915: Adding YUV444 packed format support for skl+ (V15) drivers/gpu/drm/i915/display/intel_display.c | 5 + drivers/gpu/drm/i915/display/intel_sprite.c | 8 drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 14 insertions(+), 1 deletion(-) -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
