Hi professional, This is Kishore from Agile Enterprise Solutions.
This is in reference to the following position. ***** Please find below job description if you feel comfortable please revert with updated resume, salary compensation and contact details ASAP ***** *Title: FPGA Design Engineer or Electrical Engineer* *Location: Plano, TX 75074* *Duration: 6 + months* *Client: L3 Communications* *Major Purpose:* Responsible for Electrical Engineering FPGA development with working experience in the creation, simulation, validation, and integration of programmable logic into a targeted FPGA embedded in a broad range of systems and interfaces. *Major Functions:* Programmable logic development, timing closure, verification, board level integration and validation Working on a Xilinx Zynq platform Development of or interfacing with a UVM verification environment Responsibility for design support tasks include: Requirements analysis Generate specific flow-down specifications from system level requirements Interface definition Develop test plans and procedures for FPGA integration Create all relevant design description documentation and comment records to ensure the delivery of a quality finished product Schedule, cost, and technical commitments and responsibility Engage in all phases of product development, including concept, architecture, design, and test Interface with HW/SW engineers to test and verify electrical interfaces and protocols between the FPGA and embedded system devices Perform detailed technical analyses and create test and analysis reports Participate in interdisciplinary design teams and reviews such as peer reviews, PDRs, CDRs, and other technical exchange forums Learn and follow company processes for product development, configuration management, purchasing, etc. Other duties as assigned. *Technical Skills:* • A minimum of 10 years’ experience of successful FPGA code development • Bachelor’s degree in Electrical Engineering • Proficient in VHDL code development, simulation, verification, constraints, and methods to reach timing closure • Thorough knowledge of Xilinx FPGA products and development environments • Expertise in laboratory debug techniques (proficient with oscilloscopes, logic analyzers, spectrum analyzers, signal generators, etc.) • Capable of simulation test benching within the Mentor ModelSim environment to produce bit-accurate results • Able to examine, understand, and modify existing VHDL in order to adapt functioning code to new requirements with minimal perturbation • Fundamental understanding of digital board level electrical interfaces, including ADCs, DACs, DSPs, High Speed SERDES, Flash and SDRAM. *Required Skills:* • Solid track record of planning, scheduling, and on-time execution of designs • Design experience with standard interfaces and protocols (e.g., SPI, Analog Device DSP Proprietary Link Port and PPI interfaces, Flash and SDRAM) • Proactive problem solver with great attention to detail • Excellent people skills to include collaborating in a multi-disciplinary, diverse, and dynamic team environment to debug and solve system level problems • Outstanding work ethic and commitment to organizational success • Proficient with Microsoft Office products • Excellent communication skills (written, verbal, & presentation) *Desired:* • Experience with PicoBlaze/MicroBlaze and Xilinx Zynq/Altera SoC ARM-based devices • Conversant in design verification techniques including UVM (along with System Verilog) or OSVVM. • Understanding of fundamental DSP algorithms and implementation methods • Design experience with Xilinx/third party IP interfaces (e.g., DDR2, Trimode Ethernet MAC, Rapid IO, USB 3.0, and PCIe) • Experience with Synopsys Design Constraints • Exposure to the Xilinx Vivado Design Suite • Experience with the Matlab/Simulink/System Generator Design flow • Knowledge of Altera product line and design tools, including Quartus II Design Software, Qsys, SOPC Builder • Familiarity with Tcl, Verilog, C/C++, Python • Existing DoD clearance Thanks & Regards *Kishore Nimmoju* Agile Enterprise Solutions, Inc Ph: 972-427-1824 Email : kishore_nimm...@aesinc.us.com || www.aesinc.us.com Agile Enterprise Solutions Inc || "Ensuring Client's Success"|| Note: If you have received this mail in error or prefer not to receive such emails in the future, please reply with "REMOVE" in the subject line and the email id(s) to be removed. All removal requests will be honored ASAP. We sincerely apologize -- You received this message because you are subscribed to the Google Groups "International SAP Projects" group. To unsubscribe from this group and stop receiving emails from it, send an email to international-sap-projects+unsubscr...@googlegroups.com. To post to this group, send email to international-sap-projects@googlegroups.com. Visit this group at https://groups.google.com/group/international-sap-projects. For more options, visit https://groups.google.com/d/optout.
