RE: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Thursday, October 04, 2012 6:47 PM
> To: Sethi Varun-B16395
> Cc: joerg.roe...@amd.com; iommu@lists.linux-foundation.org; linuxppc-
> d...@lists.ozlabs.org; linux-ker...@vger.kernel.org; Sethi Varun-B16395
> Subject: Re: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes
> required by fsl PAMU driver.
>
>
> On Oct 4, 2012, at 6:56 AM,
> wrote:
>
> > From: Varun Sethi
> >
> > Added the following domain attributes required by FSL PAMU driver:
> > 1. Subwindows field added to the iommu domain geometry attribute.
> > 2. Added new iommu stash attribute, which allows setting of the
> > LIODN specific stash id parameter through IOMMU API.
> > 3. Added an attribute for enabling/disabling DMA to a particular
> > memory window.
> >
> > Signed-off-by: Varun Sethi
> > ---
> > include/linux/iommu.h | 35 +++
> > 1 files changed, 35 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/linux/iommu.h b/include/linux/iommu.h index
> > f3b99e1..62e22f0 100644
> > --- a/include/linux/iommu.h
> > +++ b/include/linux/iommu.h
> > @@ -44,6 +44,33 @@ struct iommu_domain_geometry {
> > dma_addr_t aperture_start; /* First address that can be mapped
> */
> > dma_addr_t aperture_end; /* Last address that can be mapped
> */
> > bool force_aperture; /* DMA only allowed in mappable range?
> */
> > +
> > + /* The subwindows field indicates number of DMA subwindows
> supported
> > +* by the geometry. Following is the interpretation of
> > +* values for this field:
> > +* 0 : This implies that the supported geometry size is 1 MB
> > + * with each subwindow size being 4KB. Thus number of
> subwindows
> > +* being = 1MB/4KB = 256.
> > +* 1 : Only one DMA window i.e. no subwindows.
> > +* value other than 0 or 1 would indicate actual number of
> subwindows.
> > +*/
> > + u32 subwindows;
> > +};
> > +
> > +/* cache stash targets */
> > +#define L1_CACHE 1
> > +#define L2_CACHE 2
> > +#define L3_CACHE 3
>
> These names are way to generic for being exposed to user space
Will fix naming to IOMMU_ATTR_CACHE_L1 etc.
-Varun
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RE: [RFC][PATCH 1/3] iommu/fsl: Store iommu domain information pointer in archdata.
> -Original Message- > From: Kumar Gala [mailto:ga...@kernel.crashing.org] > Sent: Wednesday, September 19, 2012 7:20 PM > To: Sethi Varun-B16395 > Cc: iommu@lists.linux-foundation.org; joerg.roe...@amd.com; linux- > ker...@vger.kernel.org; linuxppc-...@lists.ozlabs.org; Sethi Varun-B16395 > Subject: Re: [RFC][PATCH 1/3] iommu/fsl: Store iommu domain information > pointer in archdata. > > > On Sep 19, 2012, at 8:17 AM, > wrote: > > > From: Varun Sethi > > > > Add a new field in the device (powerpc) archdata structure for storing > > iommu domain information pointer. This pointer is stored when the > > device is attached to a particular domain. > > > > Signed-off-by: Varun Sethi > > --- > > arch/powerpc/include/asm/device.h |4 > > 1 files changed, 4 insertions(+), 0 deletions(-) > > Not too familiar, but what does the IBM Server IOMMU do for iommu_domain? > [Sethi Varun-B16395] I am not sure if the IBM iommu driver implements the iommu API. -Varun ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 3/3 v2] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
On Oct 4, 2012, at 6:56 AM, wrote: > From: Varun Sethi > > Following is a brief description of the PAMU hardware: > PAMU determines what action to take and whether to authorize the action on > the basis > of the memory address, a Logical IO Device Number (LIODN), and PAACT table > (logically) > indexed by LIODN and address. Hardware devices which need to access memory > must provide > an LIODN in addition to the memory address. > > Peripheral Access Authorization and Control Tables (PAACTs) are the primary > data structures > used by PAMU. A PAACT is a table of peripheral access authorization and > control entries (PAACE). > Each PAACE defines the range of I/O bus address space that is accessible by > the LIOD and the > associated access capabilities. > > There are two types of PAACTs: primary PAACT (PPAACT) and secondary PAACT > (SPAACT). A given physical > I/O device may be able to act as one or more independent logical I/O devices > (LIODs). Each such > logical I/O device is assigned an identifier called logical I/O device number > (LIODN). A LIOD is > allocated a contiguous portion of the I/O bus address space called the DSA > window for performing > DSA operations. The DSA window may optionally be divided into multiple > sub-windows, each of which > may be used to map to a region in system storage space. The first sub-window > is referred to > as the primary sub-window and the remaining are called secondary sub-windows. > > This patch provides the PAMU driver (fsl_pamu.c) and the corresponding IOMMU > API implementation > (fsl_pamu_domain.c). The PAMU hardware driver (fsl_pamu.c) has been derived > from the work done > by Ashish Kalra and Timur Tabi (ti...@freescale.com). > > Signed-off-by: Varun Sethi > --- I'm not seeing any of the comments I made addressed. What changed in this version? - k ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.
On Oct 4, 2012, at 6:56 AM, wrote:
> From: Varun Sethi
>
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
> LIODN specific stash id parameter through IOMMU API.
> 3. Added an attribute for enabling/disabling DMA to a particular
> memory window.
>
> Signed-off-by: Varun Sethi
> ---
> include/linux/iommu.h | 35 +++
> 1 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index f3b99e1..62e22f0 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -44,6 +44,33 @@ struct iommu_domain_geometry {
> dma_addr_t aperture_start; /* First address that can be mapped*/
> dma_addr_t aperture_end; /* Last address that can be mapped */
> bool force_aperture; /* DMA only allowed in mappable range? */
> +
> + /* The subwindows field indicates number of DMA subwindows supported
> + * by the geometry. Following is the interpretation of
> + * values for this field:
> + * 0 : This implies that the supported geometry size is 1 MB
> + * with each subwindow size being 4KB. Thus number of subwindows
> + * being = 1MB/4KB = 256.
> + * 1 : Only one DMA window i.e. no subwindows.
> + * value other than 0 or 1 would indicate actual number of subwindows.
> + */
> + u32 subwindows;
> +};
> +
> +/* cache stash targets */
> +#define L1_CACHE 1
> +#define L2_CACHE 2
> +#define L3_CACHE 3
These names are way to generic for being exposed to user space
> +
> +/* This attribute corresponds to IOMMUs capable of generating
> + * a stash transaction. A stash transaction is typically a
> + * hardware initiated prefetch of data from memory to cache.
> + * This attribute allows configuring stashig specific parameters
> + * in the IOMMU hardware.
> + */
> +struct iommu_stash_attribute {
> + u32 cpu;/* cpu number */
> + u32 cache; /* cache to stash to: L1,L2,L3 */
> };
>
> struct iommu_domain {
> @@ -60,6 +87,14 @@ struct iommu_domain {
> enum iommu_attr {
> DOMAIN_ATTR_MAX,
> DOMAIN_ATTR_GEOMETRY,
> + /* Set the IOMMU hardware stashing
> + * parameters.
> + */
> + DOMAIN_ATTR_STASH,
> + /* Explicity enable/disable DMA for a
> + * particular memory window.
> + */
> + DOMAIN_ATTR_ENABLE,
> };
>
> #ifdef CONFIG_IOMMU_API
> --
> 1.7.4.1
>
>
> --
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[PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.
From: Varun Sethi
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API.
3. Added an attribute for enabling/disabling DMA to a particular
memory window.
Signed-off-by: Varun Sethi
---
include/linux/iommu.h | 35 +++
1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index f3b99e1..62e22f0 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -44,6 +44,33 @@ struct iommu_domain_geometry {
dma_addr_t aperture_start; /* First address that can be mapped*/
dma_addr_t aperture_end; /* Last address that can be mapped */
bool force_aperture; /* DMA only allowed in mappable range? */
+
+ /* The subwindows field indicates number of DMA subwindows supported
+* by the geometry. Following is the interpretation of
+* values for this field:
+* 0 : This implies that the supported geometry size is 1 MB
+ * with each subwindow size being 4KB. Thus number of subwindows
+* being = 1MB/4KB = 256.
+* 1 : Only one DMA window i.e. no subwindows.
+* value other than 0 or 1 would indicate actual number of subwindows.
+*/
+ u32 subwindows;
+};
+
+/* cache stash targets */
+#define L1_CACHE 1
+#define L2_CACHE 2
+#define L3_CACHE 3
+
+/* This attribute corresponds to IOMMUs capable of generating
+ * a stash transaction. A stash transaction is typically a
+ * hardware initiated prefetch of data from memory to cache.
+ * This attribute allows configuring stashig specific parameters
+ * in the IOMMU hardware.
+ */
+struct iommu_stash_attribute {
+ u32 cpu;/* cpu number */
+ u32 cache; /* cache to stash to: L1,L2,L3 */
};
struct iommu_domain {
@@ -60,6 +87,14 @@ struct iommu_domain {
enum iommu_attr {
DOMAIN_ATTR_MAX,
DOMAIN_ATTR_GEOMETRY,
+ /* Set the IOMMU hardware stashing
+* parameters.
+*/
+ DOMAIN_ATTR_STASH,
+ /* Explicity enable/disable DMA for a
+ * particular memory window.
+ */
+ DOMAIN_ATTR_ENABLE,
};
#ifdef CONFIG_IOMMU_API
--
1.7.4.1
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[PATCH 1/3 v2] iommu/fsl: Store iommu domain information pointer in archdata.
From: Varun Sethi
Add a new field in the device (powerpc) archdata structure for storing iommu
domain
information pointer. This pointer is stored when the device is attached to a
particular
domain.
Signed-off-by: Varun Sethi
---
arch/powerpc/include/asm/device.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/device.h
b/arch/powerpc/include/asm/device.h
index 77e97dd..6dc79fe 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -28,6 +28,10 @@ struct dev_archdata {
void*iommu_table_base;
} dma_data;
+ /* IOMMU domain information pointer. This would be set
+* when this device is attached to an iommu_domain.
+*/
+ void*iommu_domain;
#ifdef CONFIG_SWIOTLB
dma_addr_t max_direct_dma_addr;
#endif
--
1.7.4.1
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[PATCH 0/3 v2] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
From: Varun Sethi This patchset provides the Freescale PAMU (Peripheral Access Management Unit) driver and the corresponding IOMMU API implementation. PAMU is the IOMMU present on Freescale QorIQ platforms. PAMU can authorize memory access, remap the memory address, and remap the I/O transaction type. This set consists of the following patches: 1. Addition of new field in the device (powerpc) archdata structure for storing iommu domain information pointer. This pointer is stored when the device is attached to a particular iommu domain. 2. Addition of domain attributes required by the PAMU driver IOMMU API. 3. PAMU driver and IOMMU API implementation. This patch set is based on the next branch of the iommu git tree maintained by Joerg. Varun Sethi (3): Store iommu domain information pointer in archdata. Add iommu domain attributes required by fsl PAMU driver. FSL PAMU driver and IOMMU API implementation. arch/powerpc/include/asm/device.h |4 + drivers/iommu/Kconfig |7 + drivers/iommu/Makefile|1 + drivers/iommu/fsl_pamu.c | 1033 + drivers/iommu/fsl_pamu.h | 377 ++ drivers/iommu/fsl_pamu_domain.c | 990 +++ drivers/iommu/fsl_pamu_domain.h | 94 drivers/iommu/fsl_pamu_proto.h| 49 ++ include/linux/iommu.h | 30 ++ 9 files changed, 2585 insertions(+), 0 deletions(-) create mode 100644 drivers/iommu/fsl_pamu.c create mode 100644 drivers/iommu/fsl_pamu.h create mode 100644 drivers/iommu/fsl_pamu_domain.c create mode 100644 drivers/iommu/fsl_pamu_domain.h create mode 100644 drivers/iommu/fsl_pamu_proto.h -- 1.7.4.1 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
