[PATCH v2 1/2] iommu/io-pgtable: Add MTK 4GB mode in Short-descriptor
In MT8173, Normally the first 1GB PA is for the HW SRAM and Regs,
so the PA will be 33bits if the dram size is 4GB. We have a
"DRAM 4GB mode" toggle bit for this. If it's enabled, from CPU's
point of view, the dram PA will be from 0x1_~0x1_.
In short descriptor, the pagetable descriptor is always 32bit.
Mediatek extend bit9 in the lvl1 and lvl2 pgtable descriptor
as the 4GB mode.
In the 4GB mode, the bit9 must be set, then M4U help add 0x1_
based on the PA in pagetable. Thus the M4U output address to EMI is
always 33bits(the input address is still 32bits).
We add a special quirk for this MTK-4GB mode. And in the standard
spec, Bit9 in the lvl1 is "IMPLEMENTATION DEFINED", while it's AP[2]
in the lvl2, therefore if this quirk is enabled, NO_PERMS is also
expected.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 13 -
drivers/iommu/io-pgtable.h | 6 ++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c
b/drivers/iommu/io-pgtable-arm-v7s.c
index 9fcceb1..32b371b 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -121,6 +121,8 @@
#define ARM_V7S_TEX_MASK 0x7
#define ARM_V7S_ATTR_TEX(val) (((val) & ARM_V7S_TEX_MASK) <<
ARM_V7S_TEX_SHIFT)
+#define ARM_V7S_ATTR_MTK_4GB BIT(9) /* MTK extend it for 4GB mode */
+
/* *well, except for TEX on level 2 large pages, of course :( */
#define ARM_V7S_CONT_PAGE_TEX_SHIFT6
#define ARM_V7S_CONT_PAGE_TEX_MASK (ARM_V7S_TEX_MASK <<
ARM_V7S_CONT_PAGE_TEX_SHIFT)
@@ -364,6 +366,9 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
if (lvl == 1 && (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS))
pte |= ARM_V7S_ATTR_NS_SECTION;
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB)
+ pte |= ARM_V7S_ATTR_MTK_4GB;
+
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, lvl);
@@ -625,9 +630,15 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct
io_pgtable_cfg *cfg,
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
- IO_PGTABLE_QUIRK_TLBI_ON_MAP))
+ IO_PGTABLE_QUIRK_TLBI_ON_MAP |
+ IO_PGTABLE_QUIRK_ARM_MTK_4GB))
return NULL;
+ /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_4GB &&
+ !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
+ return NULL;
+
data = kmalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return NULL;
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
index d4f5027..969d82c 100644
--- a/drivers/iommu/io-pgtable.h
+++ b/drivers/iommu/io-pgtable.h
@@ -60,10 +60,16 @@ struct io_pgtable_cfg {
* IO_PGTABLE_QUIRK_TLBI_ON_MAP: If the format forbids caching invalid
* (unmapped) entries but the hardware might do so anyway, perform
* TLB maintenance when mapping as well as when unmapping.
+*
+* IO_PGTABLE_QUIRK_ARM_MTK_4GB: (ARM v7s format) Set bit 9 in all
+* PTEs, for Mediatek IOMMUs which treat it as a 33rd address bit
+* when the SoC is in "4GB mode" and they can only access the high
+* remap of DRAM (0x1_ to 0x1_).
*/
#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
#define IO_PGTABLE_QUIRK_TLBI_ON_MAPBIT(2)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_4GBBIT(3)
unsigned long quirks;
unsigned long pgsize_bitmap;
unsigned intias;
--
1.8.1.1.dirty
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[PATCH v2 2/2] iommu/mediatek: Add 4GB mode support
This patch add 4GB mode support for m4u.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 721ffdb..b97de21 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -11,6 +11,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+#include
#include
#include
#include
@@ -56,7 +57,7 @@
#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
#define REG_MMU_IVRP_PADDR 0x114
-#define F_MMU_IVRP_PA_SET(pa) ((pa) >> 1)
+#define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) <<
31))
#define REG_MMU_INT_CONTROL0 0x120
#define F_L2_MULIT_HIT_EN BIT(0)
@@ -125,6 +126,7 @@ struct mtk_iommu_data {
struct mtk_iommu_domain *m4u_dom;
struct iommu_group *m4u_group;
struct mtk_smi_iommusmi_imu; /* SMI larb iommu info */
+ boolenable_4GB;
};
static struct iommu_ops mtk_iommu_ops;
@@ -257,6 +259,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_data
*data)
.iommu_dev = data->dev,
};
+ if (data->enable_4GB)
+ dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB;
+
dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
if (!dom->iop) {
dev_err(data->dev, "Failed to alloc io pgtable\n");
@@ -530,7 +535,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data
*data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base),
+ writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
data->base + REG_MMU_IVRP_PADDR);
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
@@ -592,6 +597,9 @@ static int mtk_iommu_probe(struct platform_device *pdev)
return -ENOMEM;
data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
+ /* Whether the current dram is over 4GB */
+ data->enable_4GB = !!(max_pfn > (0xUL >> PAGE_SHIFT));
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->base = devm_ioremap_resource(dev, res);
if (IS_ERR(data->base))
@@ -691,7 +699,7 @@ static int mtk_iommu_resume(struct device *dev)
writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
- writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base),
+ writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
base + REG_MMU_IVRP_PADDR);
return 0;
}
--
1.8.1.1.dirty
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[PATCH v2 0/2] MT8173 IOMMU 4GB MODE SUPPORT
This patch-set add MTK 4GB mode support on the Short-Descriptor. Normally, the memory map in mt8173 looks like below: Physical addr | 1st GB |-> HW SRAM and Regs | | 2nd GB |-> Dram 1st GB | | 3rd GB |-> Dram 2nd GB | | 4th GB |-> Dram 3rd GB | Then if the dram size is 4GB, we have to add bit33 in the physical address. We have a "DRAM 4GB mode" toggle bit for this. If it is enabled, from CPU's point of view, the dram will be shifted to start from PA 0x1_. Then the dram PA is from 0x1_~0x1_. MTK extend the bit9 of the standard pgtable descriptor as the 4GB mode. we add a special quirk for this. v2: - Rebase on next-20160310. - Rename IO_PGTABLE_QUIRK_MTK_4GB_EXT to IO_PGTABLE_QUIRK_ARM_MTK_4GB. - Improve the comment of this "4GB mode". Yong Wu (2): iommu/io-pgtable: Add MTK 4GB mode in Short-descriptor iommu/mediatek: Add 4GB mode support drivers/iommu/io-pgtable-arm-v7s.c | 13 - drivers/iommu/io-pgtable.h | 6 ++ drivers/iommu/mtk_iommu.c | 14 +++--- 3 files changed, 29 insertions(+), 4 deletions(-) -- 1.8.1.1.dirty ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH V5 02/10] perf/amd/iommu: Consolidate and move perf_event_amd_iommu header
Hi, On 03/12/2016 08:22 PM, Peter Zijlstra wrote: On Tue, Feb 23, 2016 at 08:12:36AM -0600, Suravee Suthikulpanit wrote: From: Suravee Suthikulpanit First, this patch move arch/x86/events/amd/iommu.h to arch/x86/include/asm/perf/amd/iommu.h so that we easily include it in both perf-amd-iommu and amd-iommu drivers. Then, we consolidate declaration of AMD IOMMU performance counter APIs into one file. These seem two independent thingies; should this therefore not be 2 patches? Reviewed-by: Joerg Roedel Signed-off-by: Suravee Suthikulpanit --- arch/x86/events/amd/iommu.c | 2 +- arch/x86/events/amd/iommu.h | 40 - arch/x86/include/asm/perf/amd/iommu.h | 42 +++ That seems somewhat excessive. Not only do you create arch/x86/include/asm/perf/ you then put another directory on top of that. The original header files (arch/x86/events/amd/iommu.h and drivers/iommu/amd_iommu_proto.h) has duplicate function declarations. So, with the new header file being in the arch/x86/include/asm/perf/amd/iommu.h, we can just have one function declaration. So, you just want to separate the file moving part and the part that removes of the duplication? Thanks, Suravee ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [v6, 5/5] mmc: sdhci-of-esdhc: fix host version for T4240-R1.0-R2.0
On Wednesday 09 March 2016 18:08:51 Yangbo Lu wrote:
> @@ -567,10 +580,20 @@ static void esdhc_init(struct platform_device *pdev,
> struct sdhci_host *host)
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_esdhc *esdhc;
> u16 host_ver;
> + u32 svr;
>
> pltfm_host = sdhci_priv(host);
> esdhc = sdhci_pltfm_priv(pltfm_host);
>
> + fsl_guts_init();
> + svr = fsl_guts_get_svr();
> + if (svr) {
> + esdhc->soc_ver = SVR_SOC_VER(svr);
> + esdhc->soc_rev = SVR_REV(svr);
> + } else {
> + dev_err(&pdev->dev, "Failed to get SVR value!\n");
> + }
> +
This makes the driver non-portable. Better identify the specific workarounds
based on the compatible string for this device, or add a boolean DT property
for the quirk.
Arnd
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