According to the manual: "Hardware access to ... invalidation queue ... are always coherent."
Remove unnecassary clflushes accordingly. Signed-off-by: Nadav Amit <na...@vmware.com> --- Build-tested since I do not have an IOMMU that does not support coherency. --- drivers/iommu/dmar.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c index 6a86b5d..ca56ec3 100644 --- a/drivers/iommu/dmar.c +++ b/drivers/iommu/dmar.c @@ -1155,8 +1155,6 @@ static int qi_check_fault(struct intel_iommu *iommu, int index) (unsigned long long)qi->desc[index].high); memcpy(&qi->desc[index], &qi->desc[wait_index], sizeof(struct qi_desc)); - __iommu_flush_cache(iommu, &qi->desc[index], - sizeof(struct qi_desc)); writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); return -EINVAL; } @@ -1231,9 +1229,6 @@ restart: hw[wait_index] = wait_desc; - __iommu_flush_cache(iommu, &hw[index], sizeof(struct qi_desc)); - __iommu_flush_cache(iommu, &hw[wait_index], sizeof(struct qi_desc)); - qi->free_head = (qi->free_head + 2) % QI_LENGTH; qi->free_cnt -= 2; -- 2.7.4 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu