Re: [PATCH 09/12] iommu/vt-d: Check device list of domain in domain free path
On 2022/6/2 14:29, Tian, Kevin wrote:
From: Baolu Lu
Sent: Wednesday, June 1, 2022 7:02 PM
On 2022/6/1 17:28, Tian, Kevin wrote:
From: Lu Baolu
Sent: Friday, May 27, 2022 2:30 PM
When the IOMMU domain is about to be freed, it should not be set on
any
device. Instead of silently dealing with some bug cases, it's better to
trigger a warning to report and fix any potential bugs at the first time.
static void domain_exit(struct dmar_domain *domain)
{
-
- /* Remove associated devices and clear attached or cached domains
*/
- domain_remove_dev_info(domain);
+ if (WARN_ON(!list_empty(>devices)))
+ return;
warning is good but it doesn't mean the driver shouldn't deal with
that situation to make it safer e.g. blocking DMA from all attached
device...
I have ever thought the same thing. :-)
Blocking DMA from attached device should be done when setting blocking
domain to the device. It should not be part of freeing a domain.
yes but here we are talking about some bug scenario.
Here, the caller asks the driver to free the domain, but the driver
finds that something is wrong. Therefore, it warns and returns directly.
The domain will still be there in use until the next set_domain().
at least it'd look safer if we always try to unmap the entire domain i.e.:
static void domain_exit(struct dmar_domain *domain)
{
-
- /* Remove associated devices and clear attached or cached domains */
- domain_remove_dev_info(domain);
if (domain->pgd) {
LIST_HEAD(freelist);
domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw), );
put_pages_list();
}
+ if (WARN_ON(!list_empty(>devices)))
+ return;
kfree(domain);
}
Fair enough. Removing all mappings is safer.
Best regards,
baolu
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Re: [PATCH v2 0/9] Add dynamic iommu backed bounce buffers
On Fri, Jun 3, 2022 at 11:53 PM Niklas Schnelle wrote: > > On Fri, 2022-05-27 at 10:25 +0900, David Stevens wrote: > > On Tue, May 24, 2022 at 9:27 PM Niklas Schnelle > > wrote: > > > On Fri, 2021-08-06 at 19:34 +0900, David Stevens wrote: > > > > From: David Stevens > > > > > > > > This patch series adds support for per-domain dynamic pools of iommu > > > > bounce buffers to the dma-iommu API. This allows iommu mappings to be > > > > reused while still maintaining strict iommu protection. > > > > > > > > This bounce buffer support is used to add a new config option that, when > > > > enabled, causes all non-direct streaming mappings below a configurable > > > > size to go through the bounce buffers. This serves as an optimization on > > > > systems where manipulating iommu mappings is very expensive. For > > > > example, virtio-iommu operations in a guest on a linux host require a > > > > vmexit, involvement the VMM, and a VFIO syscall. For relatively small > > > > DMA operations, memcpy can be significantly faster. > > > > > > > > As a performance comparison, on a device with an i5-10210U, I ran fio > > > > with a VFIO passthrough NVMe drive and virtio-iommu with '--direct=1 > > > > --rw=read --ioengine=libaio --iodepth=64' and block sizes 4k, 16k, 64k, > > > > and 128k. Test throughput increased by 2.8x, 4.7x, 3.6x, and 3.6x. Time > > > > spent in iommu_dma_unmap_(page|sg) per GB processed decreased by 97%, > > > > 94%, 90%, and 87%. Time spent in iommu_dma_map_(page|sg) decreased > > > > by >99%, as bounce buffers don't require syncing here in the read case. > > > > Running with multiple jobs doesn't serve as a useful performance > > > > comparison because virtio-iommu and vfio_iommu_type1 both have big > > > > locks that significantly limit mulithreaded DMA performance. > > > > > > > > These pooled bounce buffers are also used for subgranule mappings with > > > > untrusted devices, replacing the single use bounce buffers used > > > > currently. The biggest difference here is that the new implementation > > > > maps a whole sglist using a single bounce buffer. The new implementation > > > > does not support using bounce buffers for only some segments of the > > > > sglist, so it may require more copying. However, the current > > > > implementation requires per-segment iommu map/unmap operations for all > > > > untrusted sglist mappings (fully aligned sglists included). On a > > > > i5-10210U laptop with the internal NVMe drive made to appear untrusted, > > > > fio --direct=1 --rw=read --ioengine=libaio --iodepth=64 --bs=64k showed > > > > a statistically significant decrease in CPU load from 2.28% -> 2.17% > > > > with the new iommu bounce buffer optimization enabled. > > > > > > > > Each domain's buffer pool is split into multiple power-of-2 size > > > > classes. Each class allocates a fixed number of buffer slot metadata. A > > > > large iova range is allocated, and each slot is assigned an iova from > > > > the range. This allows the iova to be easily mapped back to the slot, > > > > and allows the critical section of most pool operations to be constant > > > > time. The one exception is finding a cached buffer to reuse. These are > > > > only separated according to R/W permissions - the use of other > > > > permissions such as IOMMU_PRIV may require a linear search through the > > > > cache. However, these other permissions are rare and likely exhibit high > > > > locality, so the should not be a bottleneck in practice. > > > > > > > > Since untrusted devices may require bounce buffers, each domain has a > > > > fallback rbtree to manage single use buffers. This may be necessary if a > > > > very large number of DMA operations are simultaneously in-flight, or for > > > > very large individual DMA operations. > > > > > > > > This patch set does not use swiotlb. There are two primary ways in which > > > > swiotlb isn't compatible with per-domain buffer pools. First, swiotlb > > > > allocates buffers to be compatible with a single device, whereas > > > > per-domain buffer pools don't handle that during buffer allocation as a > > > > single buffer may end up being used by multiple devices. Second, swiotlb > > > > allocation establishes the original to bounce buffer mapping, which > > > > again doesn't work if buffers can be reused. Effectively the only code > > > > that can be shared between the two use cases is allocating slots from > > > > the swiotlb's memory. However, given that we're going to be allocating > > > > memory for use with an iommu, allocating memory from a block of memory > > > > explicitly set aside to deal with a lack of iommu seems kind of > > > > contradictory. At best there might be a small performance improvement if > > > > wiotlb allocation is faster than regular page allocation, but buffer > > > > allocation isn't on the hot path anyway. > > > > > > > > Not using the swiotlb has the benefit that memory doesn't have to be > > > > preallocated. Instead, bounce buffers
Re: [PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior
On 2022-05-31 16:55:59, Will Deacon wrote: > On Fri, May 27, 2022 at 11:28:57PM +0200, Konrad Dybcio wrote: > > From: AngeloGioacchino Del Regno > > > > As also stated in the arm-smmu driver, we must write the TCR before > > writing the TTBRs, since the TCR determines the access behavior of > > some fields. > > Where is this stated in the arm-smmu driver? > > > > > Signed-off-by: AngeloGioacchino Del Regno > > > > Signed-off-by: Marijn Suijten > > Signed-off-by: Konrad Dybcio > > --- > > drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++-- > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c > > b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > > index 1728d4d7fe25..75f353866c40 100644 > > --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c > > +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > > @@ -273,18 +273,18 @@ static int qcom_iommu_init_domain(struct iommu_domain > > *domain, > > ctx->secure_init = true; > > } > > > > - /* TTBRs */ > > - iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, > > - pgtbl_cfg.arm_lpae_s1_cfg.ttbr | > > - FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); > > - iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); > > - > > /* TCR */ > > iommu_writel(ctx, ARM_SMMU_CB_TCR2, > > arm_smmu_lpae_tcr2(_cfg)); > > iommu_writel(ctx, ARM_SMMU_CB_TCR, > > arm_smmu_lpae_tcr(_cfg) | ARM_SMMU_TCR_EAE); > > > > + /* TTBRs */ > > + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, > > + pgtbl_cfg.arm_lpae_s1_cfg.ttbr | > > + FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); > > + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); > > I'd have thought that SCTLR.M would be clear here, so it shouldn't matter > what order we write these in. Having tested the series without this particular patch on 8976 (Sony Loire Suzu), it doesn't seem to matter indeed. I'll ask around if this "access behaviour" was observed on a different board/platform. - Marijn ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH V4 5/8] dt-bindings: Add xen,grant-dma IOMMU description for xen-grant DMA ops
On Thu, 02 Jun 2022 22:23:50 +0300, Oleksandr Tyshchenko wrote: > From: Oleksandr Tyshchenko > > The main purpose of this binding is to communicate Xen specific > information using generic IOMMU device tree bindings (which is > a good fit here) rather than introducing a custom property. > > Introduce Xen specific IOMMU for the virtualized device (e.g. virtio) > to be used by Xen grant DMA-mapping layer in the subsequent commit. > > The reference to Xen specific IOMMU node using "iommus" property > indicates that Xen grant mappings need to be enabled for the device, > and it specifies the ID of the domain where the corresponding backend > resides. The domid (domain ID) is used as an argument to the Xen grant > mapping APIs. > > This is needed for the option to restrict memory access using Xen grant > mappings to work which primary goal is to enable using virtio devices > in Xen guests. > > Signed-off-by: Oleksandr Tyshchenko > Reviewed-by: Stefano Stabellini > --- > Changes RFC -> V1: >- update commit subject/description and text in description >- move to devicetree/bindings/arm/ > > Changes V1 -> V2: >- update text in description >- change the maintainer of the binding >- fix validation issue >- reference xen,dev-domid.yaml schema from virtio/mmio.yaml > > Change V2 -> V3: >- Stefano already gave his Reviewed-by, I dropped it due to the changes > (significant) >- use generic IOMMU device tree bindings instead of custom property > "xen,dev-domid" >- change commit subject and description, was > "dt-bindings: Add xen,dev-domid property description for xen-grant DMA > ops" > > Changes V3 -> V4: >- add Stefano's R-b >- remove underscore in iommu node name >- remove consumer example virtio@3000 >- update text for two descriptions > --- > .../devicetree/bindings/iommu/xen,grant-dma.yaml | 39 > ++ > 1 file changed, 39 insertions(+) > create mode 100644 Documentation/devicetree/bindings/iommu/xen,grant-dma.yaml > Reviewed-by: Rob Herring ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
On Mon, May 30, 2022 at 08:03:26PM +0200, Fabien Parent wrote: > Add IOMMU binding documentation for the MT8365 SoC. > > Signed-off-by: Fabien Parent > --- > .../bindings/iommu/mediatek,iommu.yaml| 2 + > include/dt-bindings/memory/mt8365-larb-port.h | 96 +++ > 2 files changed, 98 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8365-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > index 97e8c471a5e8..5ba688365da5 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -77,6 +77,7 @@ properties: >- mediatek,mt8173-m4u # generation two >- mediatek,mt8183-m4u # generation two >- mediatek,mt8192-m4u # generation two > + - mediatek,mt8365-m4u # generation two > >- description: mt7623 generation one > items: > @@ -120,6 +121,7 @@ properties: >dt-binding/memory/mt8173-larb-port.h for mt8173, >dt-binding/memory/mt8183-larb-port.h for mt8183, >dt-binding/memory/mt8192-larb-port.h for mt8192. > + dt-binding/memory/mt8365-larb-port.h for mt8365. > >power-domains: > maxItems: 1 > diff --git a/include/dt-bindings/memory/mt8365-larb-port.h > b/include/dt-bindings/memory/mt8365-larb-port.h > new file mode 100644 > index ..e7d5637aa38e > --- /dev/null > +++ b/include/dt-bindings/memory/mt8365-larb-port.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ Dual license please. Rob ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
