Re: [PATCH 1/2] iommu: arm-smmu-impl: Add 8250 display compatible to the client list.
On 15.06.2022 01:01, Emma Anholt wrote:
> Required for turning on per-process page tables for the GPU.
>
> Signed-off-by: Emma Anholt
> ---
Reviewed-by: Konrad Dybcio
Konrad
>
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index d8e1ef83c01b..bb9220937068 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -233,6 +233,7 @@ static const struct of_device_id
> qcom_smmu_client_of_match[] __maybe_unused = {
> { .compatible = "qcom,sc7280-mdss" },
> { .compatible = "qcom,sc7280-mss-pil" },
> { .compatible = "qcom,sc8180x-mdss" },
> + { .compatible = "qcom,sm8250-mdss" },
> { .compatible = "qcom,sdm845-mdss" },
> { .compatible = "qcom,sdm845-mss-pil" },
> { }
>
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Re: [PATCH 1/6] iommu/qcom: Use the asid read from device-tree if specified
On 31.05.2022 22:57, Rob Clark wrote: > On Tue, May 31, 2022 at 9:19 AM Will Deacon wrote: >> >> On Tue, May 31, 2022 at 09:15:22AM -0700, Rob Clark wrote: >>> On Tue, May 31, 2022 at 8:46 AM Will Deacon wrote: >>>> >>>> On Fri, May 27, 2022 at 11:28:56PM +0200, Konrad Dybcio wrote: >>>>> From: AngeloGioacchino Del Regno >>>>> >>>>> >>>>> As specified in this driver, the context banks are 0x1000 apart. >>>>> Problem is that sometimes the context number (our asid) does not >>>>> match this logic and we end up using the wrong one: this starts >>>>> being a problem in the case that we need to send TZ commands >>>>> to do anything on a specific context. >>>> >>>> I don't understand this. The ASID is a software construct, so it shouldn't >>>> matter what we use. If it does matter, then please can you explain why? The >>>> fact that the context banks are 0x1000 apart seems unrelated. >>> >>> I think the connection is that mapping from ctx bank to ASID is 1:1 >> >> But in what sense? How is the ASID used beyond a tag in the TLB? The commit >> message hints at "TZ commands" being a problem. >> >> I'm not doubting that this is needed to make the thing work, I just don't >> understand why. > > (disclaimer, it has been quite a while since I've looked at the smmu > setup with earlier tz, ie. things that use qcom_iommu, but from > memory...) > > We cannot actually assign the context banks ourselves, so in the dt > bindings the "ASID" is actually the context bank index. I think so. I don't > remember exactly if this was a limitation of the tz interface, or > result of not being able to program the smmu's global registers > ourselves. As far as I understand, it's the latter, as changing the defaults is not allowed by the security policy on consumer devices. Qualcomm arbitrarily chose some numbers that may or may have not aligned with their usual index-is-offset-divided-by-0x1000 and hardcoded them in the BSP, and now the secure side (if required, and well, it is..) expects precisely that configuration. Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 1/6] iommu/qcom: Use the asid read from device-tree if specified
From: AngeloGioacchino Del Regno
As specified in this driver, the context banks are 0x1000 apart.
Problem is that sometimes the context number (our asid) does not
match this logic and we end up using the wrong one: this starts
being a problem in the case that we need to send TZ commands
to do anything on a specific context.
For this reason, read the ASID from the DT if the property
"qcom,ctx-num" is present on the IOMMU context node.
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 1 +
drivers/iommu/arm/arm-smmu/qcom_iommu.c| 18 +++---
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
index 059139abce35..ba0b77889f02 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
@@ -46,6 +46,7 @@ to non-secure vs secure interrupt line.
for routing of context bank irq's to secure vs non-
secure lines. (Ie. if the iommu contains secure
context banks)
+- qcom,ctx-num : The number associated to the context bank
** Examples:
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 4c077c38fbd6..1728d4d7fe25 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -566,7 +566,8 @@ static int qcom_iommu_of_xlate(struct device *dev, struct
of_phandle_args *args)
* index into qcom_iommu->ctxs:
*/
if (WARN_ON(asid < 1) ||
- WARN_ON(asid > qcom_iommu->num_ctxs)) {
+ WARN_ON(asid > qcom_iommu->num_ctxs) ||
+ WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) {
put_device(_pdev->dev);
return -EINVAL;
}
@@ -654,7 +655,8 @@ static int qcom_iommu_sec_ptbl_init(struct device *dev)
static int get_asid(const struct device_node *np)
{
- u32 reg;
+ u32 reg, val;
+ int asid;
/* read the "reg" property directly to get the relative address
* of the context bank, and calculate the asid from that:
@@ -662,7 +664,17 @@ static int get_asid(const struct device_node *np)
if (of_property_read_u32_index(np, "reg", 0, ))
return -ENODEV;
- return reg / 0x1000; /* context banks are 0x1000 apart */
+ /*
+* Context banks are 0x1000 apart but, in some cases, the ASID
+* number doesn't match to this logic and needs to be passed
+* from the DT configuration explicitly.
+*/
+ if (of_property_read_u32(np, "qcom,ctx-num", ))
+ asid = reg / 0x1000;
+ else
+ asid = val;
+
+ return asid;
}
static int qcom_iommu_ctx_probe(struct platform_device *pdev)
--
2.36.1
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[PATCH 0/6] Fix and extend Qualcomm IOMMU support
Due to Qualcomm's software solutions, genius or otherwise, the IOMMUs on pre-msm8998-and-sdm630 SoCs are flawed beyond reason, and conviniently it is all due to an (almost in all cases) irreplaceable hypervisor and TZ stack. As end users and developers, we have no choice but to adapt to that and follow whatever the IOMMUs expect. This series fixes and improves the existing support (adjusts the code flow to make sure things are written in correct order and adds a way to properly (i.e. in compliance with the firmware's expectations) reset the IOMMUs) and extends it with features for the SoCs that came near the end of an era of what we call "qcom_iommu" upstream, namely 8952 family (8917, 8937, 8952, 8956/76, 8953 and possibly more) (Aarch64 pagetables and secured QCIOMMUv2/QCIOMMU_500 ctxs) and at the same time builds another milestone in getting msm8974/94 IOMMU support that has been in the works for something like 7 years, and never got upstreamed in the end (we'll get it one day, eventually...). The dt-bindings are NOT converted to YAML as a part of this series, that will come in a later patchset. AngeloGioacchino Del Regno (6): iommu/qcom: Use the asid read from device-tree if specified iommu/qcom: Write TCR before TTBRs to fix ASID access behavior iommu/qcom: Properly reset the IOMMU context iommu/qcom: Add support for AArch64 IOMMU pagetables iommu/qcom: Index contexts by asid number to allow asid 0 iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts .../devicetree/bindings/iommu/qcom,iommu.txt | 5 + drivers/iommu/arm/arm-smmu/qcom_iommu.c | 137 ++ 2 files changed, 114 insertions(+), 28 deletions(-) -- 2.36.1 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 3/6] iommu/qcom: Properly reset the IOMMU context
From: AngeloGioacchino Del Regno
To avoid context faults reset the context entirely on detach and
to ensure a fresh clean start also do a complete reset before
programming the context for domain initialization.
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 75f353866c40..129e322f56a6 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -223,6 +223,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
return IRQ_HANDLED;
}
+static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx)
+{
+ iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_PAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
+
+ /* Should we issue a TLBSYNC there instead? */
+ wmb();
+}
+
static int qcom_iommu_init_domain(struct iommu_domain *domain,
struct qcom_iommu_dev *qcom_iommu,
struct device *dev)
@@ -273,6 +290,8 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
ctx->secure_init = true;
}
+ qcom_iommu_reset_ctx(ctx);
+
/* TCR */
iommu_writel(ctx, ARM_SMMU_CB_TCR2,
arm_smmu_lpae_tcr2(_cfg));
@@ -406,8 +425,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain
*domain, struct device *de
for (i = 0; i < fwspec->num_ids; i++) {
struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain,
fwspec->ids[i]);
- /* Disable the context bank: */
- iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ /* Disable and reset the context bank */
+ qcom_iommu_reset_ctx(ctx);
ctx->domain = NULL;
}
--
2.36.1
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[PATCH 2/6] iommu/qcom: Write TCR before TTBRs to fix ASID access behavior
From: AngeloGioacchino Del Regno As also stated in the arm-smmu driver, we must write the TCR before writing the TTBRs, since the TCR determines the access behavior of some fields. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Marijn Suijten Signed-off-by: Konrad Dybcio --- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 1728d4d7fe25..75f353866c40 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -273,18 +273,18 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, ctx->secure_init = true; } - /* TTBRs */ - iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, - pgtbl_cfg.arm_lpae_s1_cfg.ttbr | - FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); - iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); - /* TCR */ iommu_writel(ctx, ARM_SMMU_CB_TCR2, arm_smmu_lpae_tcr2(_cfg)); iommu_writel(ctx, ARM_SMMU_CB_TCR, arm_smmu_lpae_tcr(_cfg) | ARM_SMMU_TCR_EAE); + /* TTBRs */ + iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, + pgtbl_cfg.arm_lpae_s1_cfg.ttbr | + FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); + iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0); + /* MAIRs (stage-1 only) */ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, pgtbl_cfg.arm_lpae_s1_cfg.mair); -- 2.36.1 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 4/6] iommu/qcom: Add support for AArch64 IOMMU pagetables
From: AngeloGioacchino Del Regno
Some IOMMUs associated with some TZ firmwares may support switching
to the AArch64 pagetable format by sending a "set pagetable format"
scm command indicating the IOMMU secure ID and the context number
to switch.
Add a DT property "qcom,use-aarch64-pagetables" for this driver to
send this command to the secure world and to switch the pagetable
format to benefit of the ARM64 IOMMU pagetables, where possible.
Note that, even though the command should be valid to switch each
context, the property is made global because:
1. It doesn't make too much sense to switch only one or two
context(s) to AA64 instead of just the entire thing
2. Some IOMMUs will go crazy and produce spectacular results when
trying to mix up the pagetables on a per-context basis.
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 2 +
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 54 +++
2 files changed, 47 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
index ba0b77889f02..72ae0595efff 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
@@ -47,6 +47,8 @@ to non-secure vs secure interrupt line.
secure lines. (Ie. if the iommu contains secure
context banks)
- qcom,ctx-num : The number associated to the context bank
+- qcom,use-aarch64-pagetables : Switch to AArch64 pagetable format on all
+contexts declared in this IOMMU
** Examples:
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 129e322f56a6..530aa92bf6a1 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -52,6 +52,7 @@ struct qcom_iommu_dev {
void __iomem*local_base;
u32 sec_id;
u8 num_ctxs;
+ bool use_aarch64_pt;
struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
};
@@ -164,11 +165,17 @@ static void qcom_iommu_tlb_inv_range_nosync(unsigned long
iova, size_t size,
reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
for (i = 0; i < fwspec->num_ids; i++) {
+ struct qcom_iommu_dev *qcom_iommu = qcom_domain->iommu;
struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain,
fwspec->ids[i]);
size_t s = size;
- iova = (iova >> 12) << 12;
- iova |= ctx->asid;
+ if (qcom_iommu->use_aarch64_pt) {
+ iova >>= 12;
+ iova |= (unsigned long)ctx->asid << 48;
+ } else {
+ iova &= (1UL << 12) - 1UL;
+ iova |= ctx->asid;
+ }
do {
iommu_writel(ctx, reg, iova);
iova += granule;
@@ -248,6 +255,8 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
struct io_pgtable_ops *pgtbl_ops;
struct io_pgtable_cfg pgtbl_cfg;
+ enum io_pgtable_fmt pgtbl_fmt;
+ unsigned long ias, oas;
int i, ret = 0;
u32 reg;
@@ -255,10 +264,19 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
if (qcom_domain->iommu)
goto out_unlock;
+ if (qcom_iommu->use_aarch64_pt) {
+ pgtbl_fmt = ARM_64_LPAE_S1;
+ ias = oas = 48;
+ } else {
+ pgtbl_fmt = ARM_32_LPAE_S1;
+ ias = 32;
+ oas = 40;
+ }
+
pgtbl_cfg = (struct io_pgtable_cfg) {
.pgsize_bitmap = qcom_iommu_ops.pgsize_bitmap,
- .ias= 32,
- .oas= 40,
+ .ias= ias,
+ .oas= oas,
.tlb= _flush_ops,
.iommu_dev = qcom_iommu->dev,
};
@@ -266,7 +284,7 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
qcom_domain->iommu = qcom_iommu;
qcom_domain->fwspec = fwspec;
- pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, _cfg,
qcom_domain);
+ pgtbl_ops = alloc_io_pgtable_ops(pgtbl_fmt, _cfg, qcom_domain);
if (!pgtbl_ops) {
dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
ret = -ENOMEM;
@@ -280,6 +298,7 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
for (i = 0; i < fwspec->num_ids; i++
[PATCH 6/6] iommu/qcom: Add support for QCIOMMUv2 and QCIOMMU-500 secured contexts
From: AngeloGioacchino Del Regno
This IOMMU is yet another Qualcomm variant of known IOMMUs, found in
Family-B SoCs, such as MSM8956, MSM8976, MSM8953, MSM8917 and others,
and that firmware perfectly adheres to this driver logic.
This time, though, the catch is that the secure contexts are also
secured, meaning that these are programmed by the bootloader or TZ
and their "interesting" registers are locked out, so the hypervisor
disallows touching them from the non-secure world: in this case
the OS is supposed to blindly trust the secure configuration of
these contexts and just use them "as they are".
For this reason, it is necessary to distinguish between the v1 and
500/v2 secure contexts in this driver in order to adhere to this
specification. To do this, add a new DT compatible, named
"qcom,msm-iommu-v2-sec" that will trigger the new behavior.
For the sake of completeness, also add a "qcom,msm-iommu-v2-ns" so
that the human eye gets pleased with it when reading the contexts
in the final SoC DT. Of course, the latter is just cosmetic.
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 2 ++
drivers/iommu/arm/arm-smmu/qcom_iommu.c| 18 --
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
index 72ae0595efff..861c0cd9c512 100644
--- a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
@@ -36,6 +36,8 @@ to non-secure vs secure interrupt line.
- compatible : Should be one of:
- "qcom,msm-iommu-v1-ns" : non-secure context bank
- "qcom,msm-iommu-v1-sec" : secure context bank
+- "qcom,msm-iommu-v2-ns" : non-secure QSMMUv2/QSMMU500 context bank
+- "qcom,msm-iommu-v2-sec" : secure QSMMUv2/QSMMU500 context bank
- reg: Base address and size of context bank within the iommu
- interrupts : The context fault irq.
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 4fefbab15b71..aa7359ae34a9 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -60,6 +60,7 @@ struct qcom_iommu_ctx {
struct device *dev;
void __iomem*base;
bool secure_init;
+ bool secured_ctx;
u8 asid; /* asid and ctx bank # are 1:1 */
struct iommu_domain *domain;
};
@@ -309,6 +310,12 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
ctx->secure_init = true;
}
+ /* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */
+ if (ctx->secured_ctx) {
+ ctx->domain = domain;
+ break;
+ }
+
qcom_iommu_reset_ctx(ctx);
@@ -751,10 +758,14 @@ static int qcom_iommu_ctx_probe(struct platform_device
*pdev)
if (irq < 0)
return -ENODEV;
+ if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec"))
+ ctx->secured_ctx = true;
+
/* clear IRQs before registering fault handler, just in case the
* boot-loader left us a surprise:
*/
- iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
+ if (!ctx->secured_ctx)
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx,
ARM_SMMU_CB_FSR));
ret = devm_request_irq(dev, irq,
qcom_iommu_fault,
@@ -796,6 +807,8 @@ static int qcom_iommu_ctx_remove(struct platform_device
*pdev)
static const struct of_device_id ctx_of_match[] = {
{ .compatible = "qcom,msm-iommu-v1-ns" },
{ .compatible = "qcom,msm-iommu-v1-sec" },
+ { .compatible = "qcom,msm-iommu-v2-ns" },
+ { .compatible = "qcom,msm-iommu-v2-sec" },
{ /* sentinel */ }
};
@@ -813,7 +826,8 @@ static bool qcom_iommu_has_secure_context(struct
qcom_iommu_dev *qcom_iommu)
struct device_node *child;
for_each_child_of_node(qcom_iommu->dev->of_node, child)
- if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec"))
+ if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") ||
+ of_device_is_compatible(child, "qcom,msm-iommu-v2-sec"))
return true;
return false;
--
2.36.1
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[PATCH 5/6] iommu/qcom: Index contexts by asid number to allow asid 0
From: AngeloGioacchino Del Regno
This driver was indexing the contexts by asid-1, which is probably
done under the assumption that the first ASID is always 1.
Unfortunately this is not entirely true: at least in the MSM8956
and MSM8976 GPU IOMMU, the gpu_user context's ASID number is zero.
To allow using an asid number of zero, stop indexing the contexts
by asid-1 and rather index them by asid.
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 530aa92bf6a1..4fefbab15b71 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -53,7 +53,7 @@ struct qcom_iommu_dev {
u32 sec_id;
u8 num_ctxs;
bool use_aarch64_pt;
- struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
+ struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */
};
struct qcom_iommu_ctx {
@@ -95,7 +95,7 @@ static struct qcom_iommu_ctx * to_ctx(struct
qcom_iommu_domain *d, unsigned asid
struct qcom_iommu_dev *qcom_iommu = d->iommu;
if (!qcom_iommu)
return NULL;
- return qcom_iommu->ctxs[asid - 1];
+ return qcom_iommu->ctxs[asid];
}
static inline void
@@ -614,12 +614,10 @@ static int qcom_iommu_of_xlate(struct device *dev, struct
of_phandle_args *args)
qcom_iommu = platform_get_drvdata(iommu_pdev);
/* make sure the asid specified in dt is valid, so we don't have
-* to sanity check this elsewhere, since 'asid - 1' is used to
-* index into qcom_iommu->ctxs:
+* to sanity check this elsewhere:
*/
- if (WARN_ON(asid < 1) ||
- WARN_ON(asid > qcom_iommu->num_ctxs) ||
- WARN_ON(qcom_iommu->ctxs[asid - 1] == NULL)) {
+ if (WARN_ON(asid >= qcom_iommu->num_ctxs) ||
+ WARN_ON(qcom_iommu->ctxs[asid] == NULL)) {
put_device(_pdev->dev);
return -EINVAL;
}
@@ -778,7 +776,7 @@ static int qcom_iommu_ctx_probe(struct platform_device
*pdev)
dev_dbg(dev, "found asid %u\n", ctx->asid);
- qcom_iommu->ctxs[ctx->asid - 1] = ctx;
+ qcom_iommu->ctxs[ctx->asid] = ctx;
return 0;
}
@@ -790,7 +788,7 @@ static int qcom_iommu_ctx_remove(struct platform_device
*pdev)
platform_set_drvdata(pdev, NULL);
- qcom_iommu->ctxs[ctx->asid - 1] = NULL;
+ qcom_iommu->ctxs[ctx->asid] = NULL;
return 0;
}
@@ -828,7 +826,7 @@ static int qcom_iommu_device_probe(struct platform_device
*pdev)
struct device *dev = >dev;
struct resource *res;
struct clk *clk;
- int ret, max_asid = 0;
+ int ret, num_ctxs, max_asid = 0;
/* find the max asid (which is 1:1 to ctx bank idx), so we know how
* many child ctx devices we have:
@@ -836,11 +834,13 @@ static int qcom_iommu_device_probe(struct platform_device
*pdev)
for_each_child_of_node(dev->of_node, child)
max_asid = max(max_asid, get_asid(child));
- qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid),
+ num_ctxs = max_asid + 1;
+
+ qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, num_ctxs),
GFP_KERNEL);
if (!qcom_iommu)
return -ENOMEM;
- qcom_iommu->num_ctxs = max_asid;
+ qcom_iommu->num_ctxs = num_ctxs;
qcom_iommu->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
2.36.1
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Re: [PATCH 2/2] iommu: arm-smmu-impl: Add SM8450 qcom iommu implementation
On 01.12.2021 08:39, Vinod Koul wrote: > Add SM8450 qcom iommu implementation to the table of > qcom_smmu_impl_of_match table which brings in iommu support for > SM8450 SoC > > Signed-off-by: Vinod Koul > Tested-by: Dmitry Baryshkov > --- With deep pain, as we've had to deal with this for a few generations now.. Acked-by: Konrad Dybcio Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 1/2] dt-bindings: arm-smmu: Add compatible for SM6350 SoC
Add the SoC specific compatible for SM6350 implementing arm,mmu-500. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 03f2b2d4db30..87b93ab3f34e 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -37,6 +37,7 @@ properties: - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 + - qcom,sm6350-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 - qcom,sm8350-smmu-500 -- 2.33.0 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 2/2] iommu/arm-smmu-qcom: Add SM6350 SMMU compatible
Add compatible for SM6350 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 9b9d13ec5a88..b9956294ca2a 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -398,6 +398,7 @@ static const struct of_device_id __maybe_unused
qcom_smmu_impl_of_match[] = {
{ .compatible = "qcom,sdm630-smmu-v2" },
{ .compatible = "qcom,sdm845-smmu-500" },
{ .compatible = "qcom,sm6125-smmu-500" },
+ { .compatible = "qcom,sm6350-smmu-500" },
{ .compatible = "qcom,sm8150-smmu-500" },
{ .compatible = "qcom,sm8250-smmu-500" },
{ .compatible = "qcom,sm8350-smmu-500" },
--
2.33.0
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[PATCH v2] iommu: arm-smmu-qcom: Add sdm630/msm8998 compatibles for qcom quirks
SDM630 and MSM8998 are among the SoCs that use Qualcomm's implementation
of SMMUv2 which has already proven to be problematic over the years. Add
their compatibles to the lookup list to prevent the platforms from being
shut down by the hypervisor at MMU probe.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
Changes since v1:
- Sort the compatibles alphabetically
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 5dff7ffbef11..a833db93e7ff 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -323,7 +323,9 @@ static struct arm_smmu_device *qcom_smmu_create(struct
arm_smmu_device *smmu,
}
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
+ { .compatible = "qcom,msm8998-smmu-v2" },
{ .compatible = "qcom,sc7180-smmu-500" },
+ { .compatible = "qcom,sdm630-smmu-v2" },
{ .compatible = "qcom,sdm845-smmu-500" },
{ .compatible = "qcom,sm8150-smmu-500" },
{ .compatible = "qcom,sm8250-smmu-500" },
--
2.29.2
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[PATCH] iommu: arm-smmu-qcom: Add sdm630/msm8998 compatibles for qcom quirks
SDM630 and MSM8998 are among the SoCs that use Qualcomm's implementation
of SMMUv2 which has already proven to be problematic over the years. Add
their compatibles to the lookup list to prevent the platforms from being
shut down by the hypervisor at MMU probe.
Signed-off-by: Konrad Dybcio
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 5dff7ffbef11..383f3671f5e5 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -323,6 +323,8 @@ static struct arm_smmu_device *qcom_smmu_create(struct
arm_smmu_device *smmu,
}
static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
+ { .compatible = "qcom,sdm630-smmu-v2" },
+ { .compatible = "qcom,msm8998-smmu-v2" },
{ .compatible = "qcom,sc7180-smmu-500" },
{ .compatible = "qcom,sdm845-smmu-500" },
{ .compatible = "qcom,sm8150-smmu-500" },
--
2.29.2
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Re: [PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init
> Sounds like things are progressing nicely for a while there, presumably > until the next time the display is being refreshed. > > Would you be willing to try out the following work in progress: > https://lore.kernel.org/linux-arm-msm/20200717001619.325317-1-bjorn.anders...@linaro.org/ I sure would like to if you could be kind enough to tell me which tree I should apply it against. Latest -next brought some changes to drivers/iommu/ structure which makes this not apply at all :/ Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init
>Is the problem on SDM630 that when you write to SMR/S2CR the device >reboots? Or that when you start writing out the context bank >configuration that trips the display and the device reboots? I added some debug prints and the phone hangs after reaching the seventh CB (with i=6) at arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); line in arm_smmu_device_reset. Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init
>The current >focus has been on moving more of the SMMU specific bits into the arm-smmu-qcom >implementation [1] and I think that is the right way to go. Pardon if I overlooked something obvious, but I can't seem to find a clean way for implementing qcom,skip-init in arm-smmu-qcom, as neither the arm_smmu_test_smr_masks nor the probe function seem to be alterable with arm_smmu_impl. I'm open to your ideas guys. Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init
So.. is this a no-no? I of course would like to omit this entirely, but SMMUs on sdm630 and friends are REALLY picky.. What seems to happen is that when the driver tries to do things the "standard" way, hypervisor decides to hang the platform or force a reboot. Not very usable. This thing is needed for the platform to even boot properly and one more [1] is required to make mdss work with video mode panels (the fact that CMD-mode panels work is kinda hilarious to me). To be honest, there are even more qcom quirks (of which at least qcom,dynamic and qcom-use-3-lvl-tables are used on 630).. [2] Looking forward to your answers and possibly better solutions. [1] https://github.com/konradybcio/linux/commit/83ac38af259968f92b6a8b7eab90096c78469f87 [2] https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.7.1.r1/drivers/iommu/arm-smmu.c#L404-L415 Regards Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init
> It would probably be better to know _which_ context banks we shouldn't > touch, no? Otherwise what happens to the others? > Do we not need to worry about the SMRs as well? This was mimicked from CAF (think [1]) and the SMMUs don't make the hypervisor angry anymore, so I wouldn't be too picky on that if it works.. [1] https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.7.1.r1/drivers/iommu/arm-smmu.c#L4104-L4109 Regards Konrad ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 1/1] iommu/arm-smmu: Implement qcom,skip-init
This adds the downstream property required to support
SMMUs on SDM630 and other platforms (the need for it
most likely depends on firmware configuration).
Signed-off-by: Konrad Dybcio
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 10 ++
drivers/iommu/arm-smmu.c | 15 +--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d7ceb4c34423..9abd6d41a32c 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -102,6 +102,16 @@ properties:
access to SMMU configuration registers. In this case non-secure aliases
of
secure registers have to be used during SMMU configuration.
+ qcom,skip-init:
+description: |
+ Disable resetting configuration for all context banks
+ during device reset. This is useful for targets where
+ some context banks are dedicated to other execution
+ environments outside of Linux and those other EEs are
+ programming their own stream match tables, SCTLR, etc.
+ Without setting this option we will trample on their
+ configuration.
+
stream-match-mask:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 243bc4cb2705..a5c623d4caf9 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1655,13 +1655,16 @@ static void arm_smmu_device_reset(struct
arm_smmu_device *smmu)
* Reset stream mapping groups: Initial values mark all SMRn as
* invalid and all S2CRn as bypass unless overridden.
*/
- for (i = 0; i < smmu->num_mapping_groups; ++i)
- arm_smmu_write_sme(smmu, i);
- /* Make sure all context banks are disabled and clear CB_FSR */
- for (i = 0; i < smmu->num_context_banks; ++i) {
- arm_smmu_write_context_bank(smmu, i);
- arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
+ if (!of_find_property(smmu->dev->of_node, "qcom,skip-init", NULL)) {
+ for (i = 0; i < smmu->num_mapping_groups; ++i)
+ arm_smmu_write_sme(smmu, i);
+
+ /* Make sure all context banks are disabled and clear CB_FSR */
+ for (i = 0; i < smmu->num_context_banks; ++i) {
+ arm_smmu_write_context_bank(smmu, i);
+ arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR,
ARM_SMMU_FSR_FAULT);
+ }
}
/* Invalidate the TLB, just in case */
--
2.27.0
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