[PATCH 01/10] ARM: sa1100/assabet: move dmabounce hack to ohci driver
From: Arnd Bergmann The sa platform is one of the two remaining users of the old Arm specific "dmabounce" code, which is an earlier implementation of the generic swiotlb. Linus Walleij submitted a patch that removes dmabounce support from the ixp4xx, and I had a look at the other user, which is the sa companion chip. Looking at how dmabounce is used, I could narrow it down to one driver one three machines: - dmabounce is only initialized on assabet/neponset, jornada720 and badge4, which are the platforms that have an sa and support DMA on it. - All three of these suffer from "erratum #7" that requires only doing DMA to half the memory sections based on one of the address lines, in addition, the neponset also can't DMA to the RAM that is connected to sa itself. - the pxa lubbock machine also has sa, but does not support DMA on it and does not set dmabounce. - only the OHCI and audio devices on sa support DMA, but as there is no audio driver for this hardware, only OHCI remains. In the OHCI code, I noticed that two other platforms already have a local bounce buffer support in the form of the "local_mem" allocator. Specifically, TMIO and SM501 use this on a few other ARM boards with 16KB or 128KB of local SRAM that can be accessed from the OHCI and from the CPU. While this is not the same problem as on sa, I could not find a reason why we can't re-use the existing implementation but replace the physical SRAM address mapping with a locally allocated DMA buffer. There are two main downsides: - rather than using a dynamically sized pool, this buffer needs to be allocated at probe time using a fixed size. Without having any idea of what it should be, I picked a size of 64KB, which is between what the other two OHCI front-ends use in their SRAM. If anyone has a better idea what that size is reasonable, this can be trivially changed. - Previously, only USB transfers to unaddressable memory needed to go through the bounce buffer, now all of them do, which may impact runtime performance for USB endpoints that do a lot of transfers. On the upside, the local_mem support uses write-combining buffers, which should be a bit faster for transfers to the device compared to normal uncached coherent memory as used in dmabounce. Cc: Linus Walleij Cc: Russell King Cc: Christoph Hellwig Cc: Laurentiu Tudor Cc: linux-...@vger.kernel.org Signed-off-by: Arnd Bergmann Reviewed-by: Greg Kroah-Hartman Acked-by: Alan Stern Signed-off-by: Christoph Hellwig --- arch/arm/common/Kconfig| 2 +- arch/arm/common/sa.c | 64 -- drivers/usb/core/hcd.c | 17 +++-- drivers/usb/host/ohci-sa.c | 25 + 4 files changed, 40 insertions(+), 68 deletions(-) diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index c8e198631d418..bc158fd227e12 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config SA bool - select DMABOUNCE if !ARCH_PXA + select ZONE_DMA if ARCH_SA1100 config DMABOUNCE bool diff --git a/arch/arm/common/sa.c b/arch/arm/common/sa.c index 2343e2b6214d7..f5e6990b8856b 100644 --- a/arch/arm/common/sa.c +++ b/arch/arm/common/sa.c @@ -1389,70 +1389,9 @@ void sa_driver_unregister(struct sa_driver *driver) } EXPORT_SYMBOL(sa_driver_unregister); -#ifdef CONFIG_DMABOUNCE -/* - * According to the "Intel StrongARM SA- Microprocessor Companion - * Chip Specification Update" (June 2000), erratum #7, there is a - * significant bug in the SA SDRAM shared memory controller. If - * an access to a region of memory above 1MB relative to the bank base, - * it is important that address bit 10 _NOT_ be asserted. Depending - * on the configuration of the RAM, bit 10 may correspond to one - * of several different (processor-relative) address bits. - * - * This routine only identifies whether or not a given DMA address - * is susceptible to the bug. - * - * This should only get called for sa_device types due to the - * way we configure our device dma_masks. - */ -static int sa_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) -{ - /* -* Section 4.6 of the "Intel StrongARM SA- Development Module -* User's Guide" mentions that jumpers R51 and R52 control the -* target of SA- DMA (either SDRAM bank 0 on Assabet, or -* SDRAM bank 1 on Neponset). The default configuration selects -* Assabet, so any address in bank 1 is necessarily invalid. -*/ - return (machine_is_assabet() || machine_is_pfs168()) && - (addr >= 0xc800 || (addr + size) >= 0xc800); -} - -static int sa_notifier_call(struct notifier_block *n, unsigned long action, - void *data) -{ - struct sa_dev *dev = to_sa_device(data); - -
[PATCH 01/10] ARM: sa1100/assabet: move dmabounce hack to ohci driver
From: Arnd Bergmann The sa platform is one of the two remaining users of the old Arm specific "dmabounce" code, which is an earlier implementation of the generic swiotlb. Linus Walleij submitted a patch that removes dmabounce support from the ixp4xx, and I had a look at the other user, which is the sa companion chip. Looking at how dmabounce is used, I could narrow it down to one driver one three machines: - dmabounce is only initialized on assabet/neponset, jornada720 and badge4, which are the platforms that have an sa and support DMA on it. - All three of these suffer from "erratum #7" that requires only doing DMA to half the memory sections based on one of the address lines, in addition, the neponset also can't DMA to the RAM that is connected to sa itself. - the pxa lubbock machine also has sa, but does not support DMA on it and does not set dmabounce. - only the OHCI and audio devices on sa support DMA, but as there is no audio driver for this hardware, only OHCI remains. In the OHCI code, I noticed that two other platforms already have a local bounce buffer support in the form of the "local_mem" allocator. Specifically, TMIO and SM501 use this on a few other ARM boards with 16KB or 128KB of local SRAM that can be accessed from the OHCI and from the CPU. While this is not the same problem as on sa, I could not find a reason why we can't re-use the existing implementation but replace the physical SRAM address mapping with a locally allocated DMA buffer. There are two main downsides: - rather than using a dynamically sized pool, this buffer needs to be allocated at probe time using a fixed size. Without having any idea of what it should be, I picked a size of 64KB, which is between what the other two OHCI front-ends use in their SRAM. If anyone has a better idea what that size is reasonable, this can be trivially changed. - Previously, only USB transfers to unaddressable memory needed to go through the bounce buffer, now all of them do, which may impact runtime performance for USB endpoints that do a lot of transfers. On the upside, the local_mem support uses write-combining buffers, which should be a bit faster for transfers to the device compared to normal uncached coherent memory as used in dmabounce. Cc: Linus Walleij Cc: Russell King Cc: Christoph Hellwig Cc: Laurentiu Tudor Cc: linux-...@vger.kernel.org Signed-off-by: Arnd Bergmann Reviewed-by: Greg Kroah-Hartman Acked-by: Alan Stern Signed-off-by: Christoph Hellwig --- arch/arm/common/Kconfig| 2 +- arch/arm/common/sa.c | 64 -- drivers/usb/core/hcd.c | 17 +++-- drivers/usb/host/ohci-sa.c | 25 + 4 files changed, 40 insertions(+), 68 deletions(-) diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index c8e198631d418..bc158fd227e12 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config SA bool - select DMABOUNCE if !ARCH_PXA + select ZONE_DMA if ARCH_SA1100 config DMABOUNCE bool diff --git a/arch/arm/common/sa.c b/arch/arm/common/sa.c index 5367f03beb468..eaf2b527b0673 100644 --- a/arch/arm/common/sa.c +++ b/arch/arm/common/sa.c @@ -1386,70 +1386,9 @@ void sa_driver_unregister(struct sa_driver *driver) } EXPORT_SYMBOL(sa_driver_unregister); -#ifdef CONFIG_DMABOUNCE -/* - * According to the "Intel StrongARM SA- Microprocessor Companion - * Chip Specification Update" (June 2000), erratum #7, there is a - * significant bug in the SA SDRAM shared memory controller. If - * an access to a region of memory above 1MB relative to the bank base, - * it is important that address bit 10 _NOT_ be asserted. Depending - * on the configuration of the RAM, bit 10 may correspond to one - * of several different (processor-relative) address bits. - * - * This routine only identifies whether or not a given DMA address - * is susceptible to the bug. - * - * This should only get called for sa_device types due to the - * way we configure our device dma_masks. - */ -static int sa_needs_bounce(struct device *dev, dma_addr_t addr, size_t size) -{ - /* -* Section 4.6 of the "Intel StrongARM SA- Development Module -* User's Guide" mentions that jumpers R51 and R52 control the -* target of SA- DMA (either SDRAM bank 0 on Assabet, or -* SDRAM bank 1 on Neponset). The default configuration selects -* Assabet, so any address in bank 1 is necessarily invalid. -*/ - return (machine_is_assabet() || machine_is_pfs168()) && - (addr >= 0xc800 || (addr + size) >= 0xc800); -} - -static int sa_notifier_call(struct notifier_block *n, unsigned long action, - void *data) -{ - struct sa_dev *dev = to_sa_device(data); - -