Re: [PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
On Wed, 30 Jun 2021 10:34:41 +0800, Yong Wu wrote: > This patch adds descriptions for mt8195 IOMMU which also use ARM > Short-Descriptor translation table format. > > In mt8195, there are two smi-common HW and IOMMU, one is for vdo(video > output), the other is for vpp(video processing pipe). They connects > with different smi-larbs, then some setting(larbid_remap) is different. > Differentiate them with the compatible string. > > Something like this: > > IOMMU(VDO) IOMMU(VPP) >| | > SMI_COMMON_VDO SMI_COMMON_VPP > --- > | | ... | | ... > larb0 larb2 ...larb1 larb3... > > Another change is that we have a new IOMMU that is for infra master like > PCIe and USB. The infra master don't have the larb and ports, thus we > rename the port header file to mt8195-memory-port.h rather than > mt8195-larb-port.h. > > Also, the IOMMU is not only for MM, thus, we don't call it "m4u" which > means "MultiMedia Memory Management UNIT". thus, use the "iommu" as the > compatiable string. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.yaml| 7 + > .../dt-bindings/memory/mt8195-memory-port.h | 390 ++ > 2 files changed, 397 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8195-memory-port.h > Reviewed-by: Rob Herring ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
On Wed, 2021-06-30 at 08:26 +0200, Krzysztof Kozlowski wrote: > On 30/06/2021 04:34, Yong Wu wrote: > > This patch adds descriptions for mt8195 IOMMU which also use ARM > > Short-Descriptor translation table format. > > > > In mt8195, there are two smi-common HW and IOMMU, one is for vdo(video > > output), the other is for vpp(video processing pipe). They connects > > with different smi-larbs, then some setting(larbid_remap) is different. > > Differentiate them with the compatible string. > > > > Something like this: > > > > IOMMU(VDO) IOMMU(VPP) > >| | > > SMI_COMMON_VDO SMI_COMMON_VPP > > --- > > | | ... | | ... > > larb0 larb2 ...larb1 larb3... > > > > Another change is that we have a new IOMMU that is for infra master like > > PCIe and USB. The infra master don't have the larb and ports, thus we > > rename the port header file to mt8195-memory-port.h rather than > > mt8195-larb-port.h. > > > > Also, the IOMMU is not only for MM, thus, we don't call it "m4u" which > > means "MultiMedia Memory Management UNIT". thus, use the "iommu" as the > > compatiable string. > > > > Signed-off-by: Yong Wu > > --- > > .../bindings/iommu/mediatek,iommu.yaml| 7 + > > .../dt-bindings/memory/mt8195-memory-port.h | 390 ++ > > 2 files changed, 397 insertions(+) > > create mode 100644 include/dt-bindings/memory/mt8195-memory-port.h > > > > I understand this will go through IOMMU tree. Do you know about any > further patches for memory controllers which will need the header? This header file will only be used in dtsi file. the iommu masters will use these port definitions in the dtsi. The SMI driver no need include this header file. By the way, the mt8195 SMI patches is at: https://lore.kernel.org/linux-mediatek/20210616114346.18812-1-yong...@mediatek.com/ > > Acked-by: Krzysztof Kozlowski Thanks very much for your quick review. > > > Best regards, > Krzysztof > > ___ > Linux-mediatek mailing list > linux-media...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
On 30/06/2021 04:34, Yong Wu wrote: > This patch adds descriptions for mt8195 IOMMU which also use ARM > Short-Descriptor translation table format. > > In mt8195, there are two smi-common HW and IOMMU, one is for vdo(video > output), the other is for vpp(video processing pipe). They connects > with different smi-larbs, then some setting(larbid_remap) is different. > Differentiate them with the compatible string. > > Something like this: > > IOMMU(VDO) IOMMU(VPP) >| | > SMI_COMMON_VDO SMI_COMMON_VPP > --- > | | ... | | ... > larb0 larb2 ...larb1 larb3... > > Another change is that we have a new IOMMU that is for infra master like > PCIe and USB. The infra master don't have the larb and ports, thus we > rename the port header file to mt8195-memory-port.h rather than > mt8195-larb-port.h. > > Also, the IOMMU is not only for MM, thus, we don't call it "m4u" which > means "MultiMedia Memory Management UNIT". thus, use the "iommu" as the > compatiable string. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.yaml| 7 + > .../dt-bindings/memory/mt8195-memory-port.h | 390 ++ > 2 files changed, 397 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8195-memory-port.h > I understand this will go through IOMMU tree. Do you know about any further patches for memory controllers which will need the header? Acked-by: Krzysztof Kozlowski Best regards, Krzysztof ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU
This patch adds descriptions for mt8195 IOMMU which also use ARM Short-Descriptor translation table format. In mt8195, there are two smi-common HW and IOMMU, one is for vdo(video output), the other is for vpp(video processing pipe). They connects with different smi-larbs, then some setting(larbid_remap) is different. Differentiate them with the compatible string. Something like this: IOMMU(VDO) IOMMU(VPP) | | SMI_COMMON_VDO SMI_COMMON_VPP --- | | ... | | ... larb0 larb2 ...larb1 larb3... Another change is that we have a new IOMMU that is for infra master like PCIe and USB. The infra master don't have the larb and ports, thus we rename the port header file to mt8195-memory-port.h rather than mt8195-larb-port.h. Also, the IOMMU is not only for MM, thus, we don't call it "m4u" which means "MultiMedia Memory Management UNIT". thus, use the "iommu" as the compatiable string. Signed-off-by: Yong Wu --- .../bindings/iommu/mediatek,iommu.yaml| 7 + .../dt-bindings/memory/mt8195-memory-port.h | 390 ++ 2 files changed, 397 insertions(+) create mode 100644 include/dt-bindings/memory/mt8195-memory-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 0f26fe14c8e2..9b04630158c8 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -77,6 +77,8 @@ properties: - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two - mediatek,mt8192-m4u # generation two + - mediatek,mt8195-iommu-vdo# generation two + - mediatek,mt8195-iommu-vpp# generation two - description: mt7623 generation one items: @@ -118,6 +120,7 @@ properties: dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, dt-binding/memory/mt8192-larb-port.h for mt8192. + dt-binding/memory/mt8195-memory-port.h for mt8195. power-domains: maxItems: 1 @@ -139,6 +142,8 @@ allOf: - mediatek,mt2712-m4u - mediatek,mt8173-m4u - mediatek,mt8192-m4u + - mediatek,mt8195-iommu-vdo + - mediatek,mt8195-iommu-vpp then: required: @@ -149,6 +154,8 @@ allOf: compatible: enum: - mediatek,mt8192-m4u +- mediatek,mt8195-iommu-vdo +- mediatek,mt8195-iommu-vpp then: required: diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h new file mode 100644 index ..783bcae8cdea --- /dev/null +++ b/include/dt-bindings/memory/mt8195-memory-port.h @@ -0,0 +1,390 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Yong Wu + */ +#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ +#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ + +#include + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G. we could adjust these master + * locate an banks. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modulesdma-address-region larbs-ports + * disp 0 ~ 4G larb0/1/2/3 + * vcodec 4G ~ 8G larb19/20/21/22/23/24 + * cam/mdp 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + * CCU0 0x24000_ ~ 0x243ff_ larb18: port 0/1 + * CCU1 0x24400_ ~ 0x247ff_ larb18: port 2/3 + * + * This SoC have two IOMMU HWs, this is the detailed connected information: + * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28 + * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 + */ + +/* mm iommu ports */ +/* larb0 */ +#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0) +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1) +#define M4U_PORT_L0_DISP_OVL0_RDMA0MTK_M4U_ID(0, 2) +#define M4U_PORT_L0_DISP_OVL0_RDMA1MTK_M4U_ID(0, 3) +#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4) +#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) + +/* larb1 */ +#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0) +#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1) +#define M4U_PORT_L1_DISP_OVL0_RDMA0MTK_M4U_ID(1, 2) +#define M4U_PORT_L1_DISP_OVL0_RDMA1MTK_M4U_ID(1, 3) +#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4) +#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5) + +/* larb2 */ +#define M4U_PORT_L2_MDP_RDMA0 MT
