Re: (subset) [PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables.

[Bjorn Andersson]

On Tue, 14 Jun 2022 16:01:36 -0700, Emma Anholt wrote:
> This is an SMMU for the adreno gpu, and adding this compatible lets
> the driver use per-fd page tables, which are required for security
> between GPU clients.
> 
> 

Applied, thanks!

[2/2] arm64: dts: qcom: sm8250: Enable per-process page tables.
  commit: 213d7368723709cf4567488e63dd667802378202

Best regards,
-- 
Bjorn Andersson 
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Re: [PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables.

[Dmitry Baryshkov]

On Wed, 15 Jun 2022 at 02:01, Emma Anholt  wrote:
>
> This is an SMMU for the adreno gpu, and adding this compatible lets
> the driver use per-fd page tables, which are required for security
> between GPU clients.
>
> Signed-off-by: Emma Anholt 
> ---
>
> Tested with a full deqp-vk run on RB5, which did involve some iommu faults.
>
>  arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi 
> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index a92230bec1dd..483c0e0f1d1a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d9 {
> };
>
> adreno_smmu: iommu@3da {
> -   compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
> +   compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", 
> "qcom,adreno-smmu";

I see that other dtsi files use a bit different order for the
compatibility strings. They put "qcom,adreno-smmu" before
"arm,mmu-500". Can we please follow them?

With that fixed:
Reviewed-by: Dmitry Baryshkov 

> reg = <0 0x03da 0 0x1>;
> #iommu-cells = <2>;
> #global-interrupts = <2>;
> --
> 2.36.1
>


-- 
With best wishes
Dmitry
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[PATCH 2/2] arm64: dts: qcom: sm8250: Enable per-process page tables.

[Emma Anholt]

This is an SMMU for the adreno gpu, and adding this compatible lets
the driver use per-fd page tables, which are required for security
between GPU clients.

Signed-off-by: Emma Anholt 
---

Tested with a full deqp-vk run on RB5, which did involve some iommu faults.

 arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi 
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index a92230bec1dd..483c0e0f1d1a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2513,7 +2513,7 @@ gpucc: clock-controller@3d9 {
};
 
adreno_smmu: iommu@3da {
-   compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
+   compatible = "qcom,sm8250-smmu-500", "arm,mmu-500", 
"qcom,adreno-smmu";
reg = <0 0x03da 0 0x1>;
#iommu-cells = <2>;
#global-interrupts = <2>;
-- 
2.36.1

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